Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[deliverable/linux.git] / include / asm-sparc64 / pgtable.h
1 /* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
10
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
15 #include <asm-generic/pgtable-nopud.h>
16
17 #include <linux/config.h>
18 #include <linux/compiler.h>
19 #include <asm/types.h>
20 #include <asm/spitfire.h>
21 #include <asm/asi.h>
22 #include <asm/system.h>
23 #include <asm/page.h>
24 #include <asm/processor.h>
25 #include <asm/const.h>
26
27 /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
28 * The page copy blockops can use 0x2000000 to 0x10000000.
29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
30 * The vmalloc area spans 0x100000000 to 0x200000000.
31 * Since modules need to be in the lowest 32-bits of the address space,
32 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
33 * There is a single static kernel PMD which maps from 0x0 to address
34 * 0x400000000.
35 */
36 #define TLBTEMP_BASE _AC(0x0000000002000000,UL)
37 #define MODULES_VADDR _AC(0x0000000010000000,UL)
38 #define MODULES_LEN _AC(0x00000000e0000000,UL)
39 #define MODULES_END _AC(0x00000000f0000000,UL)
40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42 #define VMALLOC_START _AC(0x0000000100000000,UL)
43 #define VMALLOC_END _AC(0x0000000200000000,UL)
44
45 /* XXX All of this needs to be rethought so we can take advantage
46 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
47 * XXX in the middle like on spitfire. -DaveM
48 */
49 /*
50 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
51 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
52 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
53 * table is a single page long). The next higher PMD_BITS determine pmd#
54 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
55 * since the pmd entries are 4 bytes, and each pmd page is a single page
56 * long). Finally, the higher few bits determine pgde#.
57 */
58
59 /* PMD_SHIFT determines the size of the area a second-level page
60 * table can map
61 */
62 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
63 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
64 #define PMD_MASK (~(PMD_SIZE-1))
65 #define PMD_BITS (PAGE_SHIFT - 2)
66
67 /* PGDIR_SHIFT determines what a third-level page table entry can map */
68 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
69 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
70 #define PGDIR_MASK (~(PGDIR_SIZE-1))
71 #define PGDIR_BITS (PAGE_SHIFT - 2)
72
73 #ifndef __ASSEMBLY__
74
75 #include <linux/sched.h>
76
77 /* Entries per page directory level. */
78 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
79 #define PTRS_PER_PMD (1UL << PMD_BITS)
80 #define PTRS_PER_PGD (1UL << PGDIR_BITS)
81
82 /* Kernel has a separate 44bit address space. */
83 #define FIRST_USER_ADDRESS 0
84
85 #define pte_ERROR(e) __builtin_trap()
86 #define pmd_ERROR(e) __builtin_trap()
87 #define pgd_ERROR(e) __builtin_trap()
88
89 #endif /* !(__ASSEMBLY__) */
90
91 /* Spitfire/Cheetah TTE bits. */
92 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
93 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit up to date*/
94 #define _PAGE_SZ4MB _AC(0x6000000000000000,UL) /* 4MB Page */
95 #define _PAGE_SZ512K _AC(0x4000000000000000,UL) /* 512K Page */
96 #define _PAGE_SZ64K _AC(0x2000000000000000,UL) /* 64K Page */
97 #define _PAGE_SZ8K _AC(0x0000000000000000,UL) /* 8K Page */
98 #define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */
99 #define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */
100 #define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
101 #define _PAGE_RES1 _AC(0x0002000000000000,UL) /* Reserved */
102 #define _PAGE_SZ32MB _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
103 #define _PAGE_SZ256MB _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
104 #define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
105 #define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */
106 #define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/
107 #define _PAGE_PADDR _AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr[42:13] */
108 #define _PAGE_SOFT _AC(0x0000000000001F80,UL) /* Software bits */
109 #define _PAGE_L _AC(0x0000000000000040,UL) /* Locked TTE */
110 #define _PAGE_CP _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
111 #define _PAGE_CV _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
112 #define _PAGE_E _AC(0x0000000000000008,UL) /* side-Effect */
113 #define _PAGE_P _AC(0x0000000000000004,UL) /* Privileged Page */
114 #define _PAGE_W _AC(0x0000000000000002,UL) /* Writable */
115 #define _PAGE_G _AC(0x0000000000000001,UL) /* Global */
116
117 /* Here are the SpitFire software bits we use in the TTE's.
118 *
119 * WARNING: If you are going to try and start using some
120 * of the soft2 bits, you will need to make
121 * modifications to the swap entry implementation.
122 * For example, one thing that could happen is that
123 * swp_entry_to_pte() would BUG_ON() if you tried
124 * to use one of the soft2 bits for _PAGE_FILE.
125 *
126 * Like other architectures, I have aliased _PAGE_FILE with
127 * _PAGE_MODIFIED. This works because _PAGE_FILE is never
128 * interpreted that way unless _PAGE_PRESENT is clear.
129 */
130 #define _PAGE_EXEC _AC(0x0000000000001000,UL) /* Executable SW bit */
131 #define _PAGE_MODIFIED _AC(0x0000000000000800,UL) /* Modified (dirty) */
132 #define _PAGE_FILE _AC(0x0000000000000800,UL) /* Pagecache page */
133 #define _PAGE_ACCESSED _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
134 #define _PAGE_READ _AC(0x0000000000000200,UL) /* Readable SW Bit */
135 #define _PAGE_WRITE _AC(0x0000000000000100,UL) /* Writable SW Bit */
136 #define _PAGE_PRESENT _AC(0x0000000000000080,UL) /* Present */
137
138 #if PAGE_SHIFT == 13
139 #define _PAGE_SZBITS _PAGE_SZ8K
140 #elif PAGE_SHIFT == 16
141 #define _PAGE_SZBITS _PAGE_SZ64K
142 #elif PAGE_SHIFT == 19
143 #define _PAGE_SZBITS _PAGE_SZ512K
144 #elif PAGE_SHIFT == 22
145 #define _PAGE_SZBITS _PAGE_SZ4MB
146 #else
147 #error Wrong PAGE_SHIFT specified
148 #endif
149
150 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
151 #define _PAGE_SZHUGE _PAGE_SZ4MB
152 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
153 #define _PAGE_SZHUGE _PAGE_SZ512K
154 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
155 #define _PAGE_SZHUGE _PAGE_SZ64K
156 #endif
157
158 #define _PAGE_CACHE (_PAGE_CP | _PAGE_CV)
159
160 #define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W)
161 #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
162 #define __PRIV_BITS _PAGE_P
163
164 #define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_CACHE)
165
166 /* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */
167 #define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
168 __ACCESS_BITS | _PAGE_WRITE | _PAGE_EXEC)
169
170 #define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
171 __ACCESS_BITS | _PAGE_EXEC)
172
173 #define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
174 __ACCESS_BITS | _PAGE_EXEC)
175
176 #define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
177 __PRIV_BITS | \
178 __ACCESS_BITS | __DIRTY_BITS | _PAGE_EXEC)
179
180 #define PAGE_SHARED_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
181 _PAGE_CACHE | \
182 __ACCESS_BITS | _PAGE_WRITE)
183
184 #define PAGE_COPY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
185 _PAGE_CACHE | __ACCESS_BITS)
186
187 #define PAGE_READONLY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
188 _PAGE_CACHE | __ACCESS_BITS)
189
190 #define _PFN_MASK _PAGE_PADDR
191
192 #define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \
193 __ACCESS_BITS | _PAGE_E)
194
195 #define __P000 PAGE_NONE
196 #define __P001 PAGE_READONLY_NOEXEC
197 #define __P010 PAGE_COPY_NOEXEC
198 #define __P011 PAGE_COPY_NOEXEC
199 #define __P100 PAGE_READONLY
200 #define __P101 PAGE_READONLY
201 #define __P110 PAGE_COPY
202 #define __P111 PAGE_COPY
203
204 #define __S000 PAGE_NONE
205 #define __S001 PAGE_READONLY_NOEXEC
206 #define __S010 PAGE_SHARED_NOEXEC
207 #define __S011 PAGE_SHARED_NOEXEC
208 #define __S100 PAGE_READONLY
209 #define __S101 PAGE_READONLY
210 #define __S110 PAGE_SHARED
211 #define __S111 PAGE_SHARED
212
213 #ifndef __ASSEMBLY__
214
215 extern unsigned long phys_base;
216 extern unsigned long pfn_base;
217
218 extern struct page *mem_map_zero;
219 #define ZERO_PAGE(vaddr) (mem_map_zero)
220
221 /* PFNs are real physical page numbers. However, mem_map only begins to record
222 * per-page information starting at pfn_base. This is to handle systems where
223 * the first physical page in the machine is at some huge physical address,
224 * such as 4GB. This is common on a partitioned E10000, for example.
225 */
226
227 #define pfn_pte(pfn, prot) \
228 __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot) | _PAGE_SZBITS)
229 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
230
231 #define pte_pfn(x) ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT)
232 #define pte_page(x) pfn_to_page(pte_pfn(x))
233
234 #define page_pte_prot(page, prot) mk_pte(page, prot)
235 #define page_pte(page) page_pte_prot(page, __pgprot(0))
236
237 static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
238 {
239 pte_t __pte;
240 const unsigned long preserve_mask = (_PFN_MASK |
241 _PAGE_MODIFIED | _PAGE_ACCESSED |
242 _PAGE_CACHE | _PAGE_E |
243 _PAGE_PRESENT | _PAGE_SZBITS);
244
245 pte_val(__pte) = (pte_val(orig_pte) & preserve_mask) |
246 (pgprot_val(new_prot) & ~preserve_mask);
247
248 return __pte;
249 }
250 #define pmd_set(pmdp, ptep) \
251 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
252 #define pud_set(pudp, pmdp) \
253 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
254 #define __pmd_page(pmd) \
255 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
256 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
257 #define pud_page(pud) \
258 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
259 #define pte_none(pte) (!pte_val(pte))
260 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
261 #define pmd_none(pmd) (!pmd_val(pmd))
262 #define pmd_bad(pmd) (0)
263 #define pmd_present(pmd) (pmd_val(pmd) != 0U)
264 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
265 #define pud_none(pud) (!pud_val(pud))
266 #define pud_bad(pud) (0)
267 #define pud_present(pud) (pud_val(pud) != 0U)
268 #define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
269
270 /* The following only work if pte_present() is true.
271 * Undefined behaviour if not..
272 */
273 #define pte_read(pte) (pte_val(pte) & _PAGE_READ)
274 #define pte_exec(pte) (pte_val(pte) & _PAGE_EXEC)
275 #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
276 #define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
277 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
278 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
279 #define pte_rdprotect(pte) \
280 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
281 #define pte_mkclean(pte) \
282 (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
283 #define pte_mkold(pte) \
284 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
285
286 /* Permanent address of a page. */
287 #define __page_address(page) page_address(page)
288
289 /* Be very careful when you change these three, they are delicate. */
290 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
291 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE))
292 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
293 #define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_SZHUGE))
294
295 /* to find an entry in a page-table-directory. */
296 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
297 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
298
299 /* to find an entry in a kernel page-table-directory */
300 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
301
302 /* extract the pgd cache used for optimizing the tlb miss
303 * slow path when executing 32-bit compat processes
304 */
305 #define get_pgd_cache(pgd) ((unsigned long) pgd_val(*pgd) << 11)
306
307 /* Find an entry in the second-level page table.. */
308 #define pmd_offset(pudp, address) \
309 ((pmd_t *) pud_page(*(pudp)) + \
310 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
311
312 /* Find an entry in the third-level page table.. */
313 #define pte_index(dir, address) \
314 ((pte_t *) __pmd_page(*(dir)) + \
315 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
316 #define pte_offset_kernel pte_index
317 #define pte_offset_map pte_index
318 #define pte_offset_map_nested pte_index
319 #define pte_unmap(pte) do { } while (0)
320 #define pte_unmap_nested(pte) do { } while (0)
321
322 /* Actual page table PTE updates. */
323 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
324
325 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
326 {
327 pte_t orig = *ptep;
328
329 *ptep = pte;
330
331 /* It is more efficient to let flush_tlb_kernel_range()
332 * handle init_mm tlb flushes.
333 */
334 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
335 tlb_batch_add(mm, addr, ptep, orig);
336 }
337
338 #define pte_clear(mm,addr,ptep) \
339 set_pte_at((mm), (addr), (ptep), __pte(0UL))
340
341 extern pgd_t swapper_pg_dir[2048];
342 extern pmd_t swapper_low_pmd_dir[2048];
343
344 extern void paging_init(void);
345 extern unsigned long find_ecache_flush_span(unsigned long size);
346
347 /* These do nothing with the way I have things setup. */
348 #define mmu_lockarea(vaddr, len) (vaddr)
349 #define mmu_unlockarea(vaddr, len) do { } while(0)
350
351 struct vm_area_struct;
352 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
353
354 /* Make a non-present pseudo-TTE. */
355 static inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
356 {
357 pte_t pte;
358 pte_val(pte) = (((page) | pgprot_val(prot) | _PAGE_E) &
359 ~(unsigned long)_PAGE_CACHE);
360 pte_val(pte) |= (((unsigned long)space) << 32);
361 return pte;
362 }
363
364 /* Encode and de-code a swap entry */
365 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
366 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
367 #define __swp_entry(type, offset) \
368 ( (swp_entry_t) \
369 { \
370 (((long)(type) << PAGE_SHIFT) | \
371 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
372 } )
373 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
374 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
375
376 /* File offset in PTE support. */
377 #define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
378 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
379 #define pgoff_to_pte(off) (__pte(((off) << PAGE_SHIFT) | _PAGE_FILE))
380 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
381
382 extern unsigned long prom_virt_to_phys(unsigned long, int *);
383
384 static __inline__ unsigned long
385 sun4u_get_pte (unsigned long addr)
386 {
387 pgd_t *pgdp;
388 pud_t *pudp;
389 pmd_t *pmdp;
390 pte_t *ptep;
391
392 if (addr >= PAGE_OFFSET)
393 return addr & _PAGE_PADDR;
394 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
395 return prom_virt_to_phys(addr, NULL);
396 pgdp = pgd_offset_k(addr);
397 pudp = pud_offset(pgdp, addr);
398 pmdp = pmd_offset(pudp, addr);
399 ptep = pte_offset_kernel(pmdp, addr);
400 return pte_val(*ptep) & _PAGE_PADDR;
401 }
402
403 static __inline__ unsigned long
404 __get_phys (unsigned long addr)
405 {
406 return sun4u_get_pte (addr);
407 }
408
409 static __inline__ int
410 __get_iospace (unsigned long addr)
411 {
412 return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
413 }
414
415 extern unsigned long *sparc64_valid_addr_bitmap;
416
417 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
418 #define kern_addr_valid(addr) \
419 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
420
421 extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
422 unsigned long pfn,
423 unsigned long size, pgprot_t prot);
424
425 /* Clear virtual and physical cachability, set side-effect bit. */
426 #define pgprot_noncached(prot) \
427 (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \
428 _PAGE_E))
429
430 /*
431 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
432 * its high 4 bits. These macros/functions put it there or get it from there.
433 */
434 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
435 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
436 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
437
438 #include <asm-generic/pgtable.h>
439
440 /* We provide our own get_unmapped_area to cope with VA holes for userland */
441 #define HAVE_ARCH_UNMAPPED_AREA
442
443 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
444 * the largest alignment possible such that larget PTEs can be used.
445 */
446 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
447 unsigned long, unsigned long,
448 unsigned long);
449 #define HAVE_ARCH_FB_UNMAPPED_AREA
450
451 /*
452 * No page table caches to initialise
453 */
454 #define pgtable_cache_init() do { } while (0)
455
456 extern void check_pgt_cache(void);
457
458 #endif /* !(__ASSEMBLY__) */
459
460 #endif /* !(_SPARC64_PGTABLE_H) */
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