include/asm-x86/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/pm.h>
   5 #include <linux/delay.h>
   6 #include <asm/fixmap.h>
   7 #include <asm/apicdef.h>
   8 #include <asm/processor.h>
   9 #include <asm/system.h>
  10 #include <asm/cpufeature.h>
  11 #include <asm/msr.h>
  12
  13 #define ARCH_APICTIMER_STOPS_ON_C3      1
  14
  15 #define Dprintk(x...)
  16
  17 /*
  18  * Debugging macros
  19  */
  20 #define APIC_QUIET   0
  21 #define APIC_VERBOSE 1
  22 #define APIC_DEBUG   2
  23
  24 /*
  25  * Define the default level of output to be very little
  26  * This can be turned up by using apic=verbose for more
  27  * information and apic=debug for _lots_ of information.
  28  * apic_verbosity is defined in apic.c
  29  */
  30 #define apic_printk(v, s, a...) do {       \
  31                 if ((v) <= apic_verbosity) \
  32                         printk(s, ##a);    \
  33         } while (0)
  34
  35
  36 extern void generic_apic_probe(void);
  37
  38 #ifdef CONFIG_X86_LOCAL_APIC
  39
  40 extern int apic_verbosity;
  41 extern int local_apic_timer_c2_ok;
  42
  43 extern int ioapic_force;
  44
  45 extern int disable_apic;
  46 /*
  47  * Basic functions accessing APICs.
  48  */
  49 #ifdef CONFIG_PARAVIRT
  50 #include <asm/paravirt.h>
  51 #else
  52 #ifndef CONFIG_X86_64
  53 #define apic_write native_apic_mem_write
  54 #define apic_write_atomic native_apic_mem_write_atomic
  55 #define apic_read native_apic_mem_read
  56 #endif
  57 #define setup_boot_clock setup_boot_APIC_clock
  58 #define setup_secondary_clock setup_secondary_APIC_clock
  59 #endif
  60
  61 extern int is_vsmp_box(void);
  62
  63 static inline void native_apic_mem_write(u32 reg, u32 v)
  64 {
  65         *((volatile u32 *)(APIC_BASE + reg)) = v;
  66 }
  67
  68 static inline void native_apic_mem_write_atomic(u32 reg, u32 v)
  69 {
  70         (void)xchg((u32 *)(APIC_BASE + reg), v);
  71 }
  72
  73 static inline u32 native_apic_mem_read(u32 reg)
  74 {
  75         return *((volatile u32 *)(APIC_BASE + reg));
  76 }
  77
  78 static inline void native_apic_msr_write(u32 reg, u32 v)
  79 {
  80         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
  81             reg == APIC_LVR)
  82                 return;
  83
  84         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
  85 }
  86
  87 static inline u32 native_apic_msr_read(u32 reg)
  88 {
  89         u32 low, high;
  90
  91         if (reg == APIC_DFR)
  92                 return -1;
  93
  94         rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
  95         return low;
  96 }
  97
  98 #ifdef CONFIG_X86_32
  99 extern void apic_wait_icr_idle(void);
 100 extern u32 safe_apic_wait_icr_idle(void);
 101 extern void apic_icr_write(u32 low, u32 id);
 102 #else
 103
 104 struct apic_ops {
 105         u32 (*read)(u32 reg);
 106         void (*write)(u32 reg, u32 v);
 107         void (*write_atomic)(u32 reg, u32 v);
 108         u64 (*icr_read)(void);
 109         void (*icr_write)(u32 low, u32 high);
 110         void (*wait_icr_idle)(void);
 111         u32 (*safe_wait_icr_idle)(void);
 112 };
 113
 114 extern struct apic_ops *apic_ops;
 115
 116 #define apic_read (apic_ops->read)
 117 #define apic_write (apic_ops->write)
 118 #define apic_write_atomic (apic_ops->write_atomic)
 119 #define apic_icr_read (apic_ops->icr_read)
 120 #define apic_icr_write (apic_ops->icr_write)
 121 #define apic_wait_icr_idle (apic_ops->wait_icr_idle)
 122 #define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
 123 #endif
 124
 125 extern int get_physical_broadcast(void);
 126
 127 #ifdef CONFIG_X86_GOOD_APIC
 128 # define FORCE_READ_AROUND_WRITE 0
 129 # define apic_read_around(x)
 130 # define apic_write_around(x, y) apic_write((x), (y))
 131 #else
 132 # define FORCE_READ_AROUND_WRITE 1
 133 # define apic_read_around(x) apic_read(x)
 134 # define apic_write_around(x, y) apic_write_atomic((x), (y))
 135 #endif
 136
 137 static inline void ack_APIC_irq(void)
 138 {
 139         /*
 140          * ack_APIC_irq() actually gets compiled as a single instruction:
 141          * - a single rmw on Pentium/82489DX
 142          * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
 143          * ... yummie.
 144          */
 145
 146         /* Docs say use 0 for future compatibility */
 147 #ifdef CONFIG_X86_32
 148         apic_write_around(APIC_EOI, 0);
 149 #else
 150         native_apic_mem_write(APIC_EOI, 0);
 151 #endif
 152 }
 153
 154 extern int lapic_get_maxlvt(void);
 155 extern void clear_local_APIC(void);
 156 extern void connect_bsp_APIC(void);
 157 extern void disconnect_bsp_APIC(int virt_wire_setup);
 158 extern void disable_local_APIC(void);
 159 extern void lapic_shutdown(void);
 160 extern int verify_local_APIC(void);
 161 extern void cache_APIC_registers(void);
 162 extern void sync_Arb_IDs(void);
 163 extern void init_bsp_APIC(void);
 164 extern void setup_local_APIC(void);
 165 extern void end_local_APIC_setup(void);
 166 extern void init_apic_mappings(void);
 167 extern void setup_boot_APIC_clock(void);
 168 extern void setup_secondary_APIC_clock(void);
 169 extern int APIC_init_uniprocessor(void);
 170 extern void enable_NMI_through_LVT0(void);
 171
 172 /*
 173  * On 32bit this is mach-xxx local
 174  */
 175 #ifdef CONFIG_X86_64
 176 extern void early_init_lapic_mapping(void);
 177 extern int apic_is_clustered_box(void);
 178 #else
 179 static inline int apic_is_clustered_box(void)
 180 {
 181         return 0;
 182 }
 183 #endif
 184
 185 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 186 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 187
 188
 189 #else /* !CONFIG_X86_LOCAL_APIC */
 190 static inline void lapic_shutdown(void) { }
 191 #define local_apic_timer_c2_ok          1
 192 static inline void init_apic_mappings(void) { }
 193
 194 #endif /* !CONFIG_X86_LOCAL_APIC */
 195
 196 #endif /* __ASM_APIC_H */