include/asm-x86/desc.h

   1 #ifndef _ASM_DESC_H_
   2 #define _ASM_DESC_H_
   3
   4 #ifndef __ASSEMBLY__
   5 #include <asm/desc_defs.h>
   6 #include <asm/ldt.h>
   7 #include <asm/mmu.h>
   8 #include <linux/smp.h>
   9
  10 static inline void fill_ldt(struct desc_struct *desc,
  11                             const struct user_desc *info)
  12 {
  13         desc->limit0 = info->limit & 0x0ffff;
  14         desc->base0 = info->base_addr & 0x0000ffff;
  15
  16         desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
  17         desc->type = (info->read_exec_only ^ 1) << 1;
  18         desc->type |= info->contents << 2;
  19         desc->s = 1;
  20         desc->dpl = 0x3;
  21         desc->p = info->seg_not_present ^ 1;
  22         desc->limit = (info->limit & 0xf0000) >> 16;
  23         desc->avl = info->useable;
  24         desc->d = info->seg_32bit;
  25         desc->g = info->limit_in_pages;
  26         desc->base2 = (info->base_addr & 0xff000000) >> 24;
  27 }
  28
  29 extern struct desc_ptr idt_descr;
  30 extern gate_desc idt_table[];
  31
  32 struct gdt_page {
  33         struct desc_struct gdt[GDT_ENTRIES];
  34 } __attribute__((aligned(PAGE_SIZE)));
  35 DECLARE_PER_CPU(struct gdt_page, gdt_page);
  36
  37 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
  38 {
  39         return per_cpu(gdt_page, cpu).gdt;
  40 }
  41
  42 #ifdef CONFIG_X86_64
  43
  44 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
  45                              unsigned dpl, unsigned ist, unsigned seg)
  46 {
  47         gate->offset_low = PTR_LOW(func);
  48         gate->segment = __KERNEL_CS;
  49         gate->ist = ist;
  50         gate->p = 1;
  51         gate->dpl = dpl;
  52         gate->zero0 = 0;
  53         gate->zero1 = 0;
  54         gate->type = type;
  55         gate->offset_middle = PTR_MIDDLE(func);
  56         gate->offset_high = PTR_HIGH(func);
  57 }
  58
  59 #else
  60 static inline void pack_gate(gate_desc *gate, unsigned char type,
  61                              unsigned long base, unsigned dpl, unsigned flags,
  62                              unsigned short seg)
  63 {
  64         gate->a = (seg << 16) | (base & 0xffff);
  65         gate->b = (base & 0xffff0000) |
  66                   (((0x80 | type | (dpl << 5)) & 0xff) << 8);
  67 }
  68
  69 #endif
  70
  71 static inline int desc_empty(const void *ptr)
  72 {
  73         const u32 *desc = ptr;
  74         return !(desc[0] | desc[1]);
  75 }
  76
  77 #ifdef CONFIG_PARAVIRT
  78 #include <asm/paravirt.h>
  79 #else
  80 #define load_TR_desc() native_load_tr_desc()
  81 #define load_gdt(dtr) native_load_gdt(dtr)
  82 #define load_idt(dtr) native_load_idt(dtr)
  83 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
  84 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
  85
  86 #define store_gdt(dtr) native_store_gdt(dtr)
  87 #define store_idt(dtr) native_store_idt(dtr)
  88 #define store_tr(tr) (tr = native_store_tr())
  89 #define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
  90
  91 #define load_TLS(t, cpu) native_load_tls(t, cpu)
  92 #define set_ldt native_set_ldt
  93
  94 #define write_ldt_entry(dt, entry, desc)        \
  95         native_write_ldt_entry(dt, entry, desc)
  96 #define write_gdt_entry(dt, entry, desc, type)          \
  97         native_write_gdt_entry(dt, entry, desc, type)
  98 #define write_idt_entry(dt, entry, g)           \
  99         native_write_idt_entry(dt, entry, g)
 100
 101 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
 102 {
 103 }
 104
 105 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
 106 {
 107 }
 108 #endif  /* CONFIG_PARAVIRT */
 109
 110 static inline void native_write_idt_entry(gate_desc *idt, int entry,
 111                                           const gate_desc *gate)
 112 {
 113         memcpy(&idt[entry], gate, sizeof(*gate));
 114 }
 115
 116 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
 117                                           const void *desc)
 118 {
 119         memcpy(&ldt[entry], desc, 8);
 120 }
 121
 122 static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
 123                                           const void *desc, int type)
 124 {
 125         unsigned int size;
 126         switch (type) {
 127         case DESC_TSS:
 128                 size = sizeof(tss_desc);
 129                 break;
 130         case DESC_LDT:
 131                 size = sizeof(ldt_desc);
 132                 break;
 133         default:
 134                 size = sizeof(struct desc_struct);
 135                 break;
 136         }
 137         memcpy(&gdt[entry], desc, size);
 138 }
 139
 140 static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
 141                                    unsigned long limit, unsigned char type,
 142                                    unsigned char flags)
 143 {
 144         desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
 145         desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
 146                 (limit & 0x000f0000) | ((type & 0xff) << 8) |
 147                 ((flags & 0xf) << 20);
 148         desc->p = 1;
 149 }
 150
 151
 152 static inline void set_tssldt_descriptor(void *d, unsigned long addr,
 153                                          unsigned type, unsigned size)
 154 {
 155 #ifdef CONFIG_X86_64
 156         struct ldttss_desc64 *desc = d;
 157         memset(desc, 0, sizeof(*desc));
 158         desc->limit0 = size & 0xFFFF;
 159         desc->base0 = PTR_LOW(addr);
 160         desc->base1 = PTR_MIDDLE(addr) & 0xFF;
 161         desc->type = type;
 162         desc->p = 1;
 163         desc->limit1 = (size >> 16) & 0xF;
 164         desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
 165         desc->base3 = PTR_HIGH(addr);
 166 #else
 167         pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
 168 #endif
 169 }
 170
 171 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
 172 {
 173         struct desc_struct *d = get_cpu_gdt_table(cpu);
 174         tss_desc tss;
 175
 176         /*
 177          * sizeof(unsigned long) coming from an extra "long" at the end
 178          * of the iobitmap. See tss_struct definition in processor.h
 179          *
 180          * -1? seg base+limit should be pointing to the address of the
 181          * last valid byte
 182          */
 183         set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
 184                               IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
 185                               sizeof(unsigned long) - 1);
 186         write_gdt_entry(d, entry, &tss, DESC_TSS);
 187 }
 188
 189 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
 190
 191 static inline void native_set_ldt(const void *addr, unsigned int entries)
 192 {
 193         if (likely(entries == 0))
 194                 asm volatile("lldt %w0"::"q" (0));
 195         else {
 196                 unsigned cpu = smp_processor_id();
 197                 ldt_desc ldt;
 198
 199                 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
 200                                       entries * LDT_ENTRY_SIZE - 1);
 201                 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
 202                                 &ldt, DESC_LDT);
 203                 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
 204         }
 205 }
 206
 207 static inline void native_load_tr_desc(void)
 208 {
 209         asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
 210 }
 211
 212 static inline void native_load_gdt(const struct desc_ptr *dtr)
 213 {
 214         asm volatile("lgdt %0"::"m" (*dtr));
 215 }
 216
 217 static inline void native_load_idt(const struct desc_ptr *dtr)
 218 {
 219         asm volatile("lidt %0"::"m" (*dtr));
 220 }
 221
 222 static inline void native_store_gdt(struct desc_ptr *dtr)
 223 {
 224         asm volatile("sgdt %0":"=m" (*dtr));
 225 }
 226
 227 static inline void native_store_idt(struct desc_ptr *dtr)
 228 {
 229         asm volatile("sidt %0":"=m" (*dtr));
 230 }
 231
 232 static inline unsigned long native_store_tr(void)
 233 {
 234         unsigned long tr;
 235         asm volatile("str %0":"=r" (tr));
 236         return tr;
 237 }
 238
 239 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
 240 {
 241         unsigned int i;
 242         struct desc_struct *gdt = get_cpu_gdt_table(cpu);
 243
 244         for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
 245                 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
 246 }
 247
 248 #define _LDT_empty(info)                                \
 249         ((info)->base_addr              == 0    &&      \
 250          (info)->limit                  == 0    &&      \
 251          (info)->contents               == 0    &&      \
 252          (info)->read_exec_only         == 1    &&      \
 253          (info)->seg_32bit              == 0    &&      \
 254          (info)->limit_in_pages         == 0    &&      \
 255          (info)->seg_not_present        == 1    &&      \
 256          (info)->useable                == 0)
 257
 258 #ifdef CONFIG_X86_64
 259 #define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
 260 #else
 261 #define LDT_empty(info) (_LDT_empty(info))
 262 #endif
 263
 264 static inline void clear_LDT(void)
 265 {
 266         set_ldt(NULL, 0);
 267 }
 268
 269 /*
 270  * load one particular LDT into the current CPU
 271  */
 272 static inline void load_LDT_nolock(mm_context_t *pc)
 273 {
 274         set_ldt(pc->ldt, pc->size);
 275 }
 276
 277 static inline void load_LDT(mm_context_t *pc)
 278 {
 279         preempt_disable();
 280         load_LDT_nolock(pc);
 281         preempt_enable();
 282 }
 283
 284 static inline unsigned long get_desc_base(const struct desc_struct *desc)
 285 {
 286         return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
 287 }
 288
 289 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
 290 {
 291         return desc->limit0 | (desc->limit << 16);
 292 }
 293
 294 static inline void _set_gate(int gate, unsigned type, void *addr,
 295                              unsigned dpl, unsigned ist, unsigned seg)
 296 {
 297         gate_desc s;
 298         pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
 299         /*
 300          * does not need to be atomic because it is only done once at
 301          * setup time
 302          */
 303         write_idt_entry(idt_table, gate, &s);
 304 }
 305
 306 /*
 307  * This needs to use 'idt_table' rather than 'idt', and
 308  * thus use the _nonmapped_ version of the IDT, as the
 309  * Pentium F0 0F bugfix can have resulted in the mapped
 310  * IDT being write-protected.
 311  */
 312 static inline void set_intr_gate(unsigned int n, void *addr)
 313 {
 314         BUG_ON((unsigned)n > 0xFF);
 315         _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
 316 }
 317
 318 #define SYS_VECTOR_FREE         0
 319 #define SYS_VECTOR_ALLOCED      1
 320
 321 extern int first_system_vector;
 322 extern char system_vectors[];
 323
 324 static inline void alloc_system_vector(int vector)
 325 {
 326         if (system_vectors[vector] == SYS_VECTOR_FREE) {
 327                 system_vectors[vector] = SYS_VECTOR_ALLOCED;
 328                 if (first_system_vector > vector)
 329                         first_system_vector = vector;
 330         } else
 331                 BUG();
 332 }
 333
 334 static inline void alloc_intr_gate(unsigned int n, void *addr)
 335 {
 336         alloc_system_vector(n);
 337         set_intr_gate(n, addr);
 338 }
 339
 340 /*
 341  * This routine sets up an interrupt gate at directory privilege level 3.
 342  */
 343 static inline void set_system_intr_gate(unsigned int n, void *addr)
 344 {
 345         BUG_ON((unsigned)n > 0xFF);
 346         _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
 347 }
 348
 349 static inline void set_trap_gate(unsigned int n, void *addr)
 350 {
 351         BUG_ON((unsigned)n > 0xFF);
 352         _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
 353 }
 354
 355 static inline void set_system_gate(unsigned int n, void *addr)
 356 {
 357         BUG_ON((unsigned)n > 0xFF);
 358 #ifdef CONFIG_X86_32
 359         _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
 360 #else
 361         _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
 362 #endif
 363 }
 364
 365 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
 366 {
 367         BUG_ON((unsigned)n > 0xFF);
 368         _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
 369 }
 370
 371 static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
 372 {
 373         BUG_ON((unsigned)n > 0xFF);
 374         _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
 375 }
 376
 377 static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
 378 {
 379         BUG_ON((unsigned)n > 0xFF);
 380         _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
 381 }
 382
 383 #else
 384 /*
 385  * GET_DESC_BASE reads the descriptor base of the specified segment.
 386  *
 387  * Args:
 388  *    idx - descriptor index
 389  *    gdt - GDT pointer
 390  *    base - 32bit register to which the base will be written
 391  *    lo_w - lo word of the "base" register
 392  *    lo_b - lo byte of the "base" register
 393  *    hi_b - hi byte of the low word of the "base" register
 394  *
 395  * Example:
 396  *    GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
 397  *    Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
 398  */
 399 #define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
 400         movb idx * 8 + 4(gdt), lo_b;                    \
 401         movb idx * 8 + 7(gdt), hi_b;                    \
 402         shll $16, base;                                 \
 403         movw idx * 8 + 2(gdt), lo_w;
 404
 405
 406 #endif /* __ASSEMBLY__ */
 407
 408 #endif