1 #ifndef ASM_X86__MPSPEC_H
2 #define ASM_X86__MPSPEC_H
4 #include <linux/init.h>
6 #include <asm/mpspec_def.h>
8 extern int apic_version
[MAX_APICS
];
11 #include <mach_mpspec.h>
13 extern unsigned int def_to_bigsmp
;
14 extern u8 apicid_2_node
[];
17 #ifdef CONFIG_X86_NUMAQ
18 extern int mp_bus_id_to_node
[MAX_MP_BUSSES
];
19 extern int mp_bus_id_to_local
[MAX_MP_BUSSES
];
20 extern int quad_local_to_mp_bus_id
[NR_CPUS
/4][4];
23 #define MAX_APICID 256
27 #define MAX_MP_BUSSES 256
28 /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
29 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
33 extern void early_find_smp_config(void);
34 extern void early_get_smp_config(void);
36 #if defined(CONFIG_MCA) || defined(CONFIG_EISA)
37 extern int mp_bus_id_to_type
[MAX_MP_BUSSES
];
40 extern DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
42 extern unsigned int boot_cpu_physical_apicid
;
43 extern unsigned int max_physical_apicid
;
44 extern int smp_found_config
;
45 extern int mpc_default_type
;
46 extern unsigned long mp_lapic_addr
;
48 extern void find_smp_config(void);
49 extern void get_smp_config(void);
50 #ifdef CONFIG_X86_MPPARSE
51 extern void early_reserve_e820_mpc_new(void);
53 static inline void early_reserve_e820_mpc_new(void) { }
56 void __cpuinit
generic_processor_info(int apicid
, int version
);
58 extern void mp_register_ioapic(int id
, u32 address
, u32 gsi_base
);
59 extern void mp_override_legacy_irq(u8 bus_irq
, u8 polarity
, u8 trigger
,
61 extern void mp_config_acpi_legacy_irqs(void);
62 extern int mp_register_gsi(u32 gsi
, int edge_level
, int active_high_low
);
63 extern int get_nr_irqs_via_madt(void);
64 #ifdef CONFIG_X86_IO_APIC
65 extern int mp_config_acpi_gsi(unsigned char number
, unsigned int devfn
, u8 pin
,
66 u32 gsi
, int triggering
, int polarity
);
69 mp_config_acpi_gsi(unsigned char number
, unsigned int devfn
, u8 pin
,
70 u32 gsi
, int triggering
, int polarity
)
75 #endif /* CONFIG_ACPI */
77 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
80 unsigned long mask
[PHYSID_ARRAY_SIZE
];
83 typedef struct physid_mask physid_mask_t
;
85 #define physid_set(physid, map) set_bit(physid, (map).mask)
86 #define physid_clear(physid, map) clear_bit(physid, (map).mask)
87 #define physid_isset(physid, map) test_bit(physid, (map).mask)
88 #define physid_test_and_set(physid, map) \
89 test_and_set_bit(physid, (map).mask)
91 #define physids_and(dst, src1, src2) \
92 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
94 #define physids_or(dst, src1, src2) \
95 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
97 #define physids_clear(map) \
98 bitmap_zero((map).mask, MAX_APICS)
100 #define physids_complement(dst, src) \
101 bitmap_complement((dst).mask, (src).mask, MAX_APICS)
103 #define physids_empty(map) \
104 bitmap_empty((map).mask, MAX_APICS)
106 #define physids_equal(map1, map2) \
107 bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
109 #define physids_weight(map) \
110 bitmap_weight((map).mask, MAX_APICS)
112 #define physids_shift_right(d, s, n) \
113 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
115 #define physids_shift_left(d, s, n) \
116 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
118 #define physids_coerce(map) ((map).mask[0])
120 #define physids_promote(physids) \
122 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
123 __physid_mask.mask[0] = physids; \
127 /* Note: will create very large stack frames if physid_mask_t is big */
128 #define physid_mask_of_physid(physid) \
130 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
131 physid_set(physid, __physid_mask); \
135 static inline void physid_set_mask_of_physid(int physid
, physid_mask_t
*map
)
138 physid_set(physid
, *map
);
141 #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
142 #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
144 extern physid_mask_t phys_cpu_present_map
;
146 #endif /* ASM_X86__MPSPEC_H */