1 #ifndef __ASM_PARAVIRT_H
2 #define __ASM_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
10 /* Bitmask of what can be clobbered: usually at least eax. */
12 #define CLBR_EAX (1 << 0)
13 #define CLBR_ECX (1 << 1)
14 #define CLBR_EDX (1 << 2)
17 #define CLBR_RSI (1 << 3)
18 #define CLBR_RDI (1 << 4)
19 #define CLBR_R8 (1 << 5)
20 #define CLBR_R9 (1 << 6)
21 #define CLBR_R10 (1 << 7)
22 #define CLBR_R11 (1 << 8)
23 #define CLBR_ANY ((1 << 9) - 1)
24 #include <asm/desc_defs.h>
26 /* CLBR_ANY should match all regs platform has. For i386, that's just it */
27 #define CLBR_ANY ((1 << 3) - 1)
31 #include <linux/types.h>
32 #include <linux/cpumask.h>
33 #include <asm/kmap_types.h>
34 #include <asm/desc_defs.h>
45 unsigned int kernel_rpl
;
46 int shared_kernel_pmd
;
53 * Patch may replace one of the defined code sequences with
54 * arbitrary code, subject to the same register constraints.
55 * This generally means the code is not free to clobber any
56 * registers other than EAX. The patch function should return
57 * the number of bytes of code generated, as we nop pad the
58 * rest in generic code.
60 unsigned (*patch
)(u8 type
, u16 clobber
, void *insnbuf
,
61 unsigned long addr
, unsigned len
);
63 /* Basic arch-specific setup */
64 void (*arch_setup
)(void);
65 char *(*memory_setup
)(void);
66 void (*post_allocator_init
)(void);
68 /* Print a banner to identify the environment */
74 /* Set deferred update mode, used for batching operations. */
80 void (*time_init
)(void);
82 /* Set and set time of day */
83 unsigned long (*get_wallclock
)(void);
84 int (*set_wallclock
)(unsigned long);
86 unsigned long long (*sched_clock
)(void);
87 unsigned long (*get_cpu_khz
)(void);
91 /* hooks for various privileged instructions */
92 unsigned long (*get_debugreg
)(int regno
);
93 void (*set_debugreg
)(int regno
, unsigned long value
);
97 unsigned long (*read_cr0
)(void);
98 void (*write_cr0
)(unsigned long);
100 unsigned long (*read_cr4_safe
)(void);
101 unsigned long (*read_cr4
)(void);
102 void (*write_cr4
)(unsigned long);
105 unsigned long (*read_cr8
)(void);
106 void (*write_cr8
)(unsigned long);
109 /* Segment descriptor handling */
110 void (*load_tr_desc
)(void);
111 void (*load_gdt
)(const struct desc_ptr
*);
112 void (*load_idt
)(const struct desc_ptr
*);
113 void (*store_gdt
)(struct desc_ptr
*);
114 void (*store_idt
)(struct desc_ptr
*);
115 void (*set_ldt
)(const void *desc
, unsigned entries
);
116 unsigned long (*store_tr
)(void);
117 void (*load_tls
)(struct thread_struct
*t
, unsigned int cpu
);
118 void (*write_ldt_entry
)(struct desc_struct
*ldt
, int entrynum
,
120 void (*write_gdt_entry
)(struct desc_struct
*,
121 int entrynum
, const void *desc
, int size
);
122 void (*write_idt_entry
)(gate_desc
*,
123 int entrynum
, const gate_desc
*gate
);
124 void (*load_sp0
)(struct tss_struct
*tss
, struct thread_struct
*t
);
126 void (*set_iopl_mask
)(unsigned mask
);
128 void (*wbinvd
)(void);
129 void (*io_delay
)(void);
131 /* cpuid emulation, mostly so that caps bits can be disabled */
132 void (*cpuid
)(unsigned int *eax
, unsigned int *ebx
,
133 unsigned int *ecx
, unsigned int *edx
);
135 /* MSR, PMC and TSR operations.
136 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
137 u64 (*read_msr
)(unsigned int msr
, int *err
);
138 int (*write_msr
)(unsigned int msr
, unsigned low
, unsigned high
);
140 u64 (*read_tsc
)(void);
141 u64 (*read_pmc
)(int counter
);
142 unsigned long long (*read_tscp
)(unsigned int *aux
);
144 /* These two are jmp to, not actually called. */
145 void (*irq_enable_syscall_ret
)(void);
148 void (*swapgs
)(void);
150 struct pv_lazy_ops lazy_mode
;
154 void (*init_IRQ
)(void);
157 * Get/set interrupt state. save_fl and restore_fl are only
158 * expected to use X86_EFLAGS_IF; all other bits
159 * returned from save_fl are undefined, and may be ignored by
162 unsigned long (*save_fl
)(void);
163 void (*restore_fl
)(unsigned long);
164 void (*irq_disable
)(void);
165 void (*irq_enable
)(void);
166 void (*safe_halt
)(void);
171 #ifdef CONFIG_X86_LOCAL_APIC
173 * Direct APIC operations, principally for VMI. Ideally
174 * these shouldn't be in this interface.
176 void (*apic_write
)(unsigned long reg
, u32 v
);
177 void (*apic_write_atomic
)(unsigned long reg
, u32 v
);
178 u32 (*apic_read
)(unsigned long reg
);
179 void (*setup_boot_clock
)(void);
180 void (*setup_secondary_clock
)(void);
182 void (*startup_ipi_hook
)(int phys_apicid
,
183 unsigned long start_eip
,
184 unsigned long start_esp
);
190 * Called before/after init_mm pagetable setup. setup_start
191 * may reset %cr3, and may pre-install parts of the pagetable;
192 * pagetable setup is expected to preserve any existing
195 void (*pagetable_setup_start
)(pgd_t
*pgd_base
);
196 void (*pagetable_setup_done
)(pgd_t
*pgd_base
);
198 unsigned long (*read_cr2
)(void);
199 void (*write_cr2
)(unsigned long);
201 unsigned long (*read_cr3
)(void);
202 void (*write_cr3
)(unsigned long);
205 * Hooks for intercepting the creation/use/destruction of an
208 void (*activate_mm
)(struct mm_struct
*prev
,
209 struct mm_struct
*next
);
210 void (*dup_mmap
)(struct mm_struct
*oldmm
,
211 struct mm_struct
*mm
);
212 void (*exit_mmap
)(struct mm_struct
*mm
);
216 void (*flush_tlb_user
)(void);
217 void (*flush_tlb_kernel
)(void);
218 void (*flush_tlb_single
)(unsigned long addr
);
219 void (*flush_tlb_others
)(const cpumask_t
*cpus
, struct mm_struct
*mm
,
222 /* Hooks for allocating/releasing pagetable pages */
223 void (*alloc_pte
)(struct mm_struct
*mm
, u32 pfn
);
224 void (*alloc_pmd
)(struct mm_struct
*mm
, u32 pfn
);
225 void (*alloc_pmd_clone
)(u32 pfn
, u32 clonepfn
, u32 start
, u32 count
);
226 void (*alloc_pud
)(struct mm_struct
*mm
, u32 pfn
);
227 void (*release_pte
)(u32 pfn
);
228 void (*release_pmd
)(u32 pfn
);
229 void (*release_pud
)(u32 pfn
);
231 /* Pagetable manipulation functions */
232 void (*set_pte
)(pte_t
*ptep
, pte_t pteval
);
233 void (*set_pte_at
)(struct mm_struct
*mm
, unsigned long addr
,
234 pte_t
*ptep
, pte_t pteval
);
235 void (*set_pmd
)(pmd_t
*pmdp
, pmd_t pmdval
);
236 void (*pte_update
)(struct mm_struct
*mm
, unsigned long addr
,
238 void (*pte_update_defer
)(struct mm_struct
*mm
,
239 unsigned long addr
, pte_t
*ptep
);
241 pte_t (*ptep_modify_prot_start
)(struct mm_struct
*mm
, unsigned long addr
,
243 void (*ptep_modify_prot_commit
)(struct mm_struct
*mm
, unsigned long addr
,
244 pte_t
*ptep
, pte_t pte
);
246 pteval_t (*pte_val
)(pte_t
);
247 pteval_t (*pte_flags
)(pte_t
);
248 pte_t (*make_pte
)(pteval_t pte
);
250 pgdval_t (*pgd_val
)(pgd_t
);
251 pgd_t (*make_pgd
)(pgdval_t pgd
);
253 #if PAGETABLE_LEVELS >= 3
254 #ifdef CONFIG_X86_PAE
255 void (*set_pte_atomic
)(pte_t
*ptep
, pte_t pteval
);
256 void (*set_pte_present
)(struct mm_struct
*mm
, unsigned long addr
,
257 pte_t
*ptep
, pte_t pte
);
258 void (*pte_clear
)(struct mm_struct
*mm
, unsigned long addr
,
260 void (*pmd_clear
)(pmd_t
*pmdp
);
262 #endif /* CONFIG_X86_PAE */
264 void (*set_pud
)(pud_t
*pudp
, pud_t pudval
);
266 pmdval_t (*pmd_val
)(pmd_t
);
267 pmd_t (*make_pmd
)(pmdval_t pmd
);
269 #if PAGETABLE_LEVELS == 4
270 pudval_t (*pud_val
)(pud_t
);
271 pud_t (*make_pud
)(pudval_t pud
);
273 void (*set_pgd
)(pgd_t
*pudp
, pgd_t pgdval
);
274 #endif /* PAGETABLE_LEVELS == 4 */
275 #endif /* PAGETABLE_LEVELS >= 3 */
277 #ifdef CONFIG_HIGHPTE
278 void *(*kmap_atomic_pte
)(struct page
*page
, enum km_type type
);
281 struct pv_lazy_ops lazy_mode
;
285 /* Sometimes the physical address is a pfn, and sometimes its
286 an mfn. We can tell which is which from the index. */
287 void (*set_fixmap
)(unsigned /* enum fixed_addresses */ idx
,
288 unsigned long phys
, pgprot_t flags
);
291 /* This contains all the paravirt structures: we get a convenient
292 * number for each function using the offset which we use to indicate
294 struct paravirt_patch_template
{
295 struct pv_init_ops pv_init_ops
;
296 struct pv_time_ops pv_time_ops
;
297 struct pv_cpu_ops pv_cpu_ops
;
298 struct pv_irq_ops pv_irq_ops
;
299 struct pv_apic_ops pv_apic_ops
;
300 struct pv_mmu_ops pv_mmu_ops
;
303 extern struct pv_info pv_info
;
304 extern struct pv_init_ops pv_init_ops
;
305 extern struct pv_time_ops pv_time_ops
;
306 extern struct pv_cpu_ops pv_cpu_ops
;
307 extern struct pv_irq_ops pv_irq_ops
;
308 extern struct pv_apic_ops pv_apic_ops
;
309 extern struct pv_mmu_ops pv_mmu_ops
;
311 #define PARAVIRT_PATCH(x) \
312 (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
314 #define paravirt_type(op) \
315 [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \
316 [paravirt_opptr] "m" (op)
317 #define paravirt_clobber(clobber) \
318 [paravirt_clobber] "i" (clobber)
321 * Generate some code, and mark it as patchable by the
322 * apply_paravirt() alternate instruction patcher.
324 #define _paravirt_alt(insn_string, type, clobber) \
325 "771:\n\t" insn_string "\n" "772:\n" \
326 ".pushsection .parainstructions,\"a\"\n" \
329 " .byte " type "\n" \
330 " .byte 772b-771b\n" \
331 " .short " clobber "\n" \
334 /* Generate patchable code, with the default asm parameters. */
335 #define paravirt_alt(insn_string) \
336 _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
338 /* Simple instruction patching code. */
339 #define DEF_NATIVE(ops, name, code) \
340 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
341 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
343 unsigned paravirt_patch_nop(void);
344 unsigned paravirt_patch_ignore(unsigned len
);
345 unsigned paravirt_patch_call(void *insnbuf
,
346 const void *target
, u16 tgt_clobbers
,
347 unsigned long addr
, u16 site_clobbers
,
349 unsigned paravirt_patch_jmp(void *insnbuf
, const void *target
,
350 unsigned long addr
, unsigned len
);
351 unsigned paravirt_patch_default(u8 type
, u16 clobbers
, void *insnbuf
,
352 unsigned long addr
, unsigned len
);
354 unsigned paravirt_patch_insns(void *insnbuf
, unsigned len
,
355 const char *start
, const char *end
);
357 unsigned native_patch(u8 type
, u16 clobbers
, void *ibuf
,
358 unsigned long addr
, unsigned len
);
360 int paravirt_disable_iospace(void);
363 * This generates an indirect call based on the operation type number.
364 * The type number, computed in PARAVIRT_PATCH, is derived from the
365 * offset into the paravirt_patch_template structure, and can therefore be
366 * freely converted back into a structure offset.
368 #define PARAVIRT_CALL "call *%[paravirt_opptr];"
371 * These macros are intended to wrap calls through one of the paravirt
372 * ops structs, so that they can be later identified and patched at
375 * Normally, a call to a pv_op function is a simple indirect call:
376 * (pv_op_struct.operations)(args...).
378 * Unfortunately, this is a relatively slow operation for modern CPUs,
379 * because it cannot necessarily determine what the destination
380 * address is. In this case, the address is a runtime constant, so at
381 * the very least we can patch the call to e a simple direct call, or
382 * ideally, patch an inline implementation into the callsite. (Direct
383 * calls are essentially free, because the call and return addresses
384 * are completely predictable.)
386 * For i386, these macros rely on the standard gcc "regparm(3)" calling
387 * convention, in which the first three arguments are placed in %eax,
388 * %edx, %ecx (in that order), and the remaining arguments are placed
389 * on the stack. All caller-save registers (eax,edx,ecx) are expected
390 * to be modified (either clobbered or used for return values).
391 * X86_64, on the other hand, already specifies a register-based calling
392 * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
393 * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
394 * special handling for dealing with 4 arguments, unlike i386.
395 * However, x86_64 also have to clobber all caller saved registers, which
396 * unfortunately, are quite a bit (r8 - r11)
398 * The call instruction itself is marked by placing its start address
399 * and size into the .parainstructions section, so that
400 * apply_paravirt() in arch/i386/kernel/alternative.c can do the
401 * appropriate patching under the control of the backend pv_init_ops
404 * Unfortunately there's no way to get gcc to generate the args setup
405 * for the call, and then allow the call itself to be generated by an
406 * inline asm. Because of this, we must do the complete arg setup and
407 * return value handling from within these macros. This is fairly
410 * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
411 * It could be extended to more arguments, but there would be little
412 * to be gained from that. For each number of arguments, there are
413 * the two VCALL and CALL variants for void and non-void functions.
415 * When there is a return value, the invoker of the macro must specify
416 * the return type. The macro then uses sizeof() on that type to
417 * determine whether its a 32 or 64 bit value, and places the return
418 * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
419 * 64-bit). For x86_64 machines, it just returns at %rax regardless of
420 * the return value size.
422 * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
423 * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
426 * Small structures are passed and returned in registers. The macro
427 * calling convention can't directly deal with this, so the wrapper
428 * functions must do this.
430 * These PVOP_* macros are only defined within this header. This
431 * means that all uses must be wrapped in inline functions. This also
432 * makes sure the incoming and outgoing types are always correct.
435 #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx
436 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS
437 #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \
439 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS
440 #define EXTRA_CLOBBERS
441 #define VEXTRA_CLOBBERS
443 #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx
444 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax
445 #define PVOP_VCALL_CLOBBERS "=D" (__edi), \
446 "=S" (__esi), "=d" (__edx), \
449 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
451 #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11"
452 #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11"
455 #define __PVOP_CALL(rettype, op, pre, post, ...) \
459 /* This is 32-bit specific, but is okay in 64-bit */ \
460 /* since this condition will never hold */ \
461 if (sizeof(rettype) > sizeof(unsigned long)) { \
463 paravirt_alt(PARAVIRT_CALL) \
465 : PVOP_CALL_CLOBBERS \
466 : paravirt_type(op), \
467 paravirt_clobber(CLBR_ANY), \
469 : "memory", "cc" EXTRA_CLOBBERS); \
470 __ret = (rettype)((((u64)__edx) << 32) | __eax); \
473 paravirt_alt(PARAVIRT_CALL) \
475 : PVOP_CALL_CLOBBERS \
476 : paravirt_type(op), \
477 paravirt_clobber(CLBR_ANY), \
479 : "memory", "cc" EXTRA_CLOBBERS); \
480 __ret = (rettype)__eax; \
484 #define __PVOP_VCALL(op, pre, post, ...) \
488 paravirt_alt(PARAVIRT_CALL) \
490 : PVOP_VCALL_CLOBBERS \
491 : paravirt_type(op), \
492 paravirt_clobber(CLBR_ANY), \
494 : "memory", "cc" VEXTRA_CLOBBERS); \
497 #define PVOP_CALL0(rettype, op) \
498 __PVOP_CALL(rettype, op, "", "")
499 #define PVOP_VCALL0(op) \
500 __PVOP_VCALL(op, "", "")
502 #define PVOP_CALL1(rettype, op, arg1) \
503 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)))
504 #define PVOP_VCALL1(op, arg1) \
505 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)))
507 #define PVOP_CALL2(rettype, op, arg1, arg2) \
508 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
509 "1" ((unsigned long)(arg2)))
510 #define PVOP_VCALL2(op, arg1, arg2) \
511 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
512 "1" ((unsigned long)(arg2)))
514 #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \
515 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
516 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
517 #define PVOP_VCALL3(op, arg1, arg2, arg3) \
518 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
519 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
521 /* This is the only difference in x86_64. We can make it much simpler */
523 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
524 __PVOP_CALL(rettype, op, \
525 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
526 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
527 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
528 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
530 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
531 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
532 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
534 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
535 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
536 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
537 "3"((unsigned long)(arg4)))
538 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
539 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
540 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
541 "3"((unsigned long)(arg4)))
544 static inline int paravirt_enabled(void)
546 return pv_info
.paravirt_enabled
;
549 static inline void load_sp0(struct tss_struct
*tss
,
550 struct thread_struct
*thread
)
552 PVOP_VCALL2(pv_cpu_ops
.load_sp0
, tss
, thread
);
555 #define ARCH_SETUP pv_init_ops.arch_setup();
556 static inline unsigned long get_wallclock(void)
558 return PVOP_CALL0(unsigned long, pv_time_ops
.get_wallclock
);
561 static inline int set_wallclock(unsigned long nowtime
)
563 return PVOP_CALL1(int, pv_time_ops
.set_wallclock
, nowtime
);
566 static inline void (*choose_time_init(void))(void)
568 return pv_time_ops
.time_init
;
571 /* The paravirtualized CPUID instruction. */
572 static inline void __cpuid(unsigned int *eax
, unsigned int *ebx
,
573 unsigned int *ecx
, unsigned int *edx
)
575 PVOP_VCALL4(pv_cpu_ops
.cpuid
, eax
, ebx
, ecx
, edx
);
579 * These special macros can be used to get or set a debugging register
581 static inline unsigned long paravirt_get_debugreg(int reg
)
583 return PVOP_CALL1(unsigned long, pv_cpu_ops
.get_debugreg
, reg
);
585 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
586 static inline void set_debugreg(unsigned long val
, int reg
)
588 PVOP_VCALL2(pv_cpu_ops
.set_debugreg
, reg
, val
);
591 static inline void clts(void)
593 PVOP_VCALL0(pv_cpu_ops
.clts
);
596 static inline unsigned long read_cr0(void)
598 return PVOP_CALL0(unsigned long, pv_cpu_ops
.read_cr0
);
601 static inline void write_cr0(unsigned long x
)
603 PVOP_VCALL1(pv_cpu_ops
.write_cr0
, x
);
606 static inline unsigned long read_cr2(void)
608 return PVOP_CALL0(unsigned long, pv_mmu_ops
.read_cr2
);
611 static inline void write_cr2(unsigned long x
)
613 PVOP_VCALL1(pv_mmu_ops
.write_cr2
, x
);
616 static inline unsigned long read_cr3(void)
618 return PVOP_CALL0(unsigned long, pv_mmu_ops
.read_cr3
);
621 static inline void write_cr3(unsigned long x
)
623 PVOP_VCALL1(pv_mmu_ops
.write_cr3
, x
);
626 static inline unsigned long read_cr4(void)
628 return PVOP_CALL0(unsigned long, pv_cpu_ops
.read_cr4
);
630 static inline unsigned long read_cr4_safe(void)
632 return PVOP_CALL0(unsigned long, pv_cpu_ops
.read_cr4_safe
);
635 static inline void write_cr4(unsigned long x
)
637 PVOP_VCALL1(pv_cpu_ops
.write_cr4
, x
);
641 static inline unsigned long read_cr8(void)
643 return PVOP_CALL0(unsigned long, pv_cpu_ops
.read_cr8
);
646 static inline void write_cr8(unsigned long x
)
648 PVOP_VCALL1(pv_cpu_ops
.write_cr8
, x
);
652 static inline void raw_safe_halt(void)
654 PVOP_VCALL0(pv_irq_ops
.safe_halt
);
657 static inline void halt(void)
659 PVOP_VCALL0(pv_irq_ops
.safe_halt
);
662 static inline void wbinvd(void)
664 PVOP_VCALL0(pv_cpu_ops
.wbinvd
);
667 #define get_kernel_rpl() (pv_info.kernel_rpl)
669 static inline u64
paravirt_read_msr(unsigned msr
, int *err
)
671 return PVOP_CALL2(u64
, pv_cpu_ops
.read_msr
, msr
, err
);
673 static inline int paravirt_write_msr(unsigned msr
, unsigned low
, unsigned high
)
675 return PVOP_CALL3(int, pv_cpu_ops
.write_msr
, msr
, low
, high
);
678 /* These should all do BUG_ON(_err), but our headers are too tangled. */
679 #define rdmsr(msr, val1, val2) \
682 u64 _l = paravirt_read_msr(msr, &_err); \
687 #define wrmsr(msr, val1, val2) \
689 paravirt_write_msr(msr, val1, val2); \
692 #define rdmsrl(msr, val) \
695 val = paravirt_read_msr(msr, &_err); \
698 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
699 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b)
701 /* rdmsr with exception handling */
702 #define rdmsr_safe(msr, a, b) \
705 u64 _l = paravirt_read_msr(msr, &_err); \
711 static inline int rdmsrl_safe(unsigned msr
, unsigned long long *p
)
715 *p
= paravirt_read_msr(msr
, &err
);
719 static inline u64
paravirt_read_tsc(void)
721 return PVOP_CALL0(u64
, pv_cpu_ops
.read_tsc
);
724 #define rdtscl(low) \
726 u64 _l = paravirt_read_tsc(); \
730 #define rdtscll(val) (val = paravirt_read_tsc())
732 static inline unsigned long long paravirt_sched_clock(void)
734 return PVOP_CALL0(unsigned long long, pv_time_ops
.sched_clock
);
736 #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz())
738 static inline unsigned long long paravirt_read_pmc(int counter
)
740 return PVOP_CALL1(u64
, pv_cpu_ops
.read_pmc
, counter
);
743 #define rdpmc(counter, low, high) \
745 u64 _l = paravirt_read_pmc(counter); \
750 static inline unsigned long long paravirt_rdtscp(unsigned int *aux
)
752 return PVOP_CALL1(u64
, pv_cpu_ops
.read_tscp
, aux
);
755 #define rdtscp(low, high, aux) \
758 unsigned long __val = paravirt_rdtscp(&__aux); \
759 (low) = (u32)__val; \
760 (high) = (u32)(__val >> 32); \
764 #define rdtscpll(val, aux) \
766 unsigned long __aux; \
767 val = paravirt_rdtscp(&__aux); \
771 static inline void load_TR_desc(void)
773 PVOP_VCALL0(pv_cpu_ops
.load_tr_desc
);
775 static inline void load_gdt(const struct desc_ptr
*dtr
)
777 PVOP_VCALL1(pv_cpu_ops
.load_gdt
, dtr
);
779 static inline void load_idt(const struct desc_ptr
*dtr
)
781 PVOP_VCALL1(pv_cpu_ops
.load_idt
, dtr
);
783 static inline void set_ldt(const void *addr
, unsigned entries
)
785 PVOP_VCALL2(pv_cpu_ops
.set_ldt
, addr
, entries
);
787 static inline void store_gdt(struct desc_ptr
*dtr
)
789 PVOP_VCALL1(pv_cpu_ops
.store_gdt
, dtr
);
791 static inline void store_idt(struct desc_ptr
*dtr
)
793 PVOP_VCALL1(pv_cpu_ops
.store_idt
, dtr
);
795 static inline unsigned long paravirt_store_tr(void)
797 return PVOP_CALL0(unsigned long, pv_cpu_ops
.store_tr
);
799 #define store_tr(tr) ((tr) = paravirt_store_tr())
800 static inline void load_TLS(struct thread_struct
*t
, unsigned cpu
)
802 PVOP_VCALL2(pv_cpu_ops
.load_tls
, t
, cpu
);
805 static inline void write_ldt_entry(struct desc_struct
*dt
, int entry
,
808 PVOP_VCALL3(pv_cpu_ops
.write_ldt_entry
, dt
, entry
, desc
);
811 static inline void write_gdt_entry(struct desc_struct
*dt
, int entry
,
812 void *desc
, int type
)
814 PVOP_VCALL4(pv_cpu_ops
.write_gdt_entry
, dt
, entry
, desc
, type
);
817 static inline void write_idt_entry(gate_desc
*dt
, int entry
, const gate_desc
*g
)
819 PVOP_VCALL3(pv_cpu_ops
.write_idt_entry
, dt
, entry
, g
);
821 static inline void set_iopl_mask(unsigned mask
)
823 PVOP_VCALL1(pv_cpu_ops
.set_iopl_mask
, mask
);
826 /* The paravirtualized I/O functions */
827 static inline void slow_down_io(void)
829 pv_cpu_ops
.io_delay();
830 #ifdef REALLY_SLOW_IO
831 pv_cpu_ops
.io_delay();
832 pv_cpu_ops
.io_delay();
833 pv_cpu_ops
.io_delay();
837 #ifdef CONFIG_X86_LOCAL_APIC
839 * Basic functions accessing APICs.
841 static inline void apic_write(unsigned long reg
, u32 v
)
843 PVOP_VCALL2(pv_apic_ops
.apic_write
, reg
, v
);
846 static inline void apic_write_atomic(unsigned long reg
, u32 v
)
848 PVOP_VCALL2(pv_apic_ops
.apic_write_atomic
, reg
, v
);
851 static inline u32
apic_read(unsigned long reg
)
853 return PVOP_CALL1(unsigned long, pv_apic_ops
.apic_read
, reg
);
856 static inline void setup_boot_clock(void)
858 PVOP_VCALL0(pv_apic_ops
.setup_boot_clock
);
861 static inline void setup_secondary_clock(void)
863 PVOP_VCALL0(pv_apic_ops
.setup_secondary_clock
);
867 static inline void paravirt_post_allocator_init(void)
869 if (pv_init_ops
.post_allocator_init
)
870 (*pv_init_ops
.post_allocator_init
)();
873 static inline void paravirt_pagetable_setup_start(pgd_t
*base
)
875 (*pv_mmu_ops
.pagetable_setup_start
)(base
);
878 static inline void paravirt_pagetable_setup_done(pgd_t
*base
)
880 (*pv_mmu_ops
.pagetable_setup_done
)(base
);
884 static inline void startup_ipi_hook(int phys_apicid
, unsigned long start_eip
,
885 unsigned long start_esp
)
887 PVOP_VCALL3(pv_apic_ops
.startup_ipi_hook
,
888 phys_apicid
, start_eip
, start_esp
);
892 static inline void paravirt_activate_mm(struct mm_struct
*prev
,
893 struct mm_struct
*next
)
895 PVOP_VCALL2(pv_mmu_ops
.activate_mm
, prev
, next
);
898 static inline void arch_dup_mmap(struct mm_struct
*oldmm
,
899 struct mm_struct
*mm
)
901 PVOP_VCALL2(pv_mmu_ops
.dup_mmap
, oldmm
, mm
);
904 static inline void arch_exit_mmap(struct mm_struct
*mm
)
906 PVOP_VCALL1(pv_mmu_ops
.exit_mmap
, mm
);
909 static inline void __flush_tlb(void)
911 PVOP_VCALL0(pv_mmu_ops
.flush_tlb_user
);
913 static inline void __flush_tlb_global(void)
915 PVOP_VCALL0(pv_mmu_ops
.flush_tlb_kernel
);
917 static inline void __flush_tlb_single(unsigned long addr
)
919 PVOP_VCALL1(pv_mmu_ops
.flush_tlb_single
, addr
);
922 static inline void flush_tlb_others(cpumask_t cpumask
, struct mm_struct
*mm
,
925 PVOP_VCALL3(pv_mmu_ops
.flush_tlb_others
, &cpumask
, mm
, va
);
928 static inline void paravirt_alloc_pte(struct mm_struct
*mm
, unsigned pfn
)
930 PVOP_VCALL2(pv_mmu_ops
.alloc_pte
, mm
, pfn
);
932 static inline void paravirt_release_pte(unsigned pfn
)
934 PVOP_VCALL1(pv_mmu_ops
.release_pte
, pfn
);
937 static inline void paravirt_alloc_pmd(struct mm_struct
*mm
, unsigned pfn
)
939 PVOP_VCALL2(pv_mmu_ops
.alloc_pmd
, mm
, pfn
);
942 static inline void paravirt_alloc_pmd_clone(unsigned pfn
, unsigned clonepfn
,
943 unsigned start
, unsigned count
)
945 PVOP_VCALL4(pv_mmu_ops
.alloc_pmd_clone
, pfn
, clonepfn
, start
, count
);
947 static inline void paravirt_release_pmd(unsigned pfn
)
949 PVOP_VCALL1(pv_mmu_ops
.release_pmd
, pfn
);
952 static inline void paravirt_alloc_pud(struct mm_struct
*mm
, unsigned pfn
)
954 PVOP_VCALL2(pv_mmu_ops
.alloc_pud
, mm
, pfn
);
956 static inline void paravirt_release_pud(unsigned pfn
)
958 PVOP_VCALL1(pv_mmu_ops
.release_pud
, pfn
);
961 #ifdef CONFIG_HIGHPTE
962 static inline void *kmap_atomic_pte(struct page
*page
, enum km_type type
)
965 ret
= PVOP_CALL2(unsigned long, pv_mmu_ops
.kmap_atomic_pte
, page
, type
);
970 static inline void pte_update(struct mm_struct
*mm
, unsigned long addr
,
973 PVOP_VCALL3(pv_mmu_ops
.pte_update
, mm
, addr
, ptep
);
976 static inline void pte_update_defer(struct mm_struct
*mm
, unsigned long addr
,
979 PVOP_VCALL3(pv_mmu_ops
.pte_update_defer
, mm
, addr
, ptep
);
982 static inline pte_t
__pte(pteval_t val
)
986 if (sizeof(pteval_t
) > sizeof(long))
987 ret
= PVOP_CALL2(pteval_t
,
989 val
, (u64
)val
>> 32);
991 ret
= PVOP_CALL1(pteval_t
,
995 return (pte_t
) { .pte
= ret
};
998 static inline pteval_t
pte_val(pte_t pte
)
1002 if (sizeof(pteval_t
) > sizeof(long))
1003 ret
= PVOP_CALL2(pteval_t
, pv_mmu_ops
.pte_val
,
1004 pte
.pte
, (u64
)pte
.pte
>> 32);
1006 ret
= PVOP_CALL1(pteval_t
, pv_mmu_ops
.pte_val
,
1012 static inline pteval_t
pte_flags(pte_t pte
)
1016 if (sizeof(pteval_t
) > sizeof(long))
1017 ret
= PVOP_CALL2(pteval_t
, pv_mmu_ops
.pte_flags
,
1018 pte
.pte
, (u64
)pte
.pte
>> 32);
1020 ret
= PVOP_CALL1(pteval_t
, pv_mmu_ops
.pte_flags
,
1026 static inline pgd_t
__pgd(pgdval_t val
)
1030 if (sizeof(pgdval_t
) > sizeof(long))
1031 ret
= PVOP_CALL2(pgdval_t
, pv_mmu_ops
.make_pgd
,
1032 val
, (u64
)val
>> 32);
1034 ret
= PVOP_CALL1(pgdval_t
, pv_mmu_ops
.make_pgd
,
1037 return (pgd_t
) { ret
};
1040 static inline pgdval_t
pgd_val(pgd_t pgd
)
1044 if (sizeof(pgdval_t
) > sizeof(long))
1045 ret
= PVOP_CALL2(pgdval_t
, pv_mmu_ops
.pgd_val
,
1046 pgd
.pgd
, (u64
)pgd
.pgd
>> 32);
1048 ret
= PVOP_CALL1(pgdval_t
, pv_mmu_ops
.pgd_val
,
1054 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1055 static inline pte_t
ptep_modify_prot_start(struct mm_struct
*mm
, unsigned long addr
,
1060 ret
= PVOP_CALL3(pteval_t
, pv_mmu_ops
.ptep_modify_prot_start
,
1063 return (pte_t
) { .pte
= ret
};
1066 static inline void ptep_modify_prot_commit(struct mm_struct
*mm
, unsigned long addr
,
1067 pte_t
*ptep
, pte_t pte
)
1069 if (sizeof(pteval_t
) > sizeof(long))
1071 pv_mmu_ops
.ptep_modify_prot_commit(mm
, addr
, ptep
, pte
);
1073 PVOP_VCALL4(pv_mmu_ops
.ptep_modify_prot_commit
,
1074 mm
, addr
, ptep
, pte
.pte
);
1077 static inline void set_pte(pte_t
*ptep
, pte_t pte
)
1079 if (sizeof(pteval_t
) > sizeof(long))
1080 PVOP_VCALL3(pv_mmu_ops
.set_pte
, ptep
,
1081 pte
.pte
, (u64
)pte
.pte
>> 32);
1083 PVOP_VCALL2(pv_mmu_ops
.set_pte
, ptep
,
1087 static inline void set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
1088 pte_t
*ptep
, pte_t pte
)
1090 if (sizeof(pteval_t
) > sizeof(long))
1092 pv_mmu_ops
.set_pte_at(mm
, addr
, ptep
, pte
);
1094 PVOP_VCALL4(pv_mmu_ops
.set_pte_at
, mm
, addr
, ptep
, pte
.pte
);
1097 static inline void set_pmd(pmd_t
*pmdp
, pmd_t pmd
)
1099 pmdval_t val
= native_pmd_val(pmd
);
1101 if (sizeof(pmdval_t
) > sizeof(long))
1102 PVOP_VCALL3(pv_mmu_ops
.set_pmd
, pmdp
, val
, (u64
)val
>> 32);
1104 PVOP_VCALL2(pv_mmu_ops
.set_pmd
, pmdp
, val
);
1107 #if PAGETABLE_LEVELS >= 3
1108 static inline pmd_t
__pmd(pmdval_t val
)
1112 if (sizeof(pmdval_t
) > sizeof(long))
1113 ret
= PVOP_CALL2(pmdval_t
, pv_mmu_ops
.make_pmd
,
1114 val
, (u64
)val
>> 32);
1116 ret
= PVOP_CALL1(pmdval_t
, pv_mmu_ops
.make_pmd
,
1119 return (pmd_t
) { ret
};
1122 static inline pmdval_t
pmd_val(pmd_t pmd
)
1126 if (sizeof(pmdval_t
) > sizeof(long))
1127 ret
= PVOP_CALL2(pmdval_t
, pv_mmu_ops
.pmd_val
,
1128 pmd
.pmd
, (u64
)pmd
.pmd
>> 32);
1130 ret
= PVOP_CALL1(pmdval_t
, pv_mmu_ops
.pmd_val
,
1136 static inline void set_pud(pud_t
*pudp
, pud_t pud
)
1138 pudval_t val
= native_pud_val(pud
);
1140 if (sizeof(pudval_t
) > sizeof(long))
1141 PVOP_VCALL3(pv_mmu_ops
.set_pud
, pudp
,
1142 val
, (u64
)val
>> 32);
1144 PVOP_VCALL2(pv_mmu_ops
.set_pud
, pudp
,
1147 #if PAGETABLE_LEVELS == 4
1148 static inline pud_t
__pud(pudval_t val
)
1152 if (sizeof(pudval_t
) > sizeof(long))
1153 ret
= PVOP_CALL2(pudval_t
, pv_mmu_ops
.make_pud
,
1154 val
, (u64
)val
>> 32);
1156 ret
= PVOP_CALL1(pudval_t
, pv_mmu_ops
.make_pud
,
1159 return (pud_t
) { ret
};
1162 static inline pudval_t
pud_val(pud_t pud
)
1166 if (sizeof(pudval_t
) > sizeof(long))
1167 ret
= PVOP_CALL2(pudval_t
, pv_mmu_ops
.pud_val
,
1168 pud
.pud
, (u64
)pud
.pud
>> 32);
1170 ret
= PVOP_CALL1(pudval_t
, pv_mmu_ops
.pud_val
,
1176 static inline void set_pgd(pgd_t
*pgdp
, pgd_t pgd
)
1178 pgdval_t val
= native_pgd_val(pgd
);
1180 if (sizeof(pgdval_t
) > sizeof(long))
1181 PVOP_VCALL3(pv_mmu_ops
.set_pgd
, pgdp
,
1182 val
, (u64
)val
>> 32);
1184 PVOP_VCALL2(pv_mmu_ops
.set_pgd
, pgdp
,
1188 static inline void pgd_clear(pgd_t
*pgdp
)
1190 set_pgd(pgdp
, __pgd(0));
1193 static inline void pud_clear(pud_t
*pudp
)
1195 set_pud(pudp
, __pud(0));
1198 #endif /* PAGETABLE_LEVELS == 4 */
1200 #endif /* PAGETABLE_LEVELS >= 3 */
1202 #ifdef CONFIG_X86_PAE
1203 /* Special-case pte-setting operations for PAE, which can't update a
1204 64-bit pte atomically */
1205 static inline void set_pte_atomic(pte_t
*ptep
, pte_t pte
)
1207 PVOP_VCALL3(pv_mmu_ops
.set_pte_atomic
, ptep
,
1208 pte
.pte
, pte
.pte
>> 32);
1211 static inline void set_pte_present(struct mm_struct
*mm
, unsigned long addr
,
1212 pte_t
*ptep
, pte_t pte
)
1215 pv_mmu_ops
.set_pte_present(mm
, addr
, ptep
, pte
);
1218 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
1221 PVOP_VCALL3(pv_mmu_ops
.pte_clear
, mm
, addr
, ptep
);
1224 static inline void pmd_clear(pmd_t
*pmdp
)
1226 PVOP_VCALL1(pv_mmu_ops
.pmd_clear
, pmdp
);
1228 #else /* !CONFIG_X86_PAE */
1229 static inline void set_pte_atomic(pte_t
*ptep
, pte_t pte
)
1234 static inline void set_pte_present(struct mm_struct
*mm
, unsigned long addr
,
1235 pte_t
*ptep
, pte_t pte
)
1240 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
,
1243 set_pte_at(mm
, addr
, ptep
, __pte(0));
1246 static inline void pmd_clear(pmd_t
*pmdp
)
1248 set_pmd(pmdp
, __pmd(0));
1250 #endif /* CONFIG_X86_PAE */
1252 /* Lazy mode for batching updates / context switch */
1253 enum paravirt_lazy_mode
{
1259 enum paravirt_lazy_mode
paravirt_get_lazy_mode(void);
1260 void paravirt_enter_lazy_cpu(void);
1261 void paravirt_leave_lazy_cpu(void);
1262 void paravirt_enter_lazy_mmu(void);
1263 void paravirt_leave_lazy_mmu(void);
1264 void paravirt_leave_lazy(enum paravirt_lazy_mode mode
);
1266 #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE
1267 static inline void arch_enter_lazy_cpu_mode(void)
1269 PVOP_VCALL0(pv_cpu_ops
.lazy_mode
.enter
);
1272 static inline void arch_leave_lazy_cpu_mode(void)
1274 PVOP_VCALL0(pv_cpu_ops
.lazy_mode
.leave
);
1277 static inline void arch_flush_lazy_cpu_mode(void)
1279 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU
)) {
1280 arch_leave_lazy_cpu_mode();
1281 arch_enter_lazy_cpu_mode();
1286 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1287 static inline void arch_enter_lazy_mmu_mode(void)
1289 PVOP_VCALL0(pv_mmu_ops
.lazy_mode
.enter
);
1292 static inline void arch_leave_lazy_mmu_mode(void)
1294 PVOP_VCALL0(pv_mmu_ops
.lazy_mode
.leave
);
1297 static inline void arch_flush_lazy_mmu_mode(void)
1299 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU
)) {
1300 arch_leave_lazy_mmu_mode();
1301 arch_enter_lazy_mmu_mode();
1305 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx
,
1306 unsigned long phys
, pgprot_t flags
)
1308 pv_mmu_ops
.set_fixmap(idx
, phys
, flags
);
1311 void _paravirt_nop(void);
1312 #define paravirt_nop ((void *)_paravirt_nop)
1314 /* These all sit in the .parainstructions section to tell us what to patch. */
1315 struct paravirt_patch_site
{
1316 u8
*instr
; /* original instructions */
1317 u8 instrtype
; /* type of this instruction */
1318 u8 len
; /* length of original instruction */
1319 u16 clobbers
; /* what registers you may clobber */
1322 extern struct paravirt_patch_site __parainstructions
[],
1323 __parainstructions_end
[];
1325 #ifdef CONFIG_X86_32
1326 #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;"
1327 #define PV_RESTORE_REGS "popl %%edx; popl %%ecx"
1328 #define PV_FLAGS_ARG "0"
1329 #define PV_EXTRA_CLOBBERS
1330 #define PV_VEXTRA_CLOBBERS
1332 /* We save some registers, but all of them, that's too much. We clobber all
1333 * caller saved registers but the argument parameter */
1334 #define PV_SAVE_REGS "pushq %%rdi;"
1335 #define PV_RESTORE_REGS "popq %%rdi;"
1336 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx"
1337 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx"
1338 #define PV_FLAGS_ARG "D"
1341 static inline unsigned long __raw_local_save_flags(void)
1345 asm volatile(paravirt_alt(PV_SAVE_REGS
1349 : paravirt_type(pv_irq_ops
.save_fl
),
1350 paravirt_clobber(CLBR_EAX
)
1351 : "memory", "cc" PV_VEXTRA_CLOBBERS
);
1355 static inline void raw_local_irq_restore(unsigned long f
)
1357 asm volatile(paravirt_alt(PV_SAVE_REGS
1362 paravirt_type(pv_irq_ops
.restore_fl
),
1363 paravirt_clobber(CLBR_EAX
)
1364 : "memory", "cc" PV_EXTRA_CLOBBERS
);
1367 static inline void raw_local_irq_disable(void)
1369 asm volatile(paravirt_alt(PV_SAVE_REGS
1373 : paravirt_type(pv_irq_ops
.irq_disable
),
1374 paravirt_clobber(CLBR_EAX
)
1375 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS
);
1378 static inline void raw_local_irq_enable(void)
1380 asm volatile(paravirt_alt(PV_SAVE_REGS
1384 : paravirt_type(pv_irq_ops
.irq_enable
),
1385 paravirt_clobber(CLBR_EAX
)
1386 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS
);
1389 static inline unsigned long __raw_local_irq_save(void)
1393 f
= __raw_local_save_flags();
1394 raw_local_irq_disable();
1398 /* Make sure as little as possible of this mess escapes. */
1399 #undef PARAVIRT_CALL
1413 #else /* __ASSEMBLY__ */
1415 #define _PVSITE(ptype, clobbers, ops, word, algn) \
1419 .pushsection .parainstructions,"a"; \
1428 #ifdef CONFIG_X86_64
1429 #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx
1430 #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax
1431 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
1432 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
1434 #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx
1435 #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
1436 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
1437 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
1440 #define INTERRUPT_RETURN \
1441 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
1442 jmp *%cs:pv_cpu_ops+PV_CPU_iret)
1444 #define DISABLE_INTERRUPTS(clobbers) \
1445 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
1447 call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \
1450 #define ENABLE_INTERRUPTS(clobbers) \
1451 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
1453 call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \
1456 #define ENABLE_INTERRUPTS_SYSCALL_RET \
1457 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\
1459 jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret)
1462 #ifdef CONFIG_X86_32
1463 #define GET_CR0_INTO_EAX \
1464 push %ecx; push %edx; \
1465 call *pv_cpu_ops+PV_CPU_read_cr0; \
1469 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1471 call *pv_cpu_ops+PV_CPU_swapgs; \
1475 #define GET_CR2_INTO_RCX \
1476 call *pv_mmu_ops+PV_MMU_read_cr2; \
1482 #endif /* __ASSEMBLY__ */
1483 #endif /* CONFIG_PARAVIRT */
1484 #endif /* __ASM_PARAVIRT_H */