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Merge branches 'x86/numa-fixes', 'x86/apic', 'x86/apm', 'x86/bitops', 'x86/build...
[deliverable/linux.git] / include / asm-x86 / paravirt.h
1 #ifndef __ASM_PARAVIRT_H
2 #define __ASM_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
5
6 #ifdef CONFIG_PARAVIRT
7 #include <asm/page.h>
8 #include <asm/asm.h>
9
10 /* Bitmask of what can be clobbered: usually at least eax. */
11 #define CLBR_NONE 0
12 #define CLBR_EAX (1 << 0)
13 #define CLBR_ECX (1 << 1)
14 #define CLBR_EDX (1 << 2)
15
16 #ifdef CONFIG_X86_64
17 #define CLBR_RSI (1 << 3)
18 #define CLBR_RDI (1 << 4)
19 #define CLBR_R8 (1 << 5)
20 #define CLBR_R9 (1 << 6)
21 #define CLBR_R10 (1 << 7)
22 #define CLBR_R11 (1 << 8)
23 #define CLBR_ANY ((1 << 9) - 1)
24 #include <asm/desc_defs.h>
25 #else
26 /* CLBR_ANY should match all regs platform has. For i386, that's just it */
27 #define CLBR_ANY ((1 << 3) - 1)
28 #endif /* X86_64 */
29
30 #ifndef __ASSEMBLY__
31 #include <linux/types.h>
32 #include <linux/cpumask.h>
33 #include <asm/kmap_types.h>
34 #include <asm/desc_defs.h>
35
36 struct page;
37 struct thread_struct;
38 struct desc_ptr;
39 struct tss_struct;
40 struct mm_struct;
41 struct desc_struct;
42
43 /* general info */
44 struct pv_info {
45 unsigned int kernel_rpl;
46 int shared_kernel_pmd;
47 int paravirt_enabled;
48 const char *name;
49 };
50
51 struct pv_init_ops {
52 /*
53 * Patch may replace one of the defined code sequences with
54 * arbitrary code, subject to the same register constraints.
55 * This generally means the code is not free to clobber any
56 * registers other than EAX. The patch function should return
57 * the number of bytes of code generated, as we nop pad the
58 * rest in generic code.
59 */
60 unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
61 unsigned long addr, unsigned len);
62
63 /* Basic arch-specific setup */
64 void (*arch_setup)(void);
65 char *(*memory_setup)(void);
66 void (*post_allocator_init)(void);
67
68 /* Print a banner to identify the environment */
69 void (*banner)(void);
70 };
71
72
73 struct pv_lazy_ops {
74 /* Set deferred update mode, used for batching operations. */
75 void (*enter)(void);
76 void (*leave)(void);
77 };
78
79 struct pv_time_ops {
80 void (*time_init)(void);
81
82 /* Set and set time of day */
83 unsigned long (*get_wallclock)(void);
84 int (*set_wallclock)(unsigned long);
85
86 unsigned long long (*sched_clock)(void);
87 unsigned long (*get_cpu_khz)(void);
88 };
89
90 struct pv_cpu_ops {
91 /* hooks for various privileged instructions */
92 unsigned long (*get_debugreg)(int regno);
93 void (*set_debugreg)(int regno, unsigned long value);
94
95 void (*clts)(void);
96
97 unsigned long (*read_cr0)(void);
98 void (*write_cr0)(unsigned long);
99
100 unsigned long (*read_cr4_safe)(void);
101 unsigned long (*read_cr4)(void);
102 void (*write_cr4)(unsigned long);
103
104 #ifdef CONFIG_X86_64
105 unsigned long (*read_cr8)(void);
106 void (*write_cr8)(unsigned long);
107 #endif
108
109 /* Segment descriptor handling */
110 void (*load_tr_desc)(void);
111 void (*load_gdt)(const struct desc_ptr *);
112 void (*load_idt)(const struct desc_ptr *);
113 void (*store_gdt)(struct desc_ptr *);
114 void (*store_idt)(struct desc_ptr *);
115 void (*set_ldt)(const void *desc, unsigned entries);
116 unsigned long (*store_tr)(void);
117 void (*load_tls)(struct thread_struct *t, unsigned int cpu);
118 void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
119 const void *desc);
120 void (*write_gdt_entry)(struct desc_struct *,
121 int entrynum, const void *desc, int size);
122 void (*write_idt_entry)(gate_desc *,
123 int entrynum, const gate_desc *gate);
124 void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
125
126 void (*set_iopl_mask)(unsigned mask);
127
128 void (*wbinvd)(void);
129 void (*io_delay)(void);
130
131 /* cpuid emulation, mostly so that caps bits can be disabled */
132 void (*cpuid)(unsigned int *eax, unsigned int *ebx,
133 unsigned int *ecx, unsigned int *edx);
134
135 /* MSR, PMC and TSR operations.
136 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
137 u64 (*read_msr)(unsigned int msr, int *err);
138 int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
139
140 u64 (*read_tsc)(void);
141 u64 (*read_pmc)(int counter);
142 unsigned long long (*read_tscp)(unsigned int *aux);
143
144 /* These two are jmp to, not actually called. */
145 void (*irq_enable_syscall_ret)(void);
146 void (*iret)(void);
147
148 void (*swapgs)(void);
149
150 struct pv_lazy_ops lazy_mode;
151 };
152
153 struct pv_irq_ops {
154 void (*init_IRQ)(void);
155
156 /*
157 * Get/set interrupt state. save_fl and restore_fl are only
158 * expected to use X86_EFLAGS_IF; all other bits
159 * returned from save_fl are undefined, and may be ignored by
160 * restore_fl.
161 */
162 unsigned long (*save_fl)(void);
163 void (*restore_fl)(unsigned long);
164 void (*irq_disable)(void);
165 void (*irq_enable)(void);
166 void (*safe_halt)(void);
167 void (*halt)(void);
168 };
169
170 struct pv_apic_ops {
171 #ifdef CONFIG_X86_LOCAL_APIC
172 /*
173 * Direct APIC operations, principally for VMI. Ideally
174 * these shouldn't be in this interface.
175 */
176 void (*apic_write)(unsigned long reg, u32 v);
177 void (*apic_write_atomic)(unsigned long reg, u32 v);
178 u32 (*apic_read)(unsigned long reg);
179 void (*setup_boot_clock)(void);
180 void (*setup_secondary_clock)(void);
181
182 void (*startup_ipi_hook)(int phys_apicid,
183 unsigned long start_eip,
184 unsigned long start_esp);
185 #endif
186 };
187
188 struct pv_mmu_ops {
189 /*
190 * Called before/after init_mm pagetable setup. setup_start
191 * may reset %cr3, and may pre-install parts of the pagetable;
192 * pagetable setup is expected to preserve any existing
193 * mapping.
194 */
195 void (*pagetable_setup_start)(pgd_t *pgd_base);
196 void (*pagetable_setup_done)(pgd_t *pgd_base);
197
198 unsigned long (*read_cr2)(void);
199 void (*write_cr2)(unsigned long);
200
201 unsigned long (*read_cr3)(void);
202 void (*write_cr3)(unsigned long);
203
204 /*
205 * Hooks for intercepting the creation/use/destruction of an
206 * mm_struct.
207 */
208 void (*activate_mm)(struct mm_struct *prev,
209 struct mm_struct *next);
210 void (*dup_mmap)(struct mm_struct *oldmm,
211 struct mm_struct *mm);
212 void (*exit_mmap)(struct mm_struct *mm);
213
214
215 /* TLB operations */
216 void (*flush_tlb_user)(void);
217 void (*flush_tlb_kernel)(void);
218 void (*flush_tlb_single)(unsigned long addr);
219 void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm,
220 unsigned long va);
221
222 /* Hooks for allocating/releasing pagetable pages */
223 void (*alloc_pte)(struct mm_struct *mm, u32 pfn);
224 void (*alloc_pmd)(struct mm_struct *mm, u32 pfn);
225 void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count);
226 void (*alloc_pud)(struct mm_struct *mm, u32 pfn);
227 void (*release_pte)(u32 pfn);
228 void (*release_pmd)(u32 pfn);
229 void (*release_pud)(u32 pfn);
230
231 /* Pagetable manipulation functions */
232 void (*set_pte)(pte_t *ptep, pte_t pteval);
233 void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
234 pte_t *ptep, pte_t pteval);
235 void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
236 void (*pte_update)(struct mm_struct *mm, unsigned long addr,
237 pte_t *ptep);
238 void (*pte_update_defer)(struct mm_struct *mm,
239 unsigned long addr, pte_t *ptep);
240
241 pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr,
242 pte_t *ptep);
243 void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr,
244 pte_t *ptep, pte_t pte);
245
246 pteval_t (*pte_val)(pte_t);
247 pteval_t (*pte_flags)(pte_t);
248 pte_t (*make_pte)(pteval_t pte);
249
250 pgdval_t (*pgd_val)(pgd_t);
251 pgd_t (*make_pgd)(pgdval_t pgd);
252
253 #if PAGETABLE_LEVELS >= 3
254 #ifdef CONFIG_X86_PAE
255 void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
256 void (*set_pte_present)(struct mm_struct *mm, unsigned long addr,
257 pte_t *ptep, pte_t pte);
258 void (*pte_clear)(struct mm_struct *mm, unsigned long addr,
259 pte_t *ptep);
260 void (*pmd_clear)(pmd_t *pmdp);
261
262 #endif /* CONFIG_X86_PAE */
263
264 void (*set_pud)(pud_t *pudp, pud_t pudval);
265
266 pmdval_t (*pmd_val)(pmd_t);
267 pmd_t (*make_pmd)(pmdval_t pmd);
268
269 #if PAGETABLE_LEVELS == 4
270 pudval_t (*pud_val)(pud_t);
271 pud_t (*make_pud)(pudval_t pud);
272
273 void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
274 #endif /* PAGETABLE_LEVELS == 4 */
275 #endif /* PAGETABLE_LEVELS >= 3 */
276
277 #ifdef CONFIG_HIGHPTE
278 void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
279 #endif
280
281 struct pv_lazy_ops lazy_mode;
282 };
283
284 /* This contains all the paravirt structures: we get a convenient
285 * number for each function using the offset which we use to indicate
286 * what to patch. */
287 struct paravirt_patch_template {
288 struct pv_init_ops pv_init_ops;
289 struct pv_time_ops pv_time_ops;
290 struct pv_cpu_ops pv_cpu_ops;
291 struct pv_irq_ops pv_irq_ops;
292 struct pv_apic_ops pv_apic_ops;
293 struct pv_mmu_ops pv_mmu_ops;
294 };
295
296 extern struct pv_info pv_info;
297 extern struct pv_init_ops pv_init_ops;
298 extern struct pv_time_ops pv_time_ops;
299 extern struct pv_cpu_ops pv_cpu_ops;
300 extern struct pv_irq_ops pv_irq_ops;
301 extern struct pv_apic_ops pv_apic_ops;
302 extern struct pv_mmu_ops pv_mmu_ops;
303
304 #define PARAVIRT_PATCH(x) \
305 (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
306
307 #define paravirt_type(op) \
308 [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \
309 [paravirt_opptr] "m" (op)
310 #define paravirt_clobber(clobber) \
311 [paravirt_clobber] "i" (clobber)
312
313 /*
314 * Generate some code, and mark it as patchable by the
315 * apply_paravirt() alternate instruction patcher.
316 */
317 #define _paravirt_alt(insn_string, type, clobber) \
318 "771:\n\t" insn_string "\n" "772:\n" \
319 ".pushsection .parainstructions,\"a\"\n" \
320 _ASM_ALIGN "\n" \
321 _ASM_PTR " 771b\n" \
322 " .byte " type "\n" \
323 " .byte 772b-771b\n" \
324 " .short " clobber "\n" \
325 ".popsection\n"
326
327 /* Generate patchable code, with the default asm parameters. */
328 #define paravirt_alt(insn_string) \
329 _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
330
331 /* Simple instruction patching code. */
332 #define DEF_NATIVE(ops, name, code) \
333 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
334 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
335
336 unsigned paravirt_patch_nop(void);
337 unsigned paravirt_patch_ignore(unsigned len);
338 unsigned paravirt_patch_call(void *insnbuf,
339 const void *target, u16 tgt_clobbers,
340 unsigned long addr, u16 site_clobbers,
341 unsigned len);
342 unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
343 unsigned long addr, unsigned len);
344 unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
345 unsigned long addr, unsigned len);
346
347 unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
348 const char *start, const char *end);
349
350 unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
351 unsigned long addr, unsigned len);
352
353 int paravirt_disable_iospace(void);
354
355 /*
356 * This generates an indirect call based on the operation type number.
357 * The type number, computed in PARAVIRT_PATCH, is derived from the
358 * offset into the paravirt_patch_template structure, and can therefore be
359 * freely converted back into a structure offset.
360 */
361 #define PARAVIRT_CALL "call *%[paravirt_opptr];"
362
363 /*
364 * These macros are intended to wrap calls through one of the paravirt
365 * ops structs, so that they can be later identified and patched at
366 * runtime.
367 *
368 * Normally, a call to a pv_op function is a simple indirect call:
369 * (pv_op_struct.operations)(args...).
370 *
371 * Unfortunately, this is a relatively slow operation for modern CPUs,
372 * because it cannot necessarily determine what the destination
373 * address is. In this case, the address is a runtime constant, so at
374 * the very least we can patch the call to e a simple direct call, or
375 * ideally, patch an inline implementation into the callsite. (Direct
376 * calls are essentially free, because the call and return addresses
377 * are completely predictable.)
378 *
379 * For i386, these macros rely on the standard gcc "regparm(3)" calling
380 * convention, in which the first three arguments are placed in %eax,
381 * %edx, %ecx (in that order), and the remaining arguments are placed
382 * on the stack. All caller-save registers (eax,edx,ecx) are expected
383 * to be modified (either clobbered or used for return values).
384 * X86_64, on the other hand, already specifies a register-based calling
385 * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
386 * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
387 * special handling for dealing with 4 arguments, unlike i386.
388 * However, x86_64 also have to clobber all caller saved registers, which
389 * unfortunately, are quite a bit (r8 - r11)
390 *
391 * The call instruction itself is marked by placing its start address
392 * and size into the .parainstructions section, so that
393 * apply_paravirt() in arch/i386/kernel/alternative.c can do the
394 * appropriate patching under the control of the backend pv_init_ops
395 * implementation.
396 *
397 * Unfortunately there's no way to get gcc to generate the args setup
398 * for the call, and then allow the call itself to be generated by an
399 * inline asm. Because of this, we must do the complete arg setup and
400 * return value handling from within these macros. This is fairly
401 * cumbersome.
402 *
403 * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
404 * It could be extended to more arguments, but there would be little
405 * to be gained from that. For each number of arguments, there are
406 * the two VCALL and CALL variants for void and non-void functions.
407 *
408 * When there is a return value, the invoker of the macro must specify
409 * the return type. The macro then uses sizeof() on that type to
410 * determine whether its a 32 or 64 bit value, and places the return
411 * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
412 * 64-bit). For x86_64 machines, it just returns at %rax regardless of
413 * the return value size.
414 *
415 * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
416 * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
417 * in low,high order
418 *
419 * Small structures are passed and returned in registers. The macro
420 * calling convention can't directly deal with this, so the wrapper
421 * functions must do this.
422 *
423 * These PVOP_* macros are only defined within this header. This
424 * means that all uses must be wrapped in inline functions. This also
425 * makes sure the incoming and outgoing types are always correct.
426 */
427 #ifdef CONFIG_X86_32
428 #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx
429 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS
430 #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \
431 "=c" (__ecx)
432 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS
433 #define EXTRA_CLOBBERS
434 #define VEXTRA_CLOBBERS
435 #else
436 #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx
437 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax
438 #define PVOP_VCALL_CLOBBERS "=D" (__edi), \
439 "=S" (__esi), "=d" (__edx), \
440 "=c" (__ecx)
441
442 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
443
444 #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11"
445 #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11"
446 #endif
447
448 #define __PVOP_CALL(rettype, op, pre, post, ...) \
449 ({ \
450 rettype __ret; \
451 PVOP_CALL_ARGS; \
452 /* This is 32-bit specific, but is okay in 64-bit */ \
453 /* since this condition will never hold */ \
454 if (sizeof(rettype) > sizeof(unsigned long)) { \
455 asm volatile(pre \
456 paravirt_alt(PARAVIRT_CALL) \
457 post \
458 : PVOP_CALL_CLOBBERS \
459 : paravirt_type(op), \
460 paravirt_clobber(CLBR_ANY), \
461 ##__VA_ARGS__ \
462 : "memory", "cc" EXTRA_CLOBBERS); \
463 __ret = (rettype)((((u64)__edx) << 32) | __eax); \
464 } else { \
465 asm volatile(pre \
466 paravirt_alt(PARAVIRT_CALL) \
467 post \
468 : PVOP_CALL_CLOBBERS \
469 : paravirt_type(op), \
470 paravirt_clobber(CLBR_ANY), \
471 ##__VA_ARGS__ \
472 : "memory", "cc" EXTRA_CLOBBERS); \
473 __ret = (rettype)__eax; \
474 } \
475 __ret; \
476 })
477 #define __PVOP_VCALL(op, pre, post, ...) \
478 ({ \
479 PVOP_VCALL_ARGS; \
480 asm volatile(pre \
481 paravirt_alt(PARAVIRT_CALL) \
482 post \
483 : PVOP_VCALL_CLOBBERS \
484 : paravirt_type(op), \
485 paravirt_clobber(CLBR_ANY), \
486 ##__VA_ARGS__ \
487 : "memory", "cc" VEXTRA_CLOBBERS); \
488 })
489
490 #define PVOP_CALL0(rettype, op) \
491 __PVOP_CALL(rettype, op, "", "")
492 #define PVOP_VCALL0(op) \
493 __PVOP_VCALL(op, "", "")
494
495 #define PVOP_CALL1(rettype, op, arg1) \
496 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)))
497 #define PVOP_VCALL1(op, arg1) \
498 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)))
499
500 #define PVOP_CALL2(rettype, op, arg1, arg2) \
501 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
502 "1" ((unsigned long)(arg2)))
503 #define PVOP_VCALL2(op, arg1, arg2) \
504 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
505 "1" ((unsigned long)(arg2)))
506
507 #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \
508 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
509 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
510 #define PVOP_VCALL3(op, arg1, arg2, arg3) \
511 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
512 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
513
514 /* This is the only difference in x86_64. We can make it much simpler */
515 #ifdef CONFIG_X86_32
516 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
517 __PVOP_CALL(rettype, op, \
518 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
519 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
520 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
521 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
522 __PVOP_VCALL(op, \
523 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
524 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
525 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
526 #else
527 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
528 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
529 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
530 "3"((unsigned long)(arg4)))
531 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
532 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
533 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
534 "3"((unsigned long)(arg4)))
535 #endif
536
537 static inline int paravirt_enabled(void)
538 {
539 return pv_info.paravirt_enabled;
540 }
541
542 static inline void load_sp0(struct tss_struct *tss,
543 struct thread_struct *thread)
544 {
545 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
546 }
547
548 #define ARCH_SETUP pv_init_ops.arch_setup();
549 static inline unsigned long get_wallclock(void)
550 {
551 return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
552 }
553
554 static inline int set_wallclock(unsigned long nowtime)
555 {
556 return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
557 }
558
559 static inline void (*choose_time_init(void))(void)
560 {
561 return pv_time_ops.time_init;
562 }
563
564 /* The paravirtualized CPUID instruction. */
565 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
566 unsigned int *ecx, unsigned int *edx)
567 {
568 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
569 }
570
571 /*
572 * These special macros can be used to get or set a debugging register
573 */
574 static inline unsigned long paravirt_get_debugreg(int reg)
575 {
576 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
577 }
578 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
579 static inline void set_debugreg(unsigned long val, int reg)
580 {
581 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
582 }
583
584 static inline void clts(void)
585 {
586 PVOP_VCALL0(pv_cpu_ops.clts);
587 }
588
589 static inline unsigned long read_cr0(void)
590 {
591 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
592 }
593
594 static inline void write_cr0(unsigned long x)
595 {
596 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
597 }
598
599 static inline unsigned long read_cr2(void)
600 {
601 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
602 }
603
604 static inline void write_cr2(unsigned long x)
605 {
606 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
607 }
608
609 static inline unsigned long read_cr3(void)
610 {
611 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
612 }
613
614 static inline void write_cr3(unsigned long x)
615 {
616 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
617 }
618
619 static inline unsigned long read_cr4(void)
620 {
621 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
622 }
623 static inline unsigned long read_cr4_safe(void)
624 {
625 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
626 }
627
628 static inline void write_cr4(unsigned long x)
629 {
630 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
631 }
632
633 #ifdef CONFIG_X86_64
634 static inline unsigned long read_cr8(void)
635 {
636 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
637 }
638
639 static inline void write_cr8(unsigned long x)
640 {
641 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
642 }
643 #endif
644
645 static inline void raw_safe_halt(void)
646 {
647 PVOP_VCALL0(pv_irq_ops.safe_halt);
648 }
649
650 static inline void halt(void)
651 {
652 PVOP_VCALL0(pv_irq_ops.safe_halt);
653 }
654
655 static inline void wbinvd(void)
656 {
657 PVOP_VCALL0(pv_cpu_ops.wbinvd);
658 }
659
660 #define get_kernel_rpl() (pv_info.kernel_rpl)
661
662 static inline u64 paravirt_read_msr(unsigned msr, int *err)
663 {
664 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
665 }
666 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
667 {
668 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
669 }
670
671 /* These should all do BUG_ON(_err), but our headers are too tangled. */
672 #define rdmsr(msr, val1, val2) \
673 do { \
674 int _err; \
675 u64 _l = paravirt_read_msr(msr, &_err); \
676 val1 = (u32)_l; \
677 val2 = _l >> 32; \
678 } while (0)
679
680 #define wrmsr(msr, val1, val2) \
681 do { \
682 paravirt_write_msr(msr, val1, val2); \
683 } while (0)
684
685 #define rdmsrl(msr, val) \
686 do { \
687 int _err; \
688 val = paravirt_read_msr(msr, &_err); \
689 } while (0)
690
691 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
692 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b)
693
694 /* rdmsr with exception handling */
695 #define rdmsr_safe(msr, a, b) \
696 ({ \
697 int _err; \
698 u64 _l = paravirt_read_msr(msr, &_err); \
699 (*a) = (u32)_l; \
700 (*b) = _l >> 32; \
701 _err; \
702 })
703
704 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
705 {
706 int err;
707
708 *p = paravirt_read_msr(msr, &err);
709 return err;
710 }
711
712 static inline u64 paravirt_read_tsc(void)
713 {
714 return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
715 }
716
717 #define rdtscl(low) \
718 do { \
719 u64 _l = paravirt_read_tsc(); \
720 low = (int)_l; \
721 } while (0)
722
723 #define rdtscll(val) (val = paravirt_read_tsc())
724
725 static inline unsigned long long paravirt_sched_clock(void)
726 {
727 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
728 }
729 #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz())
730
731 static inline unsigned long long paravirt_read_pmc(int counter)
732 {
733 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
734 }
735
736 #define rdpmc(counter, low, high) \
737 do { \
738 u64 _l = paravirt_read_pmc(counter); \
739 low = (u32)_l; \
740 high = _l >> 32; \
741 } while (0)
742
743 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
744 {
745 return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
746 }
747
748 #define rdtscp(low, high, aux) \
749 do { \
750 int __aux; \
751 unsigned long __val = paravirt_rdtscp(&__aux); \
752 (low) = (u32)__val; \
753 (high) = (u32)(__val >> 32); \
754 (aux) = __aux; \
755 } while (0)
756
757 #define rdtscpll(val, aux) \
758 do { \
759 unsigned long __aux; \
760 val = paravirt_rdtscp(&__aux); \
761 (aux) = __aux; \
762 } while (0)
763
764 static inline void load_TR_desc(void)
765 {
766 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
767 }
768 static inline void load_gdt(const struct desc_ptr *dtr)
769 {
770 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
771 }
772 static inline void load_idt(const struct desc_ptr *dtr)
773 {
774 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
775 }
776 static inline void set_ldt(const void *addr, unsigned entries)
777 {
778 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
779 }
780 static inline void store_gdt(struct desc_ptr *dtr)
781 {
782 PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
783 }
784 static inline void store_idt(struct desc_ptr *dtr)
785 {
786 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
787 }
788 static inline unsigned long paravirt_store_tr(void)
789 {
790 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
791 }
792 #define store_tr(tr) ((tr) = paravirt_store_tr())
793 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
794 {
795 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
796 }
797
798 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
799 const void *desc)
800 {
801 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
802 }
803
804 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
805 void *desc, int type)
806 {
807 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
808 }
809
810 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
811 {
812 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
813 }
814 static inline void set_iopl_mask(unsigned mask)
815 {
816 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
817 }
818
819 /* The paravirtualized I/O functions */
820 static inline void slow_down_io(void)
821 {
822 pv_cpu_ops.io_delay();
823 #ifdef REALLY_SLOW_IO
824 pv_cpu_ops.io_delay();
825 pv_cpu_ops.io_delay();
826 pv_cpu_ops.io_delay();
827 #endif
828 }
829
830 #ifdef CONFIG_X86_LOCAL_APIC
831 /*
832 * Basic functions accessing APICs.
833 */
834 static inline void apic_write(unsigned long reg, u32 v)
835 {
836 PVOP_VCALL2(pv_apic_ops.apic_write, reg, v);
837 }
838
839 static inline void apic_write_atomic(unsigned long reg, u32 v)
840 {
841 PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v);
842 }
843
844 static inline u32 apic_read(unsigned long reg)
845 {
846 return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg);
847 }
848
849 static inline void setup_boot_clock(void)
850 {
851 PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
852 }
853
854 static inline void setup_secondary_clock(void)
855 {
856 PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
857 }
858 #endif
859
860 static inline void paravirt_post_allocator_init(void)
861 {
862 if (pv_init_ops.post_allocator_init)
863 (*pv_init_ops.post_allocator_init)();
864 }
865
866 static inline void paravirt_pagetable_setup_start(pgd_t *base)
867 {
868 (*pv_mmu_ops.pagetable_setup_start)(base);
869 }
870
871 static inline void paravirt_pagetable_setup_done(pgd_t *base)
872 {
873 (*pv_mmu_ops.pagetable_setup_done)(base);
874 }
875
876 #ifdef CONFIG_SMP
877 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
878 unsigned long start_esp)
879 {
880 PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
881 phys_apicid, start_eip, start_esp);
882 }
883 #endif
884
885 static inline void paravirt_activate_mm(struct mm_struct *prev,
886 struct mm_struct *next)
887 {
888 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
889 }
890
891 static inline void arch_dup_mmap(struct mm_struct *oldmm,
892 struct mm_struct *mm)
893 {
894 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
895 }
896
897 static inline void arch_exit_mmap(struct mm_struct *mm)
898 {
899 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
900 }
901
902 static inline void __flush_tlb(void)
903 {
904 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
905 }
906 static inline void __flush_tlb_global(void)
907 {
908 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
909 }
910 static inline void __flush_tlb_single(unsigned long addr)
911 {
912 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
913 }
914
915 static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
916 unsigned long va)
917 {
918 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va);
919 }
920
921 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn)
922 {
923 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
924 }
925 static inline void paravirt_release_pte(unsigned pfn)
926 {
927 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
928 }
929
930 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned pfn)
931 {
932 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
933 }
934
935 static inline void paravirt_alloc_pmd_clone(unsigned pfn, unsigned clonepfn,
936 unsigned start, unsigned count)
937 {
938 PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count);
939 }
940 static inline void paravirt_release_pmd(unsigned pfn)
941 {
942 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
943 }
944
945 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned pfn)
946 {
947 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
948 }
949 static inline void paravirt_release_pud(unsigned pfn)
950 {
951 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
952 }
953
954 #ifdef CONFIG_HIGHPTE
955 static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
956 {
957 unsigned long ret;
958 ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
959 return (void *)ret;
960 }
961 #endif
962
963 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
964 pte_t *ptep)
965 {
966 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
967 }
968
969 static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
970 pte_t *ptep)
971 {
972 PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
973 }
974
975 static inline pte_t __pte(pteval_t val)
976 {
977 pteval_t ret;
978
979 if (sizeof(pteval_t) > sizeof(long))
980 ret = PVOP_CALL2(pteval_t,
981 pv_mmu_ops.make_pte,
982 val, (u64)val >> 32);
983 else
984 ret = PVOP_CALL1(pteval_t,
985 pv_mmu_ops.make_pte,
986 val);
987
988 return (pte_t) { .pte = ret };
989 }
990
991 static inline pteval_t pte_val(pte_t pte)
992 {
993 pteval_t ret;
994
995 if (sizeof(pteval_t) > sizeof(long))
996 ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val,
997 pte.pte, (u64)pte.pte >> 32);
998 else
999 ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val,
1000 pte.pte);
1001
1002 return ret;
1003 }
1004
1005 static inline pteval_t pte_flags(pte_t pte)
1006 {
1007 pteval_t ret;
1008
1009 if (sizeof(pteval_t) > sizeof(long))
1010 ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_flags,
1011 pte.pte, (u64)pte.pte >> 32);
1012 else
1013 ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_flags,
1014 pte.pte);
1015
1016 return ret;
1017 }
1018
1019 static inline pgd_t __pgd(pgdval_t val)
1020 {
1021 pgdval_t ret;
1022
1023 if (sizeof(pgdval_t) > sizeof(long))
1024 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd,
1025 val, (u64)val >> 32);
1026 else
1027 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd,
1028 val);
1029
1030 return (pgd_t) { ret };
1031 }
1032
1033 static inline pgdval_t pgd_val(pgd_t pgd)
1034 {
1035 pgdval_t ret;
1036
1037 if (sizeof(pgdval_t) > sizeof(long))
1038 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val,
1039 pgd.pgd, (u64)pgd.pgd >> 32);
1040 else
1041 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val,
1042 pgd.pgd);
1043
1044 return ret;
1045 }
1046
1047 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1048 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
1049 pte_t *ptep)
1050 {
1051 pteval_t ret;
1052
1053 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
1054 mm, addr, ptep);
1055
1056 return (pte_t) { .pte = ret };
1057 }
1058
1059 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
1060 pte_t *ptep, pte_t pte)
1061 {
1062 if (sizeof(pteval_t) > sizeof(long))
1063 /* 5 arg words */
1064 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
1065 else
1066 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
1067 mm, addr, ptep, pte.pte);
1068 }
1069
1070 static inline void set_pte(pte_t *ptep, pte_t pte)
1071 {
1072 if (sizeof(pteval_t) > sizeof(long))
1073 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
1074 pte.pte, (u64)pte.pte >> 32);
1075 else
1076 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
1077 pte.pte);
1078 }
1079
1080 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
1081 pte_t *ptep, pte_t pte)
1082 {
1083 if (sizeof(pteval_t) > sizeof(long))
1084 /* 5 arg words */
1085 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
1086 else
1087 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
1088 }
1089
1090 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
1091 {
1092 pmdval_t val = native_pmd_val(pmd);
1093
1094 if (sizeof(pmdval_t) > sizeof(long))
1095 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
1096 else
1097 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
1098 }
1099
1100 #if PAGETABLE_LEVELS >= 3
1101 static inline pmd_t __pmd(pmdval_t val)
1102 {
1103 pmdval_t ret;
1104
1105 if (sizeof(pmdval_t) > sizeof(long))
1106 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd,
1107 val, (u64)val >> 32);
1108 else
1109 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd,
1110 val);
1111
1112 return (pmd_t) { ret };
1113 }
1114
1115 static inline pmdval_t pmd_val(pmd_t pmd)
1116 {
1117 pmdval_t ret;
1118
1119 if (sizeof(pmdval_t) > sizeof(long))
1120 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val,
1121 pmd.pmd, (u64)pmd.pmd >> 32);
1122 else
1123 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val,
1124 pmd.pmd);
1125
1126 return ret;
1127 }
1128
1129 static inline void set_pud(pud_t *pudp, pud_t pud)
1130 {
1131 pudval_t val = native_pud_val(pud);
1132
1133 if (sizeof(pudval_t) > sizeof(long))
1134 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
1135 val, (u64)val >> 32);
1136 else
1137 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
1138 val);
1139 }
1140 #if PAGETABLE_LEVELS == 4
1141 static inline pud_t __pud(pudval_t val)
1142 {
1143 pudval_t ret;
1144
1145 if (sizeof(pudval_t) > sizeof(long))
1146 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud,
1147 val, (u64)val >> 32);
1148 else
1149 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud,
1150 val);
1151
1152 return (pud_t) { ret };
1153 }
1154
1155 static inline pudval_t pud_val(pud_t pud)
1156 {
1157 pudval_t ret;
1158
1159 if (sizeof(pudval_t) > sizeof(long))
1160 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val,
1161 pud.pud, (u64)pud.pud >> 32);
1162 else
1163 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val,
1164 pud.pud);
1165
1166 return ret;
1167 }
1168
1169 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
1170 {
1171 pgdval_t val = native_pgd_val(pgd);
1172
1173 if (sizeof(pgdval_t) > sizeof(long))
1174 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
1175 val, (u64)val >> 32);
1176 else
1177 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
1178 val);
1179 }
1180
1181 static inline void pgd_clear(pgd_t *pgdp)
1182 {
1183 set_pgd(pgdp, __pgd(0));
1184 }
1185
1186 static inline void pud_clear(pud_t *pudp)
1187 {
1188 set_pud(pudp, __pud(0));
1189 }
1190
1191 #endif /* PAGETABLE_LEVELS == 4 */
1192
1193 #endif /* PAGETABLE_LEVELS >= 3 */
1194
1195 #ifdef CONFIG_X86_PAE
1196 /* Special-case pte-setting operations for PAE, which can't update a
1197 64-bit pte atomically */
1198 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1199 {
1200 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
1201 pte.pte, pte.pte >> 32);
1202 }
1203
1204 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1205 pte_t *ptep, pte_t pte)
1206 {
1207 /* 5 arg words */
1208 pv_mmu_ops.set_pte_present(mm, addr, ptep, pte);
1209 }
1210
1211 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1212 pte_t *ptep)
1213 {
1214 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
1215 }
1216
1217 static inline void pmd_clear(pmd_t *pmdp)
1218 {
1219 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
1220 }
1221 #else /* !CONFIG_X86_PAE */
1222 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1223 {
1224 set_pte(ptep, pte);
1225 }
1226
1227 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1228 pte_t *ptep, pte_t pte)
1229 {
1230 set_pte(ptep, pte);
1231 }
1232
1233 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1234 pte_t *ptep)
1235 {
1236 set_pte_at(mm, addr, ptep, __pte(0));
1237 }
1238
1239 static inline void pmd_clear(pmd_t *pmdp)
1240 {
1241 set_pmd(pmdp, __pmd(0));
1242 }
1243 #endif /* CONFIG_X86_PAE */
1244
1245 /* Lazy mode for batching updates / context switch */
1246 enum paravirt_lazy_mode {
1247 PARAVIRT_LAZY_NONE,
1248 PARAVIRT_LAZY_MMU,
1249 PARAVIRT_LAZY_CPU,
1250 };
1251
1252 enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
1253 void paravirt_enter_lazy_cpu(void);
1254 void paravirt_leave_lazy_cpu(void);
1255 void paravirt_enter_lazy_mmu(void);
1256 void paravirt_leave_lazy_mmu(void);
1257 void paravirt_leave_lazy(enum paravirt_lazy_mode mode);
1258
1259 #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE
1260 static inline void arch_enter_lazy_cpu_mode(void)
1261 {
1262 PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter);
1263 }
1264
1265 static inline void arch_leave_lazy_cpu_mode(void)
1266 {
1267 PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
1268 }
1269
1270 static inline void arch_flush_lazy_cpu_mode(void)
1271 {
1272 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
1273 arch_leave_lazy_cpu_mode();
1274 arch_enter_lazy_cpu_mode();
1275 }
1276 }
1277
1278
1279 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1280 static inline void arch_enter_lazy_mmu_mode(void)
1281 {
1282 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
1283 }
1284
1285 static inline void arch_leave_lazy_mmu_mode(void)
1286 {
1287 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
1288 }
1289
1290 static inline void arch_flush_lazy_mmu_mode(void)
1291 {
1292 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
1293 arch_leave_lazy_mmu_mode();
1294 arch_enter_lazy_mmu_mode();
1295 }
1296 }
1297
1298 void _paravirt_nop(void);
1299 #define paravirt_nop ((void *)_paravirt_nop)
1300
1301 /* These all sit in the .parainstructions section to tell us what to patch. */
1302 struct paravirt_patch_site {
1303 u8 *instr; /* original instructions */
1304 u8 instrtype; /* type of this instruction */
1305 u8 len; /* length of original instruction */
1306 u16 clobbers; /* what registers you may clobber */
1307 };
1308
1309 extern struct paravirt_patch_site __parainstructions[],
1310 __parainstructions_end[];
1311
1312 #ifdef CONFIG_X86_32
1313 #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;"
1314 #define PV_RESTORE_REGS "popl %%edx; popl %%ecx"
1315 #define PV_FLAGS_ARG "0"
1316 #define PV_EXTRA_CLOBBERS
1317 #define PV_VEXTRA_CLOBBERS
1318 #else
1319 /* We save some registers, but all of them, that's too much. We clobber all
1320 * caller saved registers but the argument parameter */
1321 #define PV_SAVE_REGS "pushq %%rdi;"
1322 #define PV_RESTORE_REGS "popq %%rdi;"
1323 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx"
1324 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx"
1325 #define PV_FLAGS_ARG "D"
1326 #endif
1327
1328 static inline unsigned long __raw_local_save_flags(void)
1329 {
1330 unsigned long f;
1331
1332 asm volatile(paravirt_alt(PV_SAVE_REGS
1333 PARAVIRT_CALL
1334 PV_RESTORE_REGS)
1335 : "=a"(f)
1336 : paravirt_type(pv_irq_ops.save_fl),
1337 paravirt_clobber(CLBR_EAX)
1338 : "memory", "cc" PV_VEXTRA_CLOBBERS);
1339 return f;
1340 }
1341
1342 static inline void raw_local_irq_restore(unsigned long f)
1343 {
1344 asm volatile(paravirt_alt(PV_SAVE_REGS
1345 PARAVIRT_CALL
1346 PV_RESTORE_REGS)
1347 : "=a"(f)
1348 : PV_FLAGS_ARG(f),
1349 paravirt_type(pv_irq_ops.restore_fl),
1350 paravirt_clobber(CLBR_EAX)
1351 : "memory", "cc" PV_EXTRA_CLOBBERS);
1352 }
1353
1354 static inline void raw_local_irq_disable(void)
1355 {
1356 asm volatile(paravirt_alt(PV_SAVE_REGS
1357 PARAVIRT_CALL
1358 PV_RESTORE_REGS)
1359 :
1360 : paravirt_type(pv_irq_ops.irq_disable),
1361 paravirt_clobber(CLBR_EAX)
1362 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1363 }
1364
1365 static inline void raw_local_irq_enable(void)
1366 {
1367 asm volatile(paravirt_alt(PV_SAVE_REGS
1368 PARAVIRT_CALL
1369 PV_RESTORE_REGS)
1370 :
1371 : paravirt_type(pv_irq_ops.irq_enable),
1372 paravirt_clobber(CLBR_EAX)
1373 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1374 }
1375
1376 static inline unsigned long __raw_local_irq_save(void)
1377 {
1378 unsigned long f;
1379
1380 f = __raw_local_save_flags();
1381 raw_local_irq_disable();
1382 return f;
1383 }
1384
1385 /* Make sure as little as possible of this mess escapes. */
1386 #undef PARAVIRT_CALL
1387 #undef __PVOP_CALL
1388 #undef __PVOP_VCALL
1389 #undef PVOP_VCALL0
1390 #undef PVOP_CALL0
1391 #undef PVOP_VCALL1
1392 #undef PVOP_CALL1
1393 #undef PVOP_VCALL2
1394 #undef PVOP_CALL2
1395 #undef PVOP_VCALL3
1396 #undef PVOP_CALL3
1397 #undef PVOP_VCALL4
1398 #undef PVOP_CALL4
1399
1400 #else /* __ASSEMBLY__ */
1401
1402 #define _PVSITE(ptype, clobbers, ops, word, algn) \
1403 771:; \
1404 ops; \
1405 772:; \
1406 .pushsection .parainstructions,"a"; \
1407 .align algn; \
1408 word 771b; \
1409 .byte ptype; \
1410 .byte 772b-771b; \
1411 .short clobbers; \
1412 .popsection
1413
1414
1415 #ifdef CONFIG_X86_64
1416 #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx
1417 #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax
1418 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
1419 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
1420 #else
1421 #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx
1422 #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
1423 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
1424 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
1425 #endif
1426
1427 #define INTERRUPT_RETURN \
1428 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
1429 jmp *%cs:pv_cpu_ops+PV_CPU_iret)
1430
1431 #define DISABLE_INTERRUPTS(clobbers) \
1432 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
1433 PV_SAVE_REGS; \
1434 call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \
1435 PV_RESTORE_REGS;) \
1436
1437 #define ENABLE_INTERRUPTS(clobbers) \
1438 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
1439 PV_SAVE_REGS; \
1440 call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \
1441 PV_RESTORE_REGS;)
1442
1443 #define ENABLE_INTERRUPTS_SYSCALL_RET \
1444 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\
1445 CLBR_NONE, \
1446 jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret)
1447
1448
1449 #ifdef CONFIG_X86_32
1450 #define GET_CR0_INTO_EAX \
1451 push %ecx; push %edx; \
1452 call *pv_cpu_ops+PV_CPU_read_cr0; \
1453 pop %edx; pop %ecx
1454 #else
1455 #define SWAPGS \
1456 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1457 PV_SAVE_REGS; \
1458 call *pv_cpu_ops+PV_CPU_swapgs; \
1459 PV_RESTORE_REGS \
1460 )
1461
1462 #define GET_CR2_INTO_RCX \
1463 call *pv_mmu_ops+PV_MMU_read_cr2; \
1464 movq %rax, %rcx; \
1465 xorq %rax, %rax;
1466
1467 #endif
1468
1469 #endif /* __ASSEMBLY__ */
1470 #endif /* CONFIG_PARAVIRT */
1471 #endif /* __ASM_PARAVIRT_H */
Linux kernel - Deliverables
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