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x86/paravirt/xen: add set_fixmap pv_mmu_ops
[deliverable/linux.git] / include / asm-x86 / paravirt.h
1 #ifndef __ASM_PARAVIRT_H
2 #define __ASM_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
5
6 #ifdef CONFIG_PARAVIRT
7 #include <asm/page.h>
8 #include <asm/asm.h>
9
10 /* Bitmask of what can be clobbered: usually at least eax. */
11 #define CLBR_NONE 0
12 #define CLBR_EAX (1 << 0)
13 #define CLBR_ECX (1 << 1)
14 #define CLBR_EDX (1 << 2)
15
16 #ifdef CONFIG_X86_64
17 #define CLBR_RSI (1 << 3)
18 #define CLBR_RDI (1 << 4)
19 #define CLBR_R8 (1 << 5)
20 #define CLBR_R9 (1 << 6)
21 #define CLBR_R10 (1 << 7)
22 #define CLBR_R11 (1 << 8)
23 #define CLBR_ANY ((1 << 9) - 1)
24 #include <asm/desc_defs.h>
25 #else
26 /* CLBR_ANY should match all regs platform has. For i386, that's just it */
27 #define CLBR_ANY ((1 << 3) - 1)
28 #endif /* X86_64 */
29
30 #ifndef __ASSEMBLY__
31 #include <linux/types.h>
32 #include <linux/cpumask.h>
33 #include <asm/kmap_types.h>
34 #include <asm/desc_defs.h>
35
36 struct page;
37 struct thread_struct;
38 struct desc_ptr;
39 struct tss_struct;
40 struct mm_struct;
41 struct desc_struct;
42
43 /* general info */
44 struct pv_info {
45 unsigned int kernel_rpl;
46 int shared_kernel_pmd;
47 int paravirt_enabled;
48 const char *name;
49 };
50
51 struct pv_init_ops {
52 /*
53 * Patch may replace one of the defined code sequences with
54 * arbitrary code, subject to the same register constraints.
55 * This generally means the code is not free to clobber any
56 * registers other than EAX. The patch function should return
57 * the number of bytes of code generated, as we nop pad the
58 * rest in generic code.
59 */
60 unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
61 unsigned long addr, unsigned len);
62
63 /* Basic arch-specific setup */
64 void (*arch_setup)(void);
65 char *(*memory_setup)(void);
66 void (*post_allocator_init)(void);
67
68 /* Print a banner to identify the environment */
69 void (*banner)(void);
70 };
71
72
73 struct pv_lazy_ops {
74 /* Set deferred update mode, used for batching operations. */
75 void (*enter)(void);
76 void (*leave)(void);
77 };
78
79 struct pv_time_ops {
80 void (*time_init)(void);
81
82 /* Set and set time of day */
83 unsigned long (*get_wallclock)(void);
84 int (*set_wallclock)(unsigned long);
85
86 unsigned long long (*sched_clock)(void);
87 unsigned long (*get_cpu_khz)(void);
88 };
89
90 struct pv_cpu_ops {
91 /* hooks for various privileged instructions */
92 unsigned long (*get_debugreg)(int regno);
93 void (*set_debugreg)(int regno, unsigned long value);
94
95 void (*clts)(void);
96
97 unsigned long (*read_cr0)(void);
98 void (*write_cr0)(unsigned long);
99
100 unsigned long (*read_cr4_safe)(void);
101 unsigned long (*read_cr4)(void);
102 void (*write_cr4)(unsigned long);
103
104 #ifdef CONFIG_X86_64
105 unsigned long (*read_cr8)(void);
106 void (*write_cr8)(unsigned long);
107 #endif
108
109 /* Segment descriptor handling */
110 void (*load_tr_desc)(void);
111 void (*load_gdt)(const struct desc_ptr *);
112 void (*load_idt)(const struct desc_ptr *);
113 void (*store_gdt)(struct desc_ptr *);
114 void (*store_idt)(struct desc_ptr *);
115 void (*set_ldt)(const void *desc, unsigned entries);
116 unsigned long (*store_tr)(void);
117 void (*load_tls)(struct thread_struct *t, unsigned int cpu);
118 void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
119 const void *desc);
120 void (*write_gdt_entry)(struct desc_struct *,
121 int entrynum, const void *desc, int size);
122 void (*write_idt_entry)(gate_desc *,
123 int entrynum, const gate_desc *gate);
124 void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
125
126 void (*set_iopl_mask)(unsigned mask);
127
128 void (*wbinvd)(void);
129 void (*io_delay)(void);
130
131 /* cpuid emulation, mostly so that caps bits can be disabled */
132 void (*cpuid)(unsigned int *eax, unsigned int *ebx,
133 unsigned int *ecx, unsigned int *edx);
134
135 /* MSR, PMC and TSR operations.
136 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
137 u64 (*read_msr)(unsigned int msr, int *err);
138 int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
139
140 u64 (*read_tsc)(void);
141 u64 (*read_pmc)(int counter);
142 unsigned long long (*read_tscp)(unsigned int *aux);
143
144 /* These two are jmp to, not actually called. */
145 void (*irq_enable_syscall_ret)(void);
146 void (*iret)(void);
147
148 void (*swapgs)(void);
149
150 struct pv_lazy_ops lazy_mode;
151 };
152
153 struct pv_irq_ops {
154 void (*init_IRQ)(void);
155
156 /*
157 * Get/set interrupt state. save_fl and restore_fl are only
158 * expected to use X86_EFLAGS_IF; all other bits
159 * returned from save_fl are undefined, and may be ignored by
160 * restore_fl.
161 */
162 unsigned long (*save_fl)(void);
163 void (*restore_fl)(unsigned long);
164 void (*irq_disable)(void);
165 void (*irq_enable)(void);
166 void (*safe_halt)(void);
167 void (*halt)(void);
168 };
169
170 struct pv_apic_ops {
171 #ifdef CONFIG_X86_LOCAL_APIC
172 /*
173 * Direct APIC operations, principally for VMI. Ideally
174 * these shouldn't be in this interface.
175 */
176 void (*apic_write)(unsigned long reg, u32 v);
177 void (*apic_write_atomic)(unsigned long reg, u32 v);
178 u32 (*apic_read)(unsigned long reg);
179 void (*setup_boot_clock)(void);
180 void (*setup_secondary_clock)(void);
181
182 void (*startup_ipi_hook)(int phys_apicid,
183 unsigned long start_eip,
184 unsigned long start_esp);
185 #endif
186 };
187
188 struct pv_mmu_ops {
189 /*
190 * Called before/after init_mm pagetable setup. setup_start
191 * may reset %cr3, and may pre-install parts of the pagetable;
192 * pagetable setup is expected to preserve any existing
193 * mapping.
194 */
195 void (*pagetable_setup_start)(pgd_t *pgd_base);
196 void (*pagetable_setup_done)(pgd_t *pgd_base);
197
198 unsigned long (*read_cr2)(void);
199 void (*write_cr2)(unsigned long);
200
201 unsigned long (*read_cr3)(void);
202 void (*write_cr3)(unsigned long);
203
204 /*
205 * Hooks for intercepting the creation/use/destruction of an
206 * mm_struct.
207 */
208 void (*activate_mm)(struct mm_struct *prev,
209 struct mm_struct *next);
210 void (*dup_mmap)(struct mm_struct *oldmm,
211 struct mm_struct *mm);
212 void (*exit_mmap)(struct mm_struct *mm);
213
214
215 /* TLB operations */
216 void (*flush_tlb_user)(void);
217 void (*flush_tlb_kernel)(void);
218 void (*flush_tlb_single)(unsigned long addr);
219 void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm,
220 unsigned long va);
221
222 /* Hooks for allocating/releasing pagetable pages */
223 void (*alloc_pte)(struct mm_struct *mm, u32 pfn);
224 void (*alloc_pmd)(struct mm_struct *mm, u32 pfn);
225 void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count);
226 void (*alloc_pud)(struct mm_struct *mm, u32 pfn);
227 void (*release_pte)(u32 pfn);
228 void (*release_pmd)(u32 pfn);
229 void (*release_pud)(u32 pfn);
230
231 /* Pagetable manipulation functions */
232 void (*set_pte)(pte_t *ptep, pte_t pteval);
233 void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
234 pte_t *ptep, pte_t pteval);
235 void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
236 void (*pte_update)(struct mm_struct *mm, unsigned long addr,
237 pte_t *ptep);
238 void (*pte_update_defer)(struct mm_struct *mm,
239 unsigned long addr, pte_t *ptep);
240
241 pteval_t (*pte_val)(pte_t);
242 pte_t (*make_pte)(pteval_t pte);
243
244 pgdval_t (*pgd_val)(pgd_t);
245 pgd_t (*make_pgd)(pgdval_t pgd);
246
247 #if PAGETABLE_LEVELS >= 3
248 #ifdef CONFIG_X86_PAE
249 void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
250 void (*set_pte_present)(struct mm_struct *mm, unsigned long addr,
251 pte_t *ptep, pte_t pte);
252 void (*pte_clear)(struct mm_struct *mm, unsigned long addr,
253 pte_t *ptep);
254 void (*pmd_clear)(pmd_t *pmdp);
255
256 #endif /* CONFIG_X86_PAE */
257
258 void (*set_pud)(pud_t *pudp, pud_t pudval);
259
260 pmdval_t (*pmd_val)(pmd_t);
261 pmd_t (*make_pmd)(pmdval_t pmd);
262
263 #if PAGETABLE_LEVELS == 4
264 pudval_t (*pud_val)(pud_t);
265 pud_t (*make_pud)(pudval_t pud);
266
267 void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
268 #endif /* PAGETABLE_LEVELS == 4 */
269 #endif /* PAGETABLE_LEVELS >= 3 */
270
271 #ifdef CONFIG_HIGHPTE
272 void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
273 #endif
274
275 struct pv_lazy_ops lazy_mode;
276
277 /* dom0 ops */
278
279 /* Sometimes the physical address is a pfn, and sometimes its
280 an mfn. We can tell which is which from the index. */
281 void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx,
282 unsigned long phys, pgprot_t flags);
283 };
284
285 /* This contains all the paravirt structures: we get a convenient
286 * number for each function using the offset which we use to indicate
287 * what to patch. */
288 struct paravirt_patch_template {
289 struct pv_init_ops pv_init_ops;
290 struct pv_time_ops pv_time_ops;
291 struct pv_cpu_ops pv_cpu_ops;
292 struct pv_irq_ops pv_irq_ops;
293 struct pv_apic_ops pv_apic_ops;
294 struct pv_mmu_ops pv_mmu_ops;
295 };
296
297 extern struct pv_info pv_info;
298 extern struct pv_init_ops pv_init_ops;
299 extern struct pv_time_ops pv_time_ops;
300 extern struct pv_cpu_ops pv_cpu_ops;
301 extern struct pv_irq_ops pv_irq_ops;
302 extern struct pv_apic_ops pv_apic_ops;
303 extern struct pv_mmu_ops pv_mmu_ops;
304
305 #define PARAVIRT_PATCH(x) \
306 (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
307
308 #define paravirt_type(op) \
309 [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \
310 [paravirt_opptr] "m" (op)
311 #define paravirt_clobber(clobber) \
312 [paravirt_clobber] "i" (clobber)
313
314 /*
315 * Generate some code, and mark it as patchable by the
316 * apply_paravirt() alternate instruction patcher.
317 */
318 #define _paravirt_alt(insn_string, type, clobber) \
319 "771:\n\t" insn_string "\n" "772:\n" \
320 ".pushsection .parainstructions,\"a\"\n" \
321 _ASM_ALIGN "\n" \
322 _ASM_PTR " 771b\n" \
323 " .byte " type "\n" \
324 " .byte 772b-771b\n" \
325 " .short " clobber "\n" \
326 ".popsection\n"
327
328 /* Generate patchable code, with the default asm parameters. */
329 #define paravirt_alt(insn_string) \
330 _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
331
332 /* Simple instruction patching code. */
333 #define DEF_NATIVE(ops, name, code) \
334 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
335 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
336
337 unsigned paravirt_patch_nop(void);
338 unsigned paravirt_patch_ignore(unsigned len);
339 unsigned paravirt_patch_call(void *insnbuf,
340 const void *target, u16 tgt_clobbers,
341 unsigned long addr, u16 site_clobbers,
342 unsigned len);
343 unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
344 unsigned long addr, unsigned len);
345 unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
346 unsigned long addr, unsigned len);
347
348 unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
349 const char *start, const char *end);
350
351 unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
352 unsigned long addr, unsigned len);
353
354 int paravirt_disable_iospace(void);
355
356 /*
357 * This generates an indirect call based on the operation type number.
358 * The type number, computed in PARAVIRT_PATCH, is derived from the
359 * offset into the paravirt_patch_template structure, and can therefore be
360 * freely converted back into a structure offset.
361 */
362 #define PARAVIRT_CALL "call *%[paravirt_opptr];"
363
364 /*
365 * These macros are intended to wrap calls through one of the paravirt
366 * ops structs, so that they can be later identified and patched at
367 * runtime.
368 *
369 * Normally, a call to a pv_op function is a simple indirect call:
370 * (pv_op_struct.operations)(args...).
371 *
372 * Unfortunately, this is a relatively slow operation for modern CPUs,
373 * because it cannot necessarily determine what the destination
374 * address is. In this case, the address is a runtime constant, so at
375 * the very least we can patch the call to e a simple direct call, or
376 * ideally, patch an inline implementation into the callsite. (Direct
377 * calls are essentially free, because the call and return addresses
378 * are completely predictable.)
379 *
380 * For i386, these macros rely on the standard gcc "regparm(3)" calling
381 * convention, in which the first three arguments are placed in %eax,
382 * %edx, %ecx (in that order), and the remaining arguments are placed
383 * on the stack. All caller-save registers (eax,edx,ecx) are expected
384 * to be modified (either clobbered or used for return values).
385 * X86_64, on the other hand, already specifies a register-based calling
386 * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
387 * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
388 * special handling for dealing with 4 arguments, unlike i386.
389 * However, x86_64 also have to clobber all caller saved registers, which
390 * unfortunately, are quite a bit (r8 - r11)
391 *
392 * The call instruction itself is marked by placing its start address
393 * and size into the .parainstructions section, so that
394 * apply_paravirt() in arch/i386/kernel/alternative.c can do the
395 * appropriate patching under the control of the backend pv_init_ops
396 * implementation.
397 *
398 * Unfortunately there's no way to get gcc to generate the args setup
399 * for the call, and then allow the call itself to be generated by an
400 * inline asm. Because of this, we must do the complete arg setup and
401 * return value handling from within these macros. This is fairly
402 * cumbersome.
403 *
404 * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
405 * It could be extended to more arguments, but there would be little
406 * to be gained from that. For each number of arguments, there are
407 * the two VCALL and CALL variants for void and non-void functions.
408 *
409 * When there is a return value, the invoker of the macro must specify
410 * the return type. The macro then uses sizeof() on that type to
411 * determine whether its a 32 or 64 bit value, and places the return
412 * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
413 * 64-bit). For x86_64 machines, it just returns at %rax regardless of
414 * the return value size.
415 *
416 * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
417 * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
418 * in low,high order
419 *
420 * Small structures are passed and returned in registers. The macro
421 * calling convention can't directly deal with this, so the wrapper
422 * functions must do this.
423 *
424 * These PVOP_* macros are only defined within this header. This
425 * means that all uses must be wrapped in inline functions. This also
426 * makes sure the incoming and outgoing types are always correct.
427 */
428 #ifdef CONFIG_X86_32
429 #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx
430 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS
431 #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \
432 "=c" (__ecx)
433 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS
434 #define EXTRA_CLOBBERS
435 #define VEXTRA_CLOBBERS
436 #else
437 #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx
438 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax
439 #define PVOP_VCALL_CLOBBERS "=D" (__edi), \
440 "=S" (__esi), "=d" (__edx), \
441 "=c" (__ecx)
442
443 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
444
445 #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11"
446 #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11"
447 #endif
448
449 #define __PVOP_CALL(rettype, op, pre, post, ...) \
450 ({ \
451 rettype __ret; \
452 PVOP_CALL_ARGS; \
453 /* This is 32-bit specific, but is okay in 64-bit */ \
454 /* since this condition will never hold */ \
455 if (sizeof(rettype) > sizeof(unsigned long)) { \
456 asm volatile(pre \
457 paravirt_alt(PARAVIRT_CALL) \
458 post \
459 : PVOP_CALL_CLOBBERS \
460 : paravirt_type(op), \
461 paravirt_clobber(CLBR_ANY), \
462 ##__VA_ARGS__ \
463 : "memory", "cc" EXTRA_CLOBBERS); \
464 __ret = (rettype)((((u64)__edx) << 32) | __eax); \
465 } else { \
466 asm volatile(pre \
467 paravirt_alt(PARAVIRT_CALL) \
468 post \
469 : PVOP_CALL_CLOBBERS \
470 : paravirt_type(op), \
471 paravirt_clobber(CLBR_ANY), \
472 ##__VA_ARGS__ \
473 : "memory", "cc" EXTRA_CLOBBERS); \
474 __ret = (rettype)__eax; \
475 } \
476 __ret; \
477 })
478 #define __PVOP_VCALL(op, pre, post, ...) \
479 ({ \
480 PVOP_VCALL_ARGS; \
481 asm volatile(pre \
482 paravirt_alt(PARAVIRT_CALL) \
483 post \
484 : PVOP_VCALL_CLOBBERS \
485 : paravirt_type(op), \
486 paravirt_clobber(CLBR_ANY), \
487 ##__VA_ARGS__ \
488 : "memory", "cc" VEXTRA_CLOBBERS); \
489 })
490
491 #define PVOP_CALL0(rettype, op) \
492 __PVOP_CALL(rettype, op, "", "")
493 #define PVOP_VCALL0(op) \
494 __PVOP_VCALL(op, "", "")
495
496 #define PVOP_CALL1(rettype, op, arg1) \
497 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)))
498 #define PVOP_VCALL1(op, arg1) \
499 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)))
500
501 #define PVOP_CALL2(rettype, op, arg1, arg2) \
502 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
503 "1" ((unsigned long)(arg2)))
504 #define PVOP_VCALL2(op, arg1, arg2) \
505 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
506 "1" ((unsigned long)(arg2)))
507
508 #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \
509 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
510 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
511 #define PVOP_VCALL3(op, arg1, arg2, arg3) \
512 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
513 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
514
515 /* This is the only difference in x86_64. We can make it much simpler */
516 #ifdef CONFIG_X86_32
517 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
518 __PVOP_CALL(rettype, op, \
519 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
520 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
521 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
522 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
523 __PVOP_VCALL(op, \
524 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
525 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
526 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
527 #else
528 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
529 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
530 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
531 "3"((unsigned long)(arg4)))
532 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
533 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
534 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
535 "3"((unsigned long)(arg4)))
536 #endif
537
538 static inline int paravirt_enabled(void)
539 {
540 return pv_info.paravirt_enabled;
541 }
542
543 static inline void load_sp0(struct tss_struct *tss,
544 struct thread_struct *thread)
545 {
546 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
547 }
548
549 #define ARCH_SETUP pv_init_ops.arch_setup();
550 static inline unsigned long get_wallclock(void)
551 {
552 return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
553 }
554
555 static inline int set_wallclock(unsigned long nowtime)
556 {
557 return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
558 }
559
560 static inline void (*choose_time_init(void))(void)
561 {
562 return pv_time_ops.time_init;
563 }
564
565 /* The paravirtualized CPUID instruction. */
566 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
567 unsigned int *ecx, unsigned int *edx)
568 {
569 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
570 }
571
572 /*
573 * These special macros can be used to get or set a debugging register
574 */
575 static inline unsigned long paravirt_get_debugreg(int reg)
576 {
577 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
578 }
579 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
580 static inline void set_debugreg(unsigned long val, int reg)
581 {
582 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
583 }
584
585 static inline void clts(void)
586 {
587 PVOP_VCALL0(pv_cpu_ops.clts);
588 }
589
590 static inline unsigned long read_cr0(void)
591 {
592 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
593 }
594
595 static inline void write_cr0(unsigned long x)
596 {
597 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
598 }
599
600 static inline unsigned long read_cr2(void)
601 {
602 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
603 }
604
605 static inline void write_cr2(unsigned long x)
606 {
607 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
608 }
609
610 static inline unsigned long read_cr3(void)
611 {
612 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
613 }
614
615 static inline void write_cr3(unsigned long x)
616 {
617 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
618 }
619
620 static inline unsigned long read_cr4(void)
621 {
622 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
623 }
624 static inline unsigned long read_cr4_safe(void)
625 {
626 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
627 }
628
629 static inline void write_cr4(unsigned long x)
630 {
631 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
632 }
633
634 #ifdef CONFIG_X86_64
635 static inline unsigned long read_cr8(void)
636 {
637 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
638 }
639
640 static inline void write_cr8(unsigned long x)
641 {
642 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
643 }
644 #endif
645
646 static inline void raw_safe_halt(void)
647 {
648 PVOP_VCALL0(pv_irq_ops.safe_halt);
649 }
650
651 static inline void halt(void)
652 {
653 PVOP_VCALL0(pv_irq_ops.safe_halt);
654 }
655
656 static inline void wbinvd(void)
657 {
658 PVOP_VCALL0(pv_cpu_ops.wbinvd);
659 }
660
661 #define get_kernel_rpl() (pv_info.kernel_rpl)
662
663 static inline u64 paravirt_read_msr(unsigned msr, int *err)
664 {
665 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
666 }
667 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
668 {
669 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
670 }
671
672 /* These should all do BUG_ON(_err), but our headers are too tangled. */
673 #define rdmsr(msr, val1, val2) \
674 do { \
675 int _err; \
676 u64 _l = paravirt_read_msr(msr, &_err); \
677 val1 = (u32)_l; \
678 val2 = _l >> 32; \
679 } while (0)
680
681 #define wrmsr(msr, val1, val2) \
682 do { \
683 paravirt_write_msr(msr, val1, val2); \
684 } while (0)
685
686 #define rdmsrl(msr, val) \
687 do { \
688 int _err; \
689 val = paravirt_read_msr(msr, &_err); \
690 } while (0)
691
692 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
693 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b)
694
695 /* rdmsr with exception handling */
696 #define rdmsr_safe(msr, a, b) \
697 ({ \
698 int _err; \
699 u64 _l = paravirt_read_msr(msr, &_err); \
700 (*a) = (u32)_l; \
701 (*b) = _l >> 32; \
702 _err; \
703 })
704
705 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
706 {
707 int err;
708
709 *p = paravirt_read_msr(msr, &err);
710 return err;
711 }
712
713 static inline u64 paravirt_read_tsc(void)
714 {
715 return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
716 }
717
718 #define rdtscl(low) \
719 do { \
720 u64 _l = paravirt_read_tsc(); \
721 low = (int)_l; \
722 } while (0)
723
724 #define rdtscll(val) (val = paravirt_read_tsc())
725
726 static inline unsigned long long paravirt_sched_clock(void)
727 {
728 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
729 }
730 #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz())
731
732 static inline unsigned long long paravirt_read_pmc(int counter)
733 {
734 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
735 }
736
737 #define rdpmc(counter, low, high) \
738 do { \
739 u64 _l = paravirt_read_pmc(counter); \
740 low = (u32)_l; \
741 high = _l >> 32; \
742 } while (0)
743
744 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
745 {
746 return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
747 }
748
749 #define rdtscp(low, high, aux) \
750 do { \
751 int __aux; \
752 unsigned long __val = paravirt_rdtscp(&__aux); \
753 (low) = (u32)__val; \
754 (high) = (u32)(__val >> 32); \
755 (aux) = __aux; \
756 } while (0)
757
758 #define rdtscpll(val, aux) \
759 do { \
760 unsigned long __aux; \
761 val = paravirt_rdtscp(&__aux); \
762 (aux) = __aux; \
763 } while (0)
764
765 static inline void load_TR_desc(void)
766 {
767 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
768 }
769 static inline void load_gdt(const struct desc_ptr *dtr)
770 {
771 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
772 }
773 static inline void load_idt(const struct desc_ptr *dtr)
774 {
775 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
776 }
777 static inline void set_ldt(const void *addr, unsigned entries)
778 {
779 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
780 }
781 static inline void store_gdt(struct desc_ptr *dtr)
782 {
783 PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
784 }
785 static inline void store_idt(struct desc_ptr *dtr)
786 {
787 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
788 }
789 static inline unsigned long paravirt_store_tr(void)
790 {
791 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
792 }
793 #define store_tr(tr) ((tr) = paravirt_store_tr())
794 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
795 {
796 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
797 }
798
799 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
800 const void *desc)
801 {
802 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
803 }
804
805 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
806 void *desc, int type)
807 {
808 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
809 }
810
811 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
812 {
813 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
814 }
815 static inline void set_iopl_mask(unsigned mask)
816 {
817 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
818 }
819
820 /* The paravirtualized I/O functions */
821 static inline void slow_down_io(void)
822 {
823 pv_cpu_ops.io_delay();
824 #ifdef REALLY_SLOW_IO
825 pv_cpu_ops.io_delay();
826 pv_cpu_ops.io_delay();
827 pv_cpu_ops.io_delay();
828 #endif
829 }
830
831 #ifdef CONFIG_X86_LOCAL_APIC
832 /*
833 * Basic functions accessing APICs.
834 */
835 static inline void apic_write(unsigned long reg, u32 v)
836 {
837 PVOP_VCALL2(pv_apic_ops.apic_write, reg, v);
838 }
839
840 static inline void apic_write_atomic(unsigned long reg, u32 v)
841 {
842 PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v);
843 }
844
845 static inline u32 apic_read(unsigned long reg)
846 {
847 return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg);
848 }
849
850 static inline void setup_boot_clock(void)
851 {
852 PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
853 }
854
855 static inline void setup_secondary_clock(void)
856 {
857 PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
858 }
859 #endif
860
861 static inline void paravirt_post_allocator_init(void)
862 {
863 if (pv_init_ops.post_allocator_init)
864 (*pv_init_ops.post_allocator_init)();
865 }
866
867 static inline void paravirt_pagetable_setup_start(pgd_t *base)
868 {
869 (*pv_mmu_ops.pagetable_setup_start)(base);
870 }
871
872 static inline void paravirt_pagetable_setup_done(pgd_t *base)
873 {
874 (*pv_mmu_ops.pagetable_setup_done)(base);
875 }
876
877 #ifdef CONFIG_SMP
878 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
879 unsigned long start_esp)
880 {
881 PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
882 phys_apicid, start_eip, start_esp);
883 }
884 #endif
885
886 static inline void paravirt_activate_mm(struct mm_struct *prev,
887 struct mm_struct *next)
888 {
889 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
890 }
891
892 static inline void arch_dup_mmap(struct mm_struct *oldmm,
893 struct mm_struct *mm)
894 {
895 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
896 }
897
898 static inline void arch_exit_mmap(struct mm_struct *mm)
899 {
900 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
901 }
902
903 static inline void __flush_tlb(void)
904 {
905 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
906 }
907 static inline void __flush_tlb_global(void)
908 {
909 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
910 }
911 static inline void __flush_tlb_single(unsigned long addr)
912 {
913 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
914 }
915
916 static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
917 unsigned long va)
918 {
919 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va);
920 }
921
922 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn)
923 {
924 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
925 }
926 static inline void paravirt_release_pte(unsigned pfn)
927 {
928 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
929 }
930
931 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned pfn)
932 {
933 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
934 }
935
936 static inline void paravirt_alloc_pmd_clone(unsigned pfn, unsigned clonepfn,
937 unsigned start, unsigned count)
938 {
939 PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count);
940 }
941 static inline void paravirt_release_pmd(unsigned pfn)
942 {
943 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
944 }
945
946 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned pfn)
947 {
948 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
949 }
950 static inline void paravirt_release_pud(unsigned pfn)
951 {
952 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
953 }
954
955 #ifdef CONFIG_HIGHPTE
956 static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
957 {
958 unsigned long ret;
959 ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
960 return (void *)ret;
961 }
962 #endif
963
964 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
965 pte_t *ptep)
966 {
967 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
968 }
969
970 static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
971 pte_t *ptep)
972 {
973 PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
974 }
975
976 static inline pte_t __pte(pteval_t val)
977 {
978 pteval_t ret;
979
980 if (sizeof(pteval_t) > sizeof(long))
981 ret = PVOP_CALL2(pteval_t,
982 pv_mmu_ops.make_pte,
983 val, (u64)val >> 32);
984 else
985 ret = PVOP_CALL1(pteval_t,
986 pv_mmu_ops.make_pte,
987 val);
988
989 return (pte_t) { .pte = ret };
990 }
991
992 static inline pteval_t pte_val(pte_t pte)
993 {
994 pteval_t ret;
995
996 if (sizeof(pteval_t) > sizeof(long))
997 ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val,
998 pte.pte, (u64)pte.pte >> 32);
999 else
1000 ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val,
1001 pte.pte);
1002
1003 return ret;
1004 }
1005
1006 static inline pgd_t __pgd(pgdval_t val)
1007 {
1008 pgdval_t ret;
1009
1010 if (sizeof(pgdval_t) > sizeof(long))
1011 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd,
1012 val, (u64)val >> 32);
1013 else
1014 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd,
1015 val);
1016
1017 return (pgd_t) { ret };
1018 }
1019
1020 static inline pgdval_t pgd_val(pgd_t pgd)
1021 {
1022 pgdval_t ret;
1023
1024 if (sizeof(pgdval_t) > sizeof(long))
1025 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val,
1026 pgd.pgd, (u64)pgd.pgd >> 32);
1027 else
1028 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val,
1029 pgd.pgd);
1030
1031 return ret;
1032 }
1033
1034 static inline void set_pte(pte_t *ptep, pte_t pte)
1035 {
1036 if (sizeof(pteval_t) > sizeof(long))
1037 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
1038 pte.pte, (u64)pte.pte >> 32);
1039 else
1040 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
1041 pte.pte);
1042 }
1043
1044 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
1045 pte_t *ptep, pte_t pte)
1046 {
1047 if (sizeof(pteval_t) > sizeof(long))
1048 /* 5 arg words */
1049 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
1050 else
1051 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
1052 }
1053
1054 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
1055 {
1056 pmdval_t val = native_pmd_val(pmd);
1057
1058 if (sizeof(pmdval_t) > sizeof(long))
1059 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
1060 else
1061 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
1062 }
1063
1064 #if PAGETABLE_LEVELS >= 3
1065 static inline pmd_t __pmd(pmdval_t val)
1066 {
1067 pmdval_t ret;
1068
1069 if (sizeof(pmdval_t) > sizeof(long))
1070 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd,
1071 val, (u64)val >> 32);
1072 else
1073 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd,
1074 val);
1075
1076 return (pmd_t) { ret };
1077 }
1078
1079 static inline pmdval_t pmd_val(pmd_t pmd)
1080 {
1081 pmdval_t ret;
1082
1083 if (sizeof(pmdval_t) > sizeof(long))
1084 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val,
1085 pmd.pmd, (u64)pmd.pmd >> 32);
1086 else
1087 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val,
1088 pmd.pmd);
1089
1090 return ret;
1091 }
1092
1093 static inline void set_pud(pud_t *pudp, pud_t pud)
1094 {
1095 pudval_t val = native_pud_val(pud);
1096
1097 if (sizeof(pudval_t) > sizeof(long))
1098 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
1099 val, (u64)val >> 32);
1100 else
1101 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
1102 val);
1103 }
1104 #if PAGETABLE_LEVELS == 4
1105 static inline pud_t __pud(pudval_t val)
1106 {
1107 pudval_t ret;
1108
1109 if (sizeof(pudval_t) > sizeof(long))
1110 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud,
1111 val, (u64)val >> 32);
1112 else
1113 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud,
1114 val);
1115
1116 return (pud_t) { ret };
1117 }
1118
1119 static inline pudval_t pud_val(pud_t pud)
1120 {
1121 pudval_t ret;
1122
1123 if (sizeof(pudval_t) > sizeof(long))
1124 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val,
1125 pud.pud, (u64)pud.pud >> 32);
1126 else
1127 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val,
1128 pud.pud);
1129
1130 return ret;
1131 }
1132
1133 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
1134 {
1135 pgdval_t val = native_pgd_val(pgd);
1136
1137 if (sizeof(pgdval_t) > sizeof(long))
1138 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
1139 val, (u64)val >> 32);
1140 else
1141 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
1142 val);
1143 }
1144
1145 static inline void pgd_clear(pgd_t *pgdp)
1146 {
1147 set_pgd(pgdp, __pgd(0));
1148 }
1149
1150 static inline void pud_clear(pud_t *pudp)
1151 {
1152 set_pud(pudp, __pud(0));
1153 }
1154
1155 #endif /* PAGETABLE_LEVELS == 4 */
1156
1157 #endif /* PAGETABLE_LEVELS >= 3 */
1158
1159 #ifdef CONFIG_X86_PAE
1160 /* Special-case pte-setting operations for PAE, which can't update a
1161 64-bit pte atomically */
1162 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1163 {
1164 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
1165 pte.pte, pte.pte >> 32);
1166 }
1167
1168 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1169 pte_t *ptep, pte_t pte)
1170 {
1171 /* 5 arg words */
1172 pv_mmu_ops.set_pte_present(mm, addr, ptep, pte);
1173 }
1174
1175 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1176 pte_t *ptep)
1177 {
1178 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
1179 }
1180
1181 static inline void pmd_clear(pmd_t *pmdp)
1182 {
1183 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
1184 }
1185 #else /* !CONFIG_X86_PAE */
1186 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1187 {
1188 set_pte(ptep, pte);
1189 }
1190
1191 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1192 pte_t *ptep, pte_t pte)
1193 {
1194 set_pte(ptep, pte);
1195 }
1196
1197 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1198 pte_t *ptep)
1199 {
1200 set_pte_at(mm, addr, ptep, __pte(0));
1201 }
1202
1203 static inline void pmd_clear(pmd_t *pmdp)
1204 {
1205 set_pmd(pmdp, __pmd(0));
1206 }
1207 #endif /* CONFIG_X86_PAE */
1208
1209 /* Lazy mode for batching updates / context switch */
1210 enum paravirt_lazy_mode {
1211 PARAVIRT_LAZY_NONE,
1212 PARAVIRT_LAZY_MMU,
1213 PARAVIRT_LAZY_CPU,
1214 };
1215
1216 enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
1217 void paravirt_enter_lazy_cpu(void);
1218 void paravirt_leave_lazy_cpu(void);
1219 void paravirt_enter_lazy_mmu(void);
1220 void paravirt_leave_lazy_mmu(void);
1221 void paravirt_leave_lazy(enum paravirt_lazy_mode mode);
1222
1223 #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE
1224 static inline void arch_enter_lazy_cpu_mode(void)
1225 {
1226 PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter);
1227 }
1228
1229 static inline void arch_leave_lazy_cpu_mode(void)
1230 {
1231 PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
1232 }
1233
1234 static inline void arch_flush_lazy_cpu_mode(void)
1235 {
1236 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
1237 arch_leave_lazy_cpu_mode();
1238 arch_enter_lazy_cpu_mode();
1239 }
1240 }
1241
1242
1243 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1244 static inline void arch_enter_lazy_mmu_mode(void)
1245 {
1246 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
1247 }
1248
1249 static inline void arch_leave_lazy_mmu_mode(void)
1250 {
1251 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
1252 }
1253
1254 static inline void arch_flush_lazy_mmu_mode(void)
1255 {
1256 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
1257 arch_leave_lazy_mmu_mode();
1258 arch_enter_lazy_mmu_mode();
1259 }
1260 }
1261
1262 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
1263 unsigned long phys, pgprot_t flags)
1264 {
1265 pv_mmu_ops.set_fixmap(idx, phys, flags);
1266 }
1267
1268 void _paravirt_nop(void);
1269 #define paravirt_nop ((void *)_paravirt_nop)
1270
1271 /* These all sit in the .parainstructions section to tell us what to patch. */
1272 struct paravirt_patch_site {
1273 u8 *instr; /* original instructions */
1274 u8 instrtype; /* type of this instruction */
1275 u8 len; /* length of original instruction */
1276 u16 clobbers; /* what registers you may clobber */
1277 };
1278
1279 extern struct paravirt_patch_site __parainstructions[],
1280 __parainstructions_end[];
1281
1282 #ifdef CONFIG_X86_32
1283 #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;"
1284 #define PV_RESTORE_REGS "popl %%edx; popl %%ecx"
1285 #define PV_FLAGS_ARG "0"
1286 #define PV_EXTRA_CLOBBERS
1287 #define PV_VEXTRA_CLOBBERS
1288 #else
1289 /* We save some registers, but all of them, that's too much. We clobber all
1290 * caller saved registers but the argument parameter */
1291 #define PV_SAVE_REGS "pushq %%rdi;"
1292 #define PV_RESTORE_REGS "popq %%rdi;"
1293 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx"
1294 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx"
1295 #define PV_FLAGS_ARG "D"
1296 #endif
1297
1298 static inline unsigned long __raw_local_save_flags(void)
1299 {
1300 unsigned long f;
1301
1302 asm volatile(paravirt_alt(PV_SAVE_REGS
1303 PARAVIRT_CALL
1304 PV_RESTORE_REGS)
1305 : "=a"(f)
1306 : paravirt_type(pv_irq_ops.save_fl),
1307 paravirt_clobber(CLBR_EAX)
1308 : "memory", "cc" PV_VEXTRA_CLOBBERS);
1309 return f;
1310 }
1311
1312 static inline void raw_local_irq_restore(unsigned long f)
1313 {
1314 asm volatile(paravirt_alt(PV_SAVE_REGS
1315 PARAVIRT_CALL
1316 PV_RESTORE_REGS)
1317 : "=a"(f)
1318 : PV_FLAGS_ARG(f),
1319 paravirt_type(pv_irq_ops.restore_fl),
1320 paravirt_clobber(CLBR_EAX)
1321 : "memory", "cc" PV_EXTRA_CLOBBERS);
1322 }
1323
1324 static inline void raw_local_irq_disable(void)
1325 {
1326 asm volatile(paravirt_alt(PV_SAVE_REGS
1327 PARAVIRT_CALL
1328 PV_RESTORE_REGS)
1329 :
1330 : paravirt_type(pv_irq_ops.irq_disable),
1331 paravirt_clobber(CLBR_EAX)
1332 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1333 }
1334
1335 static inline void raw_local_irq_enable(void)
1336 {
1337 asm volatile(paravirt_alt(PV_SAVE_REGS
1338 PARAVIRT_CALL
1339 PV_RESTORE_REGS)
1340 :
1341 : paravirt_type(pv_irq_ops.irq_enable),
1342 paravirt_clobber(CLBR_EAX)
1343 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1344 }
1345
1346 static inline unsigned long __raw_local_irq_save(void)
1347 {
1348 unsigned long f;
1349
1350 f = __raw_local_save_flags();
1351 raw_local_irq_disable();
1352 return f;
1353 }
1354
1355 /* Make sure as little as possible of this mess escapes. */
1356 #undef PARAVIRT_CALL
1357 #undef __PVOP_CALL
1358 #undef __PVOP_VCALL
1359 #undef PVOP_VCALL0
1360 #undef PVOP_CALL0
1361 #undef PVOP_VCALL1
1362 #undef PVOP_CALL1
1363 #undef PVOP_VCALL2
1364 #undef PVOP_CALL2
1365 #undef PVOP_VCALL3
1366 #undef PVOP_CALL3
1367 #undef PVOP_VCALL4
1368 #undef PVOP_CALL4
1369
1370 #else /* __ASSEMBLY__ */
1371
1372 #define _PVSITE(ptype, clobbers, ops, word, algn) \
1373 771:; \
1374 ops; \
1375 772:; \
1376 .pushsection .parainstructions,"a"; \
1377 .align algn; \
1378 word 771b; \
1379 .byte ptype; \
1380 .byte 772b-771b; \
1381 .short clobbers; \
1382 .popsection
1383
1384
1385 #ifdef CONFIG_X86_64
1386 #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx
1387 #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax
1388 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
1389 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
1390 #else
1391 #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx
1392 #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
1393 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
1394 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
1395 #endif
1396
1397 #define INTERRUPT_RETURN \
1398 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
1399 jmp *%cs:pv_cpu_ops+PV_CPU_iret)
1400
1401 #define DISABLE_INTERRUPTS(clobbers) \
1402 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
1403 PV_SAVE_REGS; \
1404 call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \
1405 PV_RESTORE_REGS;) \
1406
1407 #define ENABLE_INTERRUPTS(clobbers) \
1408 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
1409 PV_SAVE_REGS; \
1410 call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \
1411 PV_RESTORE_REGS;)
1412
1413 #define ENABLE_INTERRUPTS_SYSCALL_RET \
1414 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\
1415 CLBR_NONE, \
1416 jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret)
1417
1418
1419 #ifdef CONFIG_X86_32
1420 #define GET_CR0_INTO_EAX \
1421 push %ecx; push %edx; \
1422 call *pv_cpu_ops+PV_CPU_read_cr0; \
1423 pop %edx; pop %ecx
1424 #else
1425 #define SWAPGS \
1426 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1427 PV_SAVE_REGS; \
1428 call *pv_cpu_ops+PV_CPU_swapgs; \
1429 PV_RESTORE_REGS \
1430 )
1431
1432 #define GET_CR2_INTO_RCX \
1433 call *pv_mmu_ops+PV_MMU_read_cr2; \
1434 movq %rax, %rcx; \
1435 xorq %rax, %rax;
1436
1437 #endif
1438
1439 #endif /* __ASSEMBLY__ */
1440 #endif /* CONFIG_PARAVIRT */
1441 #endif /* __ASM_PARAVIRT_H */
Linux kernel - Deliverables
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