include/asm-x86/processor.h

   1 #ifndef __ASM_X86_PROCESSOR_H
   2 #define __ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/page.h>
  11 #include <asm/percpu.h>
  12 #include <asm/system.h>
  13
  14 /*
  15  * Default implementation of macro that returns current
  16  * instruction pointer ("program counter").
  17  */
  18 static inline void *current_text_addr(void)
  19 {
  20         void *pc;
  21         asm volatile("mov $1f,%0\n1:":"=r" (pc));
  22         return pc;
  23 }
  24
  25 #ifdef CONFIG_X86_VSMP
  26 #define ARCH_MIN_TASKALIGN      (1 << INTERNODE_CACHE_SHIFT)
  27 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
  28 #else
  29 #define ARCH_MIN_TASKALIGN      16
  30 #define ARCH_MIN_MMSTRUCT_ALIGN 0
  31 #endif
  32
  33 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
  34                                          unsigned int *ecx, unsigned int *edx)
  35 {
  36         /* ecx is often an input as well as an output. */
  37         __asm__("cpuid"
  38                 : "=a" (*eax),
  39                   "=b" (*ebx),
  40                   "=c" (*ecx),
  41                   "=d" (*edx)
  42                 : "0" (*eax), "2" (*ecx));
  43 }
  44
  45 static inline void load_cr3(pgd_t *pgdir)
  46 {
  47         write_cr3(__pa(pgdir));
  48 }
  49
  50 #ifdef CONFIG_X86_32
  51 /* This is the TSS defined by the hardware. */
  52 struct x86_hw_tss {
  53         unsigned short  back_link, __blh;
  54         unsigned long   sp0;
  55         unsigned short  ss0, __ss0h;
  56         unsigned long   sp1;
  57         unsigned short  ss1, __ss1h;    /* ss1 caches MSR_IA32_SYSENTER_CS */
  58         unsigned long   sp2;
  59         unsigned short  ss2, __ss2h;
  60         unsigned long   __cr3;
  61         unsigned long   ip;
  62         unsigned long   flags;
  63         unsigned long   ax, cx, dx, bx;
  64         unsigned long   sp, bp, si, di;
  65         unsigned short  es, __esh;
  66         unsigned short  cs, __csh;
  67         unsigned short  ss, __ssh;
  68         unsigned short  ds, __dsh;
  69         unsigned short  fs, __fsh;
  70         unsigned short  gs, __gsh;
  71         unsigned short  ldt, __ldth;
  72         unsigned short  trace, io_bitmap_base;
  73 } __attribute__((packed));
  74 #else
  75 struct x86_hw_tss {
  76         u32 reserved1;
  77         u64 sp0;
  78         u64 sp1;
  79         u64 sp2;
  80         u64 reserved2;
  81         u64 ist[7];
  82         u32 reserved3;
  83         u32 reserved4;
  84         u16 reserved5;
  85         u16 io_bitmap_base;
  86 } __attribute__((packed)) ____cacheline_aligned;
  87 #endif
  88
  89 /*
  90  * Size of io_bitmap.
  91  */
  92 #define IO_BITMAP_BITS  65536
  93 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
  94 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
  95 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
  96 #define INVALID_IO_BITMAP_OFFSET 0x8000
  97 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
  98
  99 struct tss_struct {
 100         struct x86_hw_tss x86_tss;
 101
 102         /*
 103          * The extra 1 is there because the CPU will access an
 104          * additional byte beyond the end of the IO permission
 105          * bitmap. The extra byte must be all 1 bits, and must
 106          * be within the limit.
 107          */
 108         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 109         /*
 110          * Cache the current maximum and the last task that used the bitmap:
 111          */
 112         unsigned long io_bitmap_max;
 113         struct thread_struct *io_bitmap_owner;
 114         /*
 115          * pads the TSS to be cacheline-aligned (size is 0x100)
 116          */
 117         unsigned long __cacheline_filler[35];
 118         /*
 119          * .. and then another 0x100 bytes for emergency kernel stack
 120          */
 121         unsigned long stack[64];
 122 } __attribute__((packed));
 123
 124 DECLARE_PER_CPU(struct tss_struct, init_tss);
 125
 126 #ifdef CONFIG_X86_32
 127 # include "processor_32.h"
 128 #else
 129 # include "processor_64.h"
 130 #endif
 131
 132 extern void print_cpu_info(struct cpuinfo_x86 *);
 133 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 134 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 135 extern unsigned short num_cache_leaves;
 136
 137 struct thread_struct {
 138 /* cached TLS descriptors. */
 139         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 140         unsigned long   sp0;
 141         unsigned long   sp;
 142 #ifdef CONFIG_X86_32
 143         unsigned long   sysenter_cs;
 144 #else
 145         unsigned long   usersp; /* Copy from PDA */
 146         unsigned short  es, ds, fsindex, gsindex;
 147 #endif
 148         unsigned long   ip;
 149         unsigned long   fs;
 150         unsigned long   gs;
 151 /* Hardware debugging registers */
 152         unsigned long   debugreg0;
 153         unsigned long   debugreg1;
 154         unsigned long   debugreg2;
 155         unsigned long   debugreg3;
 156         unsigned long   debugreg6;
 157         unsigned long   debugreg7;
 158 /* fault info */
 159         unsigned long   cr2, trap_no, error_code;
 160 /* floating point info */
 161         union i387_union        i387 __attribute__((aligned(16)));;
 162 #ifdef CONFIG_X86_32
 163 /* virtual 86 mode info */
 164         struct vm86_struct __user *vm86_info;
 165         unsigned long           screen_bitmap;
 166         unsigned long           v86flags, v86mask, saved_sp0;
 167         unsigned int            saved_fs, saved_gs;
 168 #endif
 169 /* IO permissions */
 170         unsigned long   *io_bitmap_ptr;
 171         unsigned long   iopl;
 172 /* max allowed port in the bitmap, in bytes: */
 173         unsigned io_bitmap_max;
 174 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 175         unsigned long   debugctlmsr;
 176 /* Debug Store - if not 0 points to a DS Save Area configuration;
 177  *               goes into MSR_IA32_DS_AREA */
 178         unsigned long   ds_area_msr;
 179 };
 180
 181 static inline unsigned long native_get_debugreg(int regno)
 182 {
 183         unsigned long val = 0;  /* Damn you, gcc! */
 184
 185         switch (regno) {
 186         case 0:
 187                 asm("mov %%db0, %0" :"=r" (val)); break;
 188         case 1:
 189                 asm("mov %%db1, %0" :"=r" (val)); break;
 190         case 2:
 191                 asm("mov %%db2, %0" :"=r" (val)); break;
 192         case 3:
 193                 asm("mov %%db3, %0" :"=r" (val)); break;
 194         case 6:
 195                 asm("mov %%db6, %0" :"=r" (val)); break;
 196         case 7:
 197                 asm("mov %%db7, %0" :"=r" (val)); break;
 198         default:
 199                 BUG();
 200         }
 201         return val;
 202 }
 203
 204 static inline void native_set_debugreg(int regno, unsigned long value)
 205 {
 206         switch (regno) {
 207         case 0:
 208                 asm("mov %0,%%db0"      : /* no output */ :"r" (value));
 209                 break;
 210         case 1:
 211                 asm("mov %0,%%db1"      : /* no output */ :"r" (value));
 212                 break;
 213         case 2:
 214                 asm("mov %0,%%db2"      : /* no output */ :"r" (value));
 215                 break;
 216         case 3:
 217                 asm("mov %0,%%db3"      : /* no output */ :"r" (value));
 218                 break;
 219         case 6:
 220                 asm("mov %0,%%db6"      : /* no output */ :"r" (value));
 221                 break;
 222         case 7:
 223                 asm("mov %0,%%db7"      : /* no output */ :"r" (value));
 224                 break;
 225         default:
 226                 BUG();
 227         }
 228 }
 229
 230 /*
 231  * Set IOPL bits in EFLAGS from given mask
 232  */
 233 static inline void native_set_iopl_mask(unsigned mask)
 234 {
 235 #ifdef CONFIG_X86_32
 236         unsigned int reg;
 237         __asm__ __volatile__ ("pushfl;"
 238                               "popl %0;"
 239                               "andl %1, %0;"
 240                               "orl %2, %0;"
 241                               "pushl %0;"
 242                               "popfl"
 243                                 : "=&r" (reg)
 244                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 245 #endif
 246 }
 247
 248 static inline void native_load_sp0(struct tss_struct *tss,
 249                                    struct thread_struct *thread)
 250 {
 251         tss->x86_tss.sp0 = thread->sp0;
 252 #ifdef CONFIG_X86_32
 253         /* Only happens when SEP is enabled, no need to test "SEP"arately */
 254         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 255                 tss->x86_tss.ss1 = thread->sysenter_cs;
 256                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 257         }
 258 #endif
 259 }
 260
 261 #ifdef CONFIG_PARAVIRT
 262 #include <asm/paravirt.h>
 263 #else
 264 #define __cpuid native_cpuid
 265 #define paravirt_enabled() 0
 266
 267 /*
 268  * These special macros can be used to get or set a debugging register
 269  */
 270 #define get_debugreg(var, register)                             \
 271         (var) = native_get_debugreg(register)
 272 #define set_debugreg(value, register)                           \
 273         native_set_debugreg(register, value)
 274
 275 static inline void load_sp0(struct tss_struct *tss,
 276                             struct thread_struct *thread)
 277 {
 278         native_load_sp0(tss, thread);
 279 }
 280
 281 #define set_iopl_mask native_set_iopl_mask
 282 #endif /* CONFIG_PARAVIRT */
 283
 284 /*
 285  * Save the cr4 feature set we're using (ie
 286  * Pentium 4MB enable and PPro Global page
 287  * enable), so that any CPU's that boot up
 288  * after us can get the correct flags.
 289  */
 290 extern unsigned long mmu_cr4_features;
 291
 292 static inline void set_in_cr4(unsigned long mask)
 293 {
 294         unsigned cr4;
 295         mmu_cr4_features |= mask;
 296         cr4 = read_cr4();
 297         cr4 |= mask;
 298         write_cr4(cr4);
 299 }
 300
 301 static inline void clear_in_cr4(unsigned long mask)
 302 {
 303         unsigned cr4;
 304         mmu_cr4_features &= ~mask;
 305         cr4 = read_cr4();
 306         cr4 &= ~mask;
 307         write_cr4(cr4);
 308 }
 309
 310 struct microcode_header {
 311         unsigned int hdrver;
 312         unsigned int rev;
 313         unsigned int date;
 314         unsigned int sig;
 315         unsigned int cksum;
 316         unsigned int ldrver;
 317         unsigned int pf;
 318         unsigned int datasize;
 319         unsigned int totalsize;
 320         unsigned int reserved[3];
 321 };
 322
 323 struct microcode {
 324         struct microcode_header hdr;
 325         unsigned int bits[0];
 326 };
 327
 328 typedef struct microcode microcode_t;
 329 typedef struct microcode_header microcode_header_t;
 330
 331 /* microcode format is extended from prescott processors */
 332 struct extended_signature {
 333         unsigned int sig;
 334         unsigned int pf;
 335         unsigned int cksum;
 336 };
 337
 338 struct extended_sigtable {
 339         unsigned int count;
 340         unsigned int cksum;
 341         unsigned int reserved[3];
 342         struct extended_signature sigs[0];
 343 };
 344
 345 /*
 346  * create a kernel thread without removing it from tasklists
 347  */
 348 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 349
 350 /* Free all resources held by a thread. */
 351 extern void release_thread(struct task_struct *);
 352
 353 /* Prepare to copy thread state - unlazy all lazy status */
 354 extern void prepare_to_copy(struct task_struct *tsk);
 355
 356 unsigned long get_wchan(struct task_struct *p);
 357
 358 /*
 359  * Generic CPUID function
 360  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 361  * resulting in stale register contents being returned.
 362  */
 363 static inline void cpuid(unsigned int op,
 364                          unsigned int *eax, unsigned int *ebx,
 365                          unsigned int *ecx, unsigned int *edx)
 366 {
 367         *eax = op;
 368         *ecx = 0;
 369         __cpuid(eax, ebx, ecx, edx);
 370 }
 371
 372 /* Some CPUID calls want 'count' to be placed in ecx */
 373 static inline void cpuid_count(unsigned int op, int count,
 374                                unsigned int *eax, unsigned int *ebx,
 375                                unsigned int *ecx, unsigned int *edx)
 376 {
 377         *eax = op;
 378         *ecx = count;
 379         __cpuid(eax, ebx, ecx, edx);
 380 }
 381
 382 /*
 383  * CPUID functions returning a single datum
 384  */
 385 static inline unsigned int cpuid_eax(unsigned int op)
 386 {
 387         unsigned int eax, ebx, ecx, edx;
 388
 389         cpuid(op, &eax, &ebx, &ecx, &edx);
 390         return eax;
 391 }
 392 static inline unsigned int cpuid_ebx(unsigned int op)
 393 {
 394         unsigned int eax, ebx, ecx, edx;
 395
 396         cpuid(op, &eax, &ebx, &ecx, &edx);
 397         return ebx;
 398 }
 399 static inline unsigned int cpuid_ecx(unsigned int op)
 400 {
 401         unsigned int eax, ebx, ecx, edx;
 402
 403         cpuid(op, &eax, &ebx, &ecx, &edx);
 404         return ecx;
 405 }
 406 static inline unsigned int cpuid_edx(unsigned int op)
 407 {
 408         unsigned int eax, ebx, ecx, edx;
 409
 410         cpuid(op, &eax, &ebx, &ecx, &edx);
 411         return edx;
 412 }
 413
 414 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 415 static inline void rep_nop(void)
 416 {
 417         __asm__ __volatile__("rep;nop": : :"memory");
 418 }
 419
 420 /* Stop speculative execution */
 421 static inline void sync_core(void)
 422 {
 423         int tmp;
 424         asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 425                                           : "ebx", "ecx", "edx", "memory");
 426 }
 427
 428 #define cpu_relax()   rep_nop()
 429
 430 static inline void __monitor(const void *eax, unsigned long ecx,
 431                 unsigned long edx)
 432 {
 433         /* "monitor %eax,%ecx,%edx;" */
 434         asm volatile(
 435                 ".byte 0x0f,0x01,0xc8;"
 436                 : :"a" (eax), "c" (ecx), "d"(edx));
 437 }
 438
 439 static inline void __mwait(unsigned long eax, unsigned long ecx)
 440 {
 441         /* "mwait %eax,%ecx;" */
 442         asm volatile(
 443                 ".byte 0x0f,0x01,0xc9;"
 444                 : :"a" (eax), "c" (ecx));
 445 }
 446
 447 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 448 {
 449         /* "mwait %eax,%ecx;" */
 450         asm volatile(
 451                 "sti; .byte 0x0f,0x01,0xc9;"
 452                 : :"a" (eax), "c" (ecx));
 453 }
 454
 455 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 456
 457 extern int force_mwait;
 458
 459 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 460
 461 extern unsigned long boot_option_idle_override;
 462
 463 /* Boot loader type from the setup header */
 464 extern int bootloader_type;
 465 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 466
 467 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 468 #define ARCH_HAS_PREFETCHW
 469 #define ARCH_HAS_SPINLOCK_PREFETCH
 470
 471 #define spin_lock_prefetch(x)   prefetchw(x)
 472 /* This decides where the kernel will search for a free chunk of vm
 473  * space during mmap's.
 474  */
 475 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 476
 477 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
 478
 479 #endif