1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/percpu.h>
12 #include <asm/system.h>
13 #include <asm/percpu.h>
14 #include <linux/cpumask.h>
15 #include <linux/cache.h>
18 * Default implementation of macro that returns current
19 * instruction pointer ("program counter").
21 static inline void *current_text_addr(void)
24 asm volatile("mov $1f,%0\n1:":"=r" (pc
));
28 #ifdef CONFIG_X86_VSMP
29 #define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
30 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
32 #define ARCH_MIN_TASKALIGN 16
33 #define ARCH_MIN_MMSTRUCT_ALIGN 0
37 * CPU type and hardware bug flags. Kept separately for each CPU.
38 * Members of this structure are referenced in head.S, so think twice
39 * before touching them. [mj]
43 __u8 x86
; /* CPU family */
44 __u8 x86_vendor
; /* CPU vendor */
48 char wp_works_ok
; /* It doesn't on 386's */
49 char hlt_works_ok
; /* Problems on some 486Dx4's and old 386's */
57 /* number of 4K pages in DTLB/ITLB combined(in pages)*/
59 __u8 x86_virt_bits
, x86_phys_bits
;
60 /* cpuid returned core id bits */
62 /* Max extended CPUID function supported */
63 __u32 extended_cpuid_level
;
65 int cpuid_level
; /* Maximum supported CPUID level, -1=no CPUID */
66 __u32 x86_capability
[NCAPINTS
];
67 char x86_vendor_id
[16];
68 char x86_model_id
[64];
69 int x86_cache_size
; /* in KB - valid for CPUS which support this
71 int x86_cache_alignment
; /* In bytes */
73 unsigned long loops_per_jiffy
;
75 cpumask_t llc_shared_map
; /* cpus sharing the last level cache */
77 unsigned char x86_max_cores
; /* cpuid returned max cores value */
79 unsigned short x86_clflush_size
;
81 unsigned char booted_cores
; /* number of cores as seen by OS */
82 __u8 phys_proc_id
; /* Physical processor id. */
83 __u8 cpu_core_id
; /* Core id */
84 __u8 cpu_index
; /* index into per_cpu list */
86 } __attribute__((__aligned__(SMP_CACHE_BYTES
)));
88 #define X86_VENDOR_INTEL 0
89 #define X86_VENDOR_CYRIX 1
90 #define X86_VENDOR_AMD 2
91 #define X86_VENDOR_UMC 3
92 #define X86_VENDOR_NEXGEN 4
93 #define X86_VENDOR_CENTAUR 5
94 #define X86_VENDOR_TRANSMETA 7
95 #define X86_VENDOR_NSC 8
96 #define X86_VENDOR_NUM 9
97 #define X86_VENDOR_UNKNOWN 0xff
100 * capabilities of CPUs
102 extern struct cpuinfo_x86 boot_cpu_data
;
103 extern struct cpuinfo_x86 new_cpu_data
;
104 extern struct tss_struct doublefault_tss
;
107 DECLARE_PER_CPU(struct cpuinfo_x86
, cpu_info
);
108 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
109 #define current_cpu_data cpu_data(smp_processor_id())
111 #define cpu_data(cpu) boot_cpu_data
112 #define current_cpu_data boot_cpu_data
115 void cpu_detect(struct cpuinfo_x86
*c
);
117 extern void identify_cpu(struct cpuinfo_x86
*);
118 extern void identify_boot_cpu(void);
119 extern void identify_secondary_cpu(struct cpuinfo_x86
*);
120 extern void print_cpu_info(struct cpuinfo_x86
*);
121 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
122 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
123 extern unsigned short num_cache_leaves
;
125 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
126 extern void detect_ht(struct cpuinfo_x86
*c
);
128 static inline void detect_ht(struct cpuinfo_x86
*c
) {}
131 static inline void native_cpuid(unsigned int *eax
, unsigned int *ebx
,
132 unsigned int *ecx
, unsigned int *edx
)
134 /* ecx is often an input as well as an output. */
140 : "0" (*eax
), "2" (*ecx
));
143 static inline void load_cr3(pgd_t
*pgdir
)
145 write_cr3(__pa(pgdir
));
149 /* This is the TSS defined by the hardware. */
151 unsigned short back_link
, __blh
;
153 unsigned short ss0
, __ss0h
;
155 unsigned short ss1
, __ss1h
; /* ss1 caches MSR_IA32_SYSENTER_CS */
157 unsigned short ss2
, __ss2h
;
161 unsigned long ax
, cx
, dx
, bx
;
162 unsigned long sp
, bp
, si
, di
;
163 unsigned short es
, __esh
;
164 unsigned short cs
, __csh
;
165 unsigned short ss
, __ssh
;
166 unsigned short ds
, __dsh
;
167 unsigned short fs
, __fsh
;
168 unsigned short gs
, __gsh
;
169 unsigned short ldt
, __ldth
;
170 unsigned short trace
, io_bitmap_base
;
171 } __attribute__((packed
));
184 } __attribute__((packed
)) ____cacheline_aligned
;
190 #define IO_BITMAP_BITS 65536
191 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
192 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
193 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
194 #define INVALID_IO_BITMAP_OFFSET 0x8000
195 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
198 struct x86_hw_tss x86_tss
;
201 * The extra 1 is there because the CPU will access an
202 * additional byte beyond the end of the IO permission
203 * bitmap. The extra byte must be all 1 bits, and must
204 * be within the limit.
206 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
208 * Cache the current maximum and the last task that used the bitmap:
210 unsigned long io_bitmap_max
;
211 struct thread_struct
*io_bitmap_owner
;
213 * pads the TSS to be cacheline-aligned (size is 0x100)
215 unsigned long __cacheline_filler
[35];
217 * .. and then another 0x100 bytes for emergency kernel stack
219 unsigned long stack
[64];
220 } __attribute__((packed
));
222 DECLARE_PER_CPU(struct tss_struct
, init_tss
);
224 /* Save the original ist values for checking stack pointers during debugging */
226 unsigned long ist
[7];
230 # include "processor_32.h"
232 # include "processor_64.h"
235 extern void print_cpu_info(struct cpuinfo_x86
*);
236 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
237 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
238 extern unsigned short num_cache_leaves
;
240 struct thread_struct
{
241 /* cached TLS descriptors. */
242 struct desc_struct tls_array
[GDT_ENTRY_TLS_ENTRIES
];
246 unsigned long sysenter_cs
;
248 unsigned long usersp
; /* Copy from PDA */
249 unsigned short es
, ds
, fsindex
, gsindex
;
254 /* Hardware debugging registers */
255 unsigned long debugreg0
;
256 unsigned long debugreg1
;
257 unsigned long debugreg2
;
258 unsigned long debugreg3
;
259 unsigned long debugreg6
;
260 unsigned long debugreg7
;
262 unsigned long cr2
, trap_no
, error_code
;
263 /* floating point info */
264 union i387_union i387
__attribute__((aligned(16)));;
266 /* virtual 86 mode info */
267 struct vm86_struct __user
*vm86_info
;
268 unsigned long screen_bitmap
;
269 unsigned long v86flags
, v86mask
, saved_sp0
;
270 unsigned int saved_fs
, saved_gs
;
273 unsigned long *io_bitmap_ptr
;
275 /* max allowed port in the bitmap, in bytes: */
276 unsigned io_bitmap_max
;
277 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
278 unsigned long debugctlmsr
;
279 /* Debug Store - if not 0 points to a DS Save Area configuration;
280 * goes into MSR_IA32_DS_AREA */
281 unsigned long ds_area_msr
;
284 static inline unsigned long native_get_debugreg(int regno
)
286 unsigned long val
= 0; /* Damn you, gcc! */
290 asm("mov %%db0, %0" :"=r" (val
)); break;
292 asm("mov %%db1, %0" :"=r" (val
)); break;
294 asm("mov %%db2, %0" :"=r" (val
)); break;
296 asm("mov %%db3, %0" :"=r" (val
)); break;
298 asm("mov %%db6, %0" :"=r" (val
)); break;
300 asm("mov %%db7, %0" :"=r" (val
)); break;
307 static inline void native_set_debugreg(int regno
, unsigned long value
)
311 asm("mov %0,%%db0" : /* no output */ :"r" (value
));
314 asm("mov %0,%%db1" : /* no output */ :"r" (value
));
317 asm("mov %0,%%db2" : /* no output */ :"r" (value
));
320 asm("mov %0,%%db3" : /* no output */ :"r" (value
));
323 asm("mov %0,%%db6" : /* no output */ :"r" (value
));
326 asm("mov %0,%%db7" : /* no output */ :"r" (value
));
334 * Set IOPL bits in EFLAGS from given mask
336 static inline void native_set_iopl_mask(unsigned mask
)
340 __asm__
__volatile__ ("pushfl;"
347 : "i" (~X86_EFLAGS_IOPL
), "r" (mask
));
351 static inline void native_load_sp0(struct tss_struct
*tss
,
352 struct thread_struct
*thread
)
354 tss
->x86_tss
.sp0
= thread
->sp0
;
356 /* Only happens when SEP is enabled, no need to test "SEP"arately */
357 if (unlikely(tss
->x86_tss
.ss1
!= thread
->sysenter_cs
)) {
358 tss
->x86_tss
.ss1
= thread
->sysenter_cs
;
359 wrmsr(MSR_IA32_SYSENTER_CS
, thread
->sysenter_cs
, 0);
364 #ifdef CONFIG_PARAVIRT
365 #include <asm/paravirt.h>
367 #define __cpuid native_cpuid
368 #define paravirt_enabled() 0
371 * These special macros can be used to get or set a debugging register
373 #define get_debugreg(var, register) \
374 (var) = native_get_debugreg(register)
375 #define set_debugreg(value, register) \
376 native_set_debugreg(register, value)
378 static inline void load_sp0(struct tss_struct
*tss
,
379 struct thread_struct
*thread
)
381 native_load_sp0(tss
, thread
);
384 #define set_iopl_mask native_set_iopl_mask
385 #endif /* CONFIG_PARAVIRT */
388 * Save the cr4 feature set we're using (ie
389 * Pentium 4MB enable and PPro Global page
390 * enable), so that any CPU's that boot up
391 * after us can get the correct flags.
393 extern unsigned long mmu_cr4_features
;
395 static inline void set_in_cr4(unsigned long mask
)
398 mmu_cr4_features
|= mask
;
404 static inline void clear_in_cr4(unsigned long mask
)
407 mmu_cr4_features
&= ~mask
;
413 struct microcode_header
{
421 unsigned int datasize
;
422 unsigned int totalsize
;
423 unsigned int reserved
[3];
427 struct microcode_header hdr
;
428 unsigned int bits
[0];
431 typedef struct microcode microcode_t
;
432 typedef struct microcode_header microcode_header_t
;
434 /* microcode format is extended from prescott processors */
435 struct extended_signature
{
441 struct extended_sigtable
{
444 unsigned int reserved
[3];
445 struct extended_signature sigs
[0];
454 * create a kernel thread without removing it from tasklists
456 extern int kernel_thread(int (*fn
)(void *), void *arg
, unsigned long flags
);
458 /* Free all resources held by a thread. */
459 extern void release_thread(struct task_struct
*);
461 /* Prepare to copy thread state - unlazy all lazy status */
462 extern void prepare_to_copy(struct task_struct
*tsk
);
464 unsigned long get_wchan(struct task_struct
*p
);
467 * Generic CPUID function
468 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
469 * resulting in stale register contents being returned.
471 static inline void cpuid(unsigned int op
,
472 unsigned int *eax
, unsigned int *ebx
,
473 unsigned int *ecx
, unsigned int *edx
)
477 __cpuid(eax
, ebx
, ecx
, edx
);
480 /* Some CPUID calls want 'count' to be placed in ecx */
481 static inline void cpuid_count(unsigned int op
, int count
,
482 unsigned int *eax
, unsigned int *ebx
,
483 unsigned int *ecx
, unsigned int *edx
)
487 __cpuid(eax
, ebx
, ecx
, edx
);
491 * CPUID functions returning a single datum
493 static inline unsigned int cpuid_eax(unsigned int op
)
495 unsigned int eax
, ebx
, ecx
, edx
;
497 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
500 static inline unsigned int cpuid_ebx(unsigned int op
)
502 unsigned int eax
, ebx
, ecx
, edx
;
504 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
507 static inline unsigned int cpuid_ecx(unsigned int op
)
509 unsigned int eax
, ebx
, ecx
, edx
;
511 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
514 static inline unsigned int cpuid_edx(unsigned int op
)
516 unsigned int eax
, ebx
, ecx
, edx
;
518 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
522 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
523 static inline void rep_nop(void)
525 __asm__
__volatile__("rep;nop": : :"memory");
528 /* Stop speculative execution */
529 static inline void sync_core(void)
532 asm volatile("cpuid" : "=a" (tmp
) : "0" (1)
533 : "ebx", "ecx", "edx", "memory");
536 #define cpu_relax() rep_nop()
538 static inline void __monitor(const void *eax
, unsigned long ecx
,
541 /* "monitor %eax,%ecx,%edx;" */
543 ".byte 0x0f,0x01,0xc8;"
544 : :"a" (eax
), "c" (ecx
), "d"(edx
));
547 static inline void __mwait(unsigned long eax
, unsigned long ecx
)
549 /* "mwait %eax,%ecx;" */
551 ".byte 0x0f,0x01,0xc9;"
552 : :"a" (eax
), "c" (ecx
));
555 static inline void __sti_mwait(unsigned long eax
, unsigned long ecx
)
557 /* "mwait %eax,%ecx;" */
559 "sti; .byte 0x0f,0x01,0xc9;"
560 : :"a" (eax
), "c" (ecx
));
563 extern void mwait_idle_with_hints(unsigned long eax
, unsigned long ecx
);
565 extern int force_mwait
;
567 extern void select_idle_routine(const struct cpuinfo_x86
*c
);
569 extern unsigned long boot_option_idle_override
;
571 extern void enable_sep_cpu(void);
572 extern int sysenter_setup(void);
574 /* Defined in head.S */
575 extern struct desc_ptr early_gdt_descr
;
577 extern void cpu_set_gdt(int);
578 extern void switch_to_new_gdt(void);
579 extern void cpu_init(void);
580 extern void init_gdt(int cpu
);
582 /* from system description table in BIOS. Mostly for MCA use, but
583 * others may find it useful. */
584 extern unsigned int machine_id
;
585 extern unsigned int machine_submodel_id
;
586 extern unsigned int BIOS_revision
;
587 extern unsigned int mca_pentium_flag
;
589 /* Boot loader type from the setup header */
590 extern int bootloader_type
;
592 extern char ignore_fpu_irq
;
593 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
595 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
596 #define ARCH_HAS_PREFETCHW
597 #define ARCH_HAS_SPINLOCK_PREFETCH
599 #define spin_lock_prefetch(x) prefetchw(x)
600 /* This decides where the kernel will search for a free chunk of vm
601 * space during mmap's.
603 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
605 #define KSTK_EIP(task) (task_pt_regs(task)->ip)