include/asm-x86/processor.h

   1 #ifndef ASM_X86__PROCESSOR_H
   2 #define ASM_X86__PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23
  24 #include <linux/personality.h>
  25 #include <linux/cpumask.h>
  26 #include <linux/cache.h>
  27 #include <linux/threads.h>
  28 #include <linux/init.h>
  29
  30 /*
  31  * Default implementation of macro that returns current
  32  * instruction pointer ("program counter").
  33  */
  34 static inline void *current_text_addr(void)
  35 {
  36         void *pc;
  37
  38         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  39
  40         return pc;
  41 }
  42
  43 #ifdef CONFIG_X86_VSMP
  44 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  45 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  46 #else
  47 # define ARCH_MIN_TASKALIGN             16
  48 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  49 #endif
  50
  51 /*
  52  *  CPU type and hardware bug flags. Kept separately for each CPU.
  53  *  Members of this structure are referenced in head.S, so think twice
  54  *  before touching them. [mj]
  55  */
  56
  57 struct cpuinfo_x86 {
  58         __u8                    x86;            /* CPU family */
  59         __u8                    x86_vendor;     /* CPU vendor */
  60         __u8                    x86_model;
  61         __u8                    x86_mask;
  62 #ifdef CONFIG_X86_32
  63         char                    wp_works_ok;    /* It doesn't on 386's */
  64
  65         /* Problems on some 486Dx4's and old 386's: */
  66         char                    hlt_works_ok;
  67         char                    hard_math;
  68         char                    rfu;
  69         char                    fdiv_bug;
  70         char                    f00f_bug;
  71         char                    coma_bug;
  72         char                    pad0;
  73 #else
  74         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  75         int                      x86_tlbsize;
  76         __u8                    x86_virt_bits;
  77         __u8                    x86_phys_bits;
  78         /* CPUID returned core id bits: */
  79         __u8                    x86_coreid_bits;
  80 #endif
  81         /* Max extended CPUID function supported: */
  82         __u32                   extended_cpuid_level;
  83         /* Maximum supported CPUID level, -1=no CPUID: */
  84         int                     cpuid_level;
  85         __u32                   x86_capability[NCAPINTS];
  86         char                    x86_vendor_id[16];
  87         char                    x86_model_id[64];
  88         /* in KB - valid for CPUS which support this call: */
  89         int                     x86_cache_size;
  90         int                     x86_cache_alignment;    /* In bytes */
  91         int                     x86_power;
  92         unsigned long           loops_per_jiffy;
  93 #ifdef CONFIG_SMP
  94         /* cpus sharing the last level cache: */
  95         cpumask_t               llc_shared_map;
  96 #endif
  97         /* cpuid returned max cores value: */
  98         u16                      x86_max_cores;
  99         u16                     apicid;
 100         u16                     initial_apicid;
 101         u16                     x86_clflush_size;
 102 #ifdef CONFIG_SMP
 103         /* number of cores as seen by the OS: */
 104         u16                     booted_cores;
 105         /* Physical processor id: */
 106         u16                     phys_proc_id;
 107         /* Core id: */
 108         u16                     cpu_core_id;
 109         /* Index into per_cpu list: */
 110         u16                     cpu_index;
 111 #endif
 112 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 113
 114 #define X86_VENDOR_INTEL        0
 115 #define X86_VENDOR_CYRIX        1
 116 #define X86_VENDOR_AMD          2
 117 #define X86_VENDOR_UMC          3
 118 #define X86_VENDOR_CENTAUR      5
 119 #define X86_VENDOR_TRANSMETA    7
 120 #define X86_VENDOR_NSC          8
 121 #define X86_VENDOR_NUM          9
 122
 123 #define X86_VENDOR_UNKNOWN      0xff
 124
 125 /*
 126  * capabilities of CPUs
 127  */
 128 extern struct cpuinfo_x86       boot_cpu_data;
 129 extern struct cpuinfo_x86       new_cpu_data;
 130
 131 extern struct tss_struct        doublefault_tss;
 132 extern __u32                    cleared_cpu_caps[NCAPINTS];
 133
 134 #ifdef CONFIG_SMP
 135 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 136 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 137 #define current_cpu_data        __get_cpu_var(cpu_info)
 138 #else
 139 #define cpu_data(cpu)           boot_cpu_data
 140 #define current_cpu_data        boot_cpu_data
 141 #endif
 142
 143 extern const struct seq_operations cpuinfo_op;
 144
 145 static inline int hlt_works(int cpu)
 146 {
 147 #ifdef CONFIG_X86_32
 148         return cpu_data(cpu).hlt_works_ok;
 149 #else
 150         return 1;
 151 #endif
 152 }
 153
 154 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 155
 156 extern void cpu_detect(struct cpuinfo_x86 *c);
 157
 158 extern struct pt_regs *idle_regs(struct pt_regs *);
 159
 160 extern void early_cpu_init(void);
 161 extern void identify_boot_cpu(void);
 162 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 163 extern void print_cpu_info(struct cpuinfo_x86 *);
 164 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 165 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 166 extern unsigned short num_cache_leaves;
 167
 168 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 169 extern void detect_ht(struct cpuinfo_x86 *c);
 170
 171 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 172                                 unsigned int *ecx, unsigned int *edx)
 173 {
 174         /* ecx is often an input as well as an output. */
 175         asm("cpuid"
 176             : "=a" (*eax),
 177               "=b" (*ebx),
 178               "=c" (*ecx),
 179               "=d" (*edx)
 180             : "0" (*eax), "2" (*ecx));
 181 }
 182
 183 static inline void load_cr3(pgd_t *pgdir)
 184 {
 185         write_cr3(__pa(pgdir));
 186 }
 187
 188 #ifdef CONFIG_X86_32
 189 /* This is the TSS defined by the hardware. */
 190 struct x86_hw_tss {
 191         unsigned short          back_link, __blh;
 192         unsigned long           sp0;
 193         unsigned short          ss0, __ss0h;
 194         unsigned long           sp1;
 195         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 196         unsigned short          ss1, __ss1h;
 197         unsigned long           sp2;
 198         unsigned short          ss2, __ss2h;
 199         unsigned long           __cr3;
 200         unsigned long           ip;
 201         unsigned long           flags;
 202         unsigned long           ax;
 203         unsigned long           cx;
 204         unsigned long           dx;
 205         unsigned long           bx;
 206         unsigned long           sp;
 207         unsigned long           bp;
 208         unsigned long           si;
 209         unsigned long           di;
 210         unsigned short          es, __esh;
 211         unsigned short          cs, __csh;
 212         unsigned short          ss, __ssh;
 213         unsigned short          ds, __dsh;
 214         unsigned short          fs, __fsh;
 215         unsigned short          gs, __gsh;
 216         unsigned short          ldt, __ldth;
 217         unsigned short          trace;
 218         unsigned short          io_bitmap_base;
 219
 220 } __attribute__((packed));
 221 #else
 222 struct x86_hw_tss {
 223         u32                     reserved1;
 224         u64                     sp0;
 225         u64                     sp1;
 226         u64                     sp2;
 227         u64                     reserved2;
 228         u64                     ist[7];
 229         u32                     reserved3;
 230         u32                     reserved4;
 231         u16                     reserved5;
 232         u16                     io_bitmap_base;
 233
 234 } __attribute__((packed)) ____cacheline_aligned;
 235 #endif
 236
 237 /*
 238  * IO-bitmap sizes:
 239  */
 240 #define IO_BITMAP_BITS                  65536
 241 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 242 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 243 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 244 #define INVALID_IO_BITMAP_OFFSET        0x8000
 245 #define INVALID_IO_BITMAP_OFFSET_LAZY   0x9000
 246
 247 struct tss_struct {
 248         /*
 249          * The hardware state:
 250          */
 251         struct x86_hw_tss       x86_tss;
 252
 253         /*
 254          * The extra 1 is there because the CPU will access an
 255          * additional byte beyond the end of the IO permission
 256          * bitmap. The extra byte must be all 1 bits, and must
 257          * be within the limit.
 258          */
 259         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 260         /*
 261          * Cache the current maximum and the last task that used the bitmap:
 262          */
 263         unsigned long           io_bitmap_max;
 264         struct thread_struct    *io_bitmap_owner;
 265
 266         /*
 267          * .. and then another 0x100 bytes for the emergency kernel stack:
 268          */
 269         unsigned long           stack[64];
 270
 271 } ____cacheline_aligned;
 272
 273 DECLARE_PER_CPU(struct tss_struct, init_tss);
 274
 275 /*
 276  * Save the original ist values for checking stack pointers during debugging
 277  */
 278 struct orig_ist {
 279         unsigned long           ist[7];
 280 };
 281
 282 #define MXCSR_DEFAULT           0x1f80
 283
 284 struct i387_fsave_struct {
 285         u32                     cwd;    /* FPU Control Word             */
 286         u32                     swd;    /* FPU Status Word              */
 287         u32                     twd;    /* FPU Tag Word                 */
 288         u32                     fip;    /* FPU IP Offset                */
 289         u32                     fcs;    /* FPU IP Selector              */
 290         u32                     foo;    /* FPU Operand Pointer Offset   */
 291         u32                     fos;    /* FPU Operand Pointer Selector */
 292
 293         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 294         u32                     st_space[20];
 295
 296         /* Software status information [not touched by FSAVE ]:         */
 297         u32                     status;
 298 };
 299
 300 struct i387_fxsave_struct {
 301         u16                     cwd; /* Control Word                    */
 302         u16                     swd; /* Status Word                     */
 303         u16                     twd; /* Tag Word                        */
 304         u16                     fop; /* Last Instruction Opcode         */
 305         union {
 306                 struct {
 307                         u64     rip; /* Instruction Pointer             */
 308                         u64     rdp; /* Data Pointer                    */
 309                 };
 310                 struct {
 311                         u32     fip; /* FPU IP Offset                   */
 312                         u32     fcs; /* FPU IP Selector                 */
 313                         u32     foo; /* FPU Operand Offset              */
 314                         u32     fos; /* FPU Operand Selector            */
 315                 };
 316         };
 317         u32                     mxcsr;          /* MXCSR Register State */
 318         u32                     mxcsr_mask;     /* MXCSR Mask           */
 319
 320         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 321         u32                     st_space[32];
 322
 323         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 324         u32                     xmm_space[64];
 325
 326         u32                     padding[12];
 327
 328         union {
 329                 u32             padding1[12];
 330                 u32             sw_reserved[12];
 331         };
 332
 333 } __attribute__((aligned(16)));
 334
 335 struct i387_soft_struct {
 336         u32                     cwd;
 337         u32                     swd;
 338         u32                     twd;
 339         u32                     fip;
 340         u32                     fcs;
 341         u32                     foo;
 342         u32                     fos;
 343         /* 8*10 bytes for each FP-reg = 80 bytes: */
 344         u32                     st_space[20];
 345         u8                      ftop;
 346         u8                      changed;
 347         u8                      lookahead;
 348         u8                      no_update;
 349         u8                      rm;
 350         u8                      alimit;
 351         struct info             *info;
 352         u32                     entry_eip;
 353 };
 354
 355 struct xsave_hdr_struct {
 356         u64 xstate_bv;
 357         u64 reserved1[2];
 358         u64 reserved2[5];
 359 } __attribute__((packed));
 360
 361 struct xsave_struct {
 362         struct i387_fxsave_struct i387;
 363         struct xsave_hdr_struct xsave_hdr;
 364         /* new processor state extensions will go here */
 365 } __attribute__ ((packed, aligned (64)));
 366
 367 union thread_xstate {
 368         struct i387_fsave_struct        fsave;
 369         struct i387_fxsave_struct       fxsave;
 370         struct i387_soft_struct         soft;
 371         struct xsave_struct             xsave;
 372 };
 373
 374 #ifdef CONFIG_X86_64
 375 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 376 #endif
 377
 378 extern void print_cpu_info(struct cpuinfo_x86 *);
 379 extern unsigned int xstate_size;
 380 extern void free_thread_xstate(struct task_struct *);
 381 extern struct kmem_cache *task_xstate_cachep;
 382 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 383 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 384 extern unsigned short num_cache_leaves;
 385
 386 struct thread_struct {
 387         /* Cached TLS descriptors: */
 388         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 389         unsigned long           sp0;
 390         unsigned long           sp;
 391 #ifdef CONFIG_X86_32
 392         unsigned long           sysenter_cs;
 393 #else
 394         unsigned long           usersp; /* Copy from PDA */
 395         unsigned short          es;
 396         unsigned short          ds;
 397         unsigned short          fsindex;
 398         unsigned short          gsindex;
 399 #endif
 400         unsigned long           ip;
 401         unsigned long           fs;
 402         unsigned long           gs;
 403         /* Hardware debugging registers: */
 404         unsigned long           debugreg0;
 405         unsigned long           debugreg1;
 406         unsigned long           debugreg2;
 407         unsigned long           debugreg3;
 408         unsigned long           debugreg6;
 409         unsigned long           debugreg7;
 410         /* Fault info: */
 411         unsigned long           cr2;
 412         unsigned long           trap_no;
 413         unsigned long           error_code;
 414         /* floating point and extended processor state */
 415         union thread_xstate     *xstate;
 416 #ifdef CONFIG_X86_32
 417         /* Virtual 86 mode info */
 418         struct vm86_struct __user *vm86_info;
 419         unsigned long           screen_bitmap;
 420         unsigned long           v86flags;
 421         unsigned long           v86mask;
 422         unsigned long           saved_sp0;
 423         unsigned int            saved_fs;
 424         unsigned int            saved_gs;
 425 #endif
 426         /* IO permissions: */
 427         unsigned long           *io_bitmap_ptr;
 428         unsigned long           iopl;
 429         /* Max allowed port in the bitmap, in bytes: */
 430         unsigned                io_bitmap_max;
 431 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 432         unsigned long   debugctlmsr;
 433 /* Debug Store - if not 0 points to a DS Save Area configuration;
 434  *               goes into MSR_IA32_DS_AREA */
 435         unsigned long   ds_area_msr;
 436 };
 437
 438 static inline unsigned long native_get_debugreg(int regno)
 439 {
 440         unsigned long val = 0;  /* Damn you, gcc! */
 441
 442         switch (regno) {
 443         case 0:
 444                 asm("mov %%db0, %0" :"=r" (val));
 445                 break;
 446         case 1:
 447                 asm("mov %%db1, %0" :"=r" (val));
 448                 break;
 449         case 2:
 450                 asm("mov %%db2, %0" :"=r" (val));
 451                 break;
 452         case 3:
 453                 asm("mov %%db3, %0" :"=r" (val));
 454                 break;
 455         case 6:
 456                 asm("mov %%db6, %0" :"=r" (val));
 457                 break;
 458         case 7:
 459                 asm("mov %%db7, %0" :"=r" (val));
 460                 break;
 461         default:
 462                 BUG();
 463         }
 464         return val;
 465 }
 466
 467 static inline void native_set_debugreg(int regno, unsigned long value)
 468 {
 469         switch (regno) {
 470         case 0:
 471                 asm("mov %0, %%db0"     ::"r" (value));
 472                 break;
 473         case 1:
 474                 asm("mov %0, %%db1"     ::"r" (value));
 475                 break;
 476         case 2:
 477                 asm("mov %0, %%db2"     ::"r" (value));
 478                 break;
 479         case 3:
 480                 asm("mov %0, %%db3"     ::"r" (value));
 481                 break;
 482         case 6:
 483                 asm("mov %0, %%db6"     ::"r" (value));
 484                 break;
 485         case 7:
 486                 asm("mov %0, %%db7"     ::"r" (value));
 487                 break;
 488         default:
 489                 BUG();
 490         }
 491 }
 492
 493 /*
 494  * Set IOPL bits in EFLAGS from given mask
 495  */
 496 static inline void native_set_iopl_mask(unsigned mask)
 497 {
 498 #ifdef CONFIG_X86_32
 499         unsigned int reg;
 500
 501         asm volatile ("pushfl;"
 502                       "popl %0;"
 503                       "andl %1, %0;"
 504                       "orl %2, %0;"
 505                       "pushl %0;"
 506                       "popfl"
 507                       : "=&r" (reg)
 508                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 509 #endif
 510 }
 511
 512 static inline void
 513 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 514 {
 515         tss->x86_tss.sp0 = thread->sp0;
 516 #ifdef CONFIG_X86_32
 517         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 518         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 519                 tss->x86_tss.ss1 = thread->sysenter_cs;
 520                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 521         }
 522 #endif
 523 }
 524
 525 static inline void native_swapgs(void)
 526 {
 527 #ifdef CONFIG_X86_64
 528         asm volatile("swapgs" ::: "memory");
 529 #endif
 530 }
 531
 532 #ifdef CONFIG_PARAVIRT
 533 #include <asm/paravirt.h>
 534 #else
 535 #define __cpuid                 native_cpuid
 536 #define paravirt_enabled()      0
 537
 538 /*
 539  * These special macros can be used to get or set a debugging register
 540  */
 541 #define get_debugreg(var, register)                             \
 542         (var) = native_get_debugreg(register)
 543 #define set_debugreg(value, register)                           \
 544         native_set_debugreg(register, value)
 545
 546 static inline void load_sp0(struct tss_struct *tss,
 547                             struct thread_struct *thread)
 548 {
 549         native_load_sp0(tss, thread);
 550 }
 551
 552 #define set_iopl_mask native_set_iopl_mask
 553 #endif /* CONFIG_PARAVIRT */
 554
 555 /*
 556  * Save the cr4 feature set we're using (ie
 557  * Pentium 4MB enable and PPro Global page
 558  * enable), so that any CPU's that boot up
 559  * after us can get the correct flags.
 560  */
 561 extern unsigned long            mmu_cr4_features;
 562
 563 static inline void set_in_cr4(unsigned long mask)
 564 {
 565         unsigned cr4;
 566
 567         mmu_cr4_features |= mask;
 568         cr4 = read_cr4();
 569         cr4 |= mask;
 570         write_cr4(cr4);
 571 }
 572
 573 static inline void clear_in_cr4(unsigned long mask)
 574 {
 575         unsigned cr4;
 576
 577         mmu_cr4_features &= ~mask;
 578         cr4 = read_cr4();
 579         cr4 &= ~mask;
 580         write_cr4(cr4);
 581 }
 582
 583 struct microcode_header {
 584         unsigned int            hdrver;
 585         unsigned int            rev;
 586         unsigned int            date;
 587         unsigned int            sig;
 588         unsigned int            cksum;
 589         unsigned int            ldrver;
 590         unsigned int            pf;
 591         unsigned int            datasize;
 592         unsigned int            totalsize;
 593         unsigned int            reserved[3];
 594 };
 595
 596 struct microcode {
 597         struct microcode_header hdr;
 598         unsigned int            bits[0];
 599 };
 600
 601 typedef struct microcode        microcode_t;
 602 typedef struct microcode_header microcode_header_t;
 603
 604 /* microcode format is extended from prescott processors */
 605 struct extended_signature {
 606         unsigned int            sig;
 607         unsigned int            pf;
 608         unsigned int            cksum;
 609 };
 610
 611 struct extended_sigtable {
 612         unsigned int            count;
 613         unsigned int            cksum;
 614         unsigned int            reserved[3];
 615         struct extended_signature sigs[0];
 616 };
 617
 618 typedef struct {
 619         unsigned long           seg;
 620 } mm_segment_t;
 621
 622
 623 /*
 624  * create a kernel thread without removing it from tasklists
 625  */
 626 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 627
 628 /* Free all resources held by a thread. */
 629 extern void release_thread(struct task_struct *);
 630
 631 /* Prepare to copy thread state - unlazy all lazy state */
 632 extern void prepare_to_copy(struct task_struct *tsk);
 633
 634 unsigned long get_wchan(struct task_struct *p);
 635
 636 /*
 637  * Generic CPUID function
 638  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 639  * resulting in stale register contents being returned.
 640  */
 641 static inline void cpuid(unsigned int op,
 642                          unsigned int *eax, unsigned int *ebx,
 643                          unsigned int *ecx, unsigned int *edx)
 644 {
 645         *eax = op;
 646         *ecx = 0;
 647         __cpuid(eax, ebx, ecx, edx);
 648 }
 649
 650 /* Some CPUID calls want 'count' to be placed in ecx */
 651 static inline void cpuid_count(unsigned int op, int count,
 652                                unsigned int *eax, unsigned int *ebx,
 653                                unsigned int *ecx, unsigned int *edx)
 654 {
 655         *eax = op;
 656         *ecx = count;
 657         __cpuid(eax, ebx, ecx, edx);
 658 }
 659
 660 /*
 661  * CPUID functions returning a single datum
 662  */
 663 static inline unsigned int cpuid_eax(unsigned int op)
 664 {
 665         unsigned int eax, ebx, ecx, edx;
 666
 667         cpuid(op, &eax, &ebx, &ecx, &edx);
 668
 669         return eax;
 670 }
 671
 672 static inline unsigned int cpuid_ebx(unsigned int op)
 673 {
 674         unsigned int eax, ebx, ecx, edx;
 675
 676         cpuid(op, &eax, &ebx, &ecx, &edx);
 677
 678         return ebx;
 679 }
 680
 681 static inline unsigned int cpuid_ecx(unsigned int op)
 682 {
 683         unsigned int eax, ebx, ecx, edx;
 684
 685         cpuid(op, &eax, &ebx, &ecx, &edx);
 686
 687         return ecx;
 688 }
 689
 690 static inline unsigned int cpuid_edx(unsigned int op)
 691 {
 692         unsigned int eax, ebx, ecx, edx;
 693
 694         cpuid(op, &eax, &ebx, &ecx, &edx);
 695
 696         return edx;
 697 }
 698
 699 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 700 static inline void rep_nop(void)
 701 {
 702         asm volatile("rep; nop" ::: "memory");
 703 }
 704
 705 static inline void cpu_relax(void)
 706 {
 707         rep_nop();
 708 }
 709
 710 /* Stop speculative execution: */
 711 static inline void sync_core(void)
 712 {
 713         int tmp;
 714
 715         asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 716                      : "ebx", "ecx", "edx", "memory");
 717 }
 718
 719 static inline void __monitor(const void *eax, unsigned long ecx,
 720                              unsigned long edx)
 721 {
 722         /* "monitor %eax, %ecx, %edx;" */
 723         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 724                      :: "a" (eax), "c" (ecx), "d"(edx));
 725 }
 726
 727 static inline void __mwait(unsigned long eax, unsigned long ecx)
 728 {
 729         /* "mwait %eax, %ecx;" */
 730         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 731                      :: "a" (eax), "c" (ecx));
 732 }
 733
 734 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 735 {
 736         trace_hardirqs_on();
 737         /* "mwait %eax, %ecx;" */
 738         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 739                      :: "a" (eax), "c" (ecx));
 740 }
 741
 742 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 743
 744 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 745
 746 extern unsigned long            boot_option_idle_override;
 747 extern unsigned long            idle_halt;
 748 extern unsigned long            idle_nomwait;
 749
 750 /*
 751  * on systems with caches, caches must be flashed as the absolute
 752  * last instruction before going into a suspended halt.  Otherwise,
 753  * dirty data can linger in the cache and become stale on resume,
 754  * leading to strange errors.
 755  *
 756  * perform a variety of operations to guarantee that the compiler
 757  * will not reorder instructions.  wbinvd itself is serializing
 758  * so the processor will not reorder.
 759  *
 760  * Systems without cache can just go into halt.
 761  */
 762 static inline void wbinvd_halt(void)
 763 {
 764         mb();
 765         /* check for clflush to determine if wbinvd is legal */
 766         if (cpu_has_clflush)
 767                 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
 768         else
 769                 while (1)
 770                         halt();
 771 }
 772
 773 extern void enable_sep_cpu(void);
 774 extern int sysenter_setup(void);
 775
 776 /* Defined in head.S */
 777 extern struct desc_ptr          early_gdt_descr;
 778
 779 extern void cpu_set_gdt(int);
 780 extern void switch_to_new_gdt(void);
 781 extern void cpu_init(void);
 782 extern void init_gdt(int cpu);
 783
 784 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 785 {
 786 #ifndef CONFIG_X86_DEBUGCTLMSR
 787         if (boot_cpu_data.x86 < 6)
 788                 return;
 789 #endif
 790         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 791 }
 792
 793 /*
 794  * from system description table in BIOS. Mostly for MCA use, but
 795  * others may find it useful:
 796  */
 797 extern unsigned int             machine_id;
 798 extern unsigned int             machine_submodel_id;
 799 extern unsigned int             BIOS_revision;
 800
 801 /* Boot loader type from the setup header: */
 802 extern int                      bootloader_type;
 803
 804 extern char                     ignore_fpu_irq;
 805
 806 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 807 #define ARCH_HAS_PREFETCHW
 808 #define ARCH_HAS_SPINLOCK_PREFETCH
 809
 810 #ifdef CONFIG_X86_32
 811 # define BASE_PREFETCH          ASM_NOP4
 812 # define ARCH_HAS_PREFETCH
 813 #else
 814 # define BASE_PREFETCH          "prefetcht0 (%1)"
 815 #endif
 816
 817 /*
 818  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 819  *
 820  * It's not worth to care about 3dnow prefetches for the K6
 821  * because they are microcoded there and very slow.
 822  */
 823 static inline void prefetch(const void *x)
 824 {
 825         alternative_input(BASE_PREFETCH,
 826                           "prefetchnta (%1)",
 827                           X86_FEATURE_XMM,
 828                           "r" (x));
 829 }
 830
 831 /*
 832  * 3dnow prefetch to get an exclusive cache line.
 833  * Useful for spinlocks to avoid one state transition in the
 834  * cache coherency protocol:
 835  */
 836 static inline void prefetchw(const void *x)
 837 {
 838         alternative_input(BASE_PREFETCH,
 839                           "prefetchw (%1)",
 840                           X86_FEATURE_3DNOW,
 841                           "r" (x));
 842 }
 843
 844 static inline void spin_lock_prefetch(const void *x)
 845 {
 846         prefetchw(x);
 847 }
 848
 849 #ifdef CONFIG_X86_32
 850 /*
 851  * User space process size: 3GB (default).
 852  */
 853 #define TASK_SIZE               PAGE_OFFSET
 854 #define STACK_TOP               TASK_SIZE
 855 #define STACK_TOP_MAX           STACK_TOP
 856
 857 #define INIT_THREAD  {                                                    \
 858         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 859         .vm86_info              = NULL,                                   \
 860         .sysenter_cs            = __KERNEL_CS,                            \
 861         .io_bitmap_ptr          = NULL,                                   \
 862         .fs                     = __KERNEL_PERCPU,                        \
 863 }
 864
 865 /*
 866  * Note that the .io_bitmap member must be extra-big. This is because
 867  * the CPU will access an additional byte beyond the end of the IO
 868  * permission bitmap. The extra byte must be all 1 bits, and must
 869  * be within the limit.
 870  */
 871 #define INIT_TSS  {                                                       \
 872         .x86_tss = {                                                      \
 873                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 874                 .ss0            = __KERNEL_DS,                            \
 875                 .ss1            = __KERNEL_CS,                            \
 876                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 877          },                                                               \
 878         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 879 }
 880
 881 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 882
 883 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 884 #define KSTK_TOP(info)                                                 \
 885 ({                                                                     \
 886        unsigned long *__ptr = (unsigned long *)(info);                 \
 887        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 888 })
 889
 890 /*
 891  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 892  * This is necessary to guarantee that the entire "struct pt_regs"
 893  * is accessable even if the CPU haven't stored the SS/ESP registers
 894  * on the stack (interrupt gate does not save these registers
 895  * when switching to the same priv ring).
 896  * Therefore beware: accessing the ss/esp fields of the
 897  * "struct pt_regs" is possible, but they may contain the
 898  * completely wrong values.
 899  */
 900 #define task_pt_regs(task)                                             \
 901 ({                                                                     \
 902        struct pt_regs *__regs__;                                       \
 903        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 904        __regs__ - 1;                                                   \
 905 })
 906
 907 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 908
 909 #else
 910 /*
 911  * User space process size. 47bits minus one guard page.
 912  */
 913 #define TASK_SIZE64     ((1UL << 47) - PAGE_SIZE)
 914
 915 /* This decides where the kernel will search for a free chunk of vm
 916  * space during mmap's.
 917  */
 918 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 919                                         0xc0000000 : 0xFFFFe000)
 920
 921 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 922                                         IA32_PAGE_OFFSET : TASK_SIZE64)
 923 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 924                                         IA32_PAGE_OFFSET : TASK_SIZE64)
 925
 926 #define STACK_TOP               TASK_SIZE
 927 #define STACK_TOP_MAX           TASK_SIZE64
 928
 929 #define INIT_THREAD  { \
 930         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 931 }
 932
 933 #define INIT_TSS  { \
 934         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 935 }
 936
 937 /*
 938  * Return saved PC of a blocked thread.
 939  * What is this good for? it will be always the scheduler or ret_from_fork.
 940  */
 941 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 942
 943 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 944 #define KSTK_ESP(tsk)           -1 /* sorry. doesn't work for syscall. */
 945 #endif /* CONFIG_X86_64 */
 946
 947 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 948                                                unsigned long new_sp);
 949
 950 /*
 951  * This decides where the kernel will search for a free chunk of vm
 952  * space during mmap's.
 953  */
 954 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 955
 956 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 957
 958 /* Get/set a process' ability to use the timestamp counter instruction */
 959 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 960 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 961
 962 extern int get_tsc_mode(unsigned long adr);
 963 extern int set_tsc_mode(unsigned int val);
 964
 965 #endif /* ASM_X86__PROCESSOR_H */