include/asm-x86/processor_32.h

   1 /*
   2  * Copyright (C) 1994 Linus Torvalds
   3  */
   4
   5 #ifndef __ASM_I386_PROCESSOR_H
   6 #define __ASM_I386_PROCESSOR_H
   7
   8 #include <asm/vm86.h>
   9 #include <asm/math_emu.h>
  10 #include <asm/segment.h>
  11 #include <asm/page.h>
  12 #include <asm/types.h>
  13 #include <asm/sigcontext.h>
  14 #include <asm/cpufeature.h>
  15 #include <asm/msr.h>
  16 #include <asm/system.h>
  17 #include <linux/cache.h>
  18 #include <linux/threads.h>
  19 #include <asm/percpu.h>
  20 #include <linux/cpumask.h>
  21 #include <linux/init.h>
  22 #include <asm/processor-flags.h>
  23
  24 /* flag for disabling the tsc */
  25 extern int tsc_disable;
  26
  27 struct desc_struct {
  28         unsigned long a,b;
  29 };
  30
  31 static inline int desc_empty(const void *ptr)
  32 {
  33         const u32 *desc = ptr;
  34         return !(desc[0] | desc[1]);
  35 }
  36
  37 /*
  38  * Default implementation of macro that returns current
  39  * instruction pointer ("program counter").
  40  */
  41 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
  42
  43 /*
  44  *  CPU type and hardware bug flags. Kept separately for each CPU.
  45  *  Members of this structure are referenced in head.S, so think twice
  46  *  before touching them. [mj]
  47  */
  48
  49 struct cpuinfo_x86 {
  50         __u8    x86;            /* CPU family */
  51         __u8    x86_vendor;     /* CPU vendor */
  52         __u8    x86_model;
  53         __u8    x86_mask;
  54         char    wp_works_ok;    /* It doesn't on 386's */
  55         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  56         char    hard_math;
  57         char    rfu;
  58         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  59         unsigned long   x86_capability[NCAPINTS];
  60         char    x86_vendor_id[16];
  61         char    x86_model_id[64];
  62         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  63                                     call  */
  64         int     x86_cache_alignment;    /* In bytes */
  65         char    fdiv_bug;
  66         char    f00f_bug;
  67         char    coma_bug;
  68         char    pad0;
  69         int     x86_power;
  70         unsigned long loops_per_jiffy;
  71 #ifdef CONFIG_SMP
  72         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  73 #endif
  74         unsigned char x86_max_cores;    /* cpuid returned max cores value */
  75         unsigned char apicid;
  76         unsigned short x86_clflush_size;
  77 #ifdef CONFIG_SMP
  78         unsigned char booted_cores;     /* number of cores as seen by OS */
  79         __u8 phys_proc_id;              /* Physical processor id. */
  80         __u8 cpu_core_id;               /* Core id */
  81         __u8 cpu_index;                 /* index into per_cpu list */
  82 #endif
  83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  84
  85 #define X86_VENDOR_INTEL 0
  86 #define X86_VENDOR_CYRIX 1
  87 #define X86_VENDOR_AMD 2
  88 #define X86_VENDOR_UMC 3
  89 #define X86_VENDOR_NEXGEN 4
  90 #define X86_VENDOR_CENTAUR 5
  91 #define X86_VENDOR_TRANSMETA 7
  92 #define X86_VENDOR_NSC 8
  93 #define X86_VENDOR_NUM 9
  94 #define X86_VENDOR_UNKNOWN 0xff
  95
  96 /*
  97  * capabilities of CPUs
  98  */
  99
 100 extern struct cpuinfo_x86 boot_cpu_data;
 101 extern struct cpuinfo_x86 new_cpu_data;
 102 extern struct tss_struct doublefault_tss;
 103 DECLARE_PER_CPU(struct tss_struct, init_tss);
 104
 105 #ifdef CONFIG_SMP
 106 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 107 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 108 #define current_cpu_data        cpu_data(smp_processor_id())
 109 #else
 110 #define cpu_data(cpu)           boot_cpu_data
 111 #define current_cpu_data        boot_cpu_data
 112 #endif
 113
 114 /*
 115  * the following now lives in the per cpu area:
 116  * extern       int cpu_llc_id[NR_CPUS];
 117  */
 118 DECLARE_PER_CPU(u8, cpu_llc_id);
 119 extern char ignore_fpu_irq;
 120
 121 void __init cpu_detect(struct cpuinfo_x86 *c);
 122
 123 extern void identify_boot_cpu(void);
 124 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 125 extern void print_cpu_info(struct cpuinfo_x86 *);
 126 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 127 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 128 extern unsigned short num_cache_leaves;
 129
 130 #ifdef CONFIG_X86_HT
 131 extern void detect_ht(struct cpuinfo_x86 *c);
 132 #else
 133 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 134 #endif
 135
 136 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 137                                          unsigned int *ecx, unsigned int *edx)
 138 {
 139         /* ecx is often an input as well as an output. */
 140         __asm__("cpuid"
 141                 : "=a" (*eax),
 142                   "=b" (*ebx),
 143                   "=c" (*ecx),
 144                   "=d" (*edx)
 145                 : "0" (*eax), "2" (*ecx));
 146 }
 147
 148 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
 149
 150 /*
 151  * Save the cr4 feature set we're using (ie
 152  * Pentium 4MB enable and PPro Global page
 153  * enable), so that any CPU's that boot up
 154  * after us can get the correct flags.
 155  */
 156 extern unsigned long mmu_cr4_features;
 157
 158 static inline void set_in_cr4 (unsigned long mask)
 159 {
 160         unsigned cr4;
 161         mmu_cr4_features |= mask;
 162         cr4 = read_cr4();
 163         cr4 |= mask;
 164         write_cr4(cr4);
 165 }
 166
 167 static inline void clear_in_cr4 (unsigned long mask)
 168 {
 169         unsigned cr4;
 170         mmu_cr4_features &= ~mask;
 171         cr4 = read_cr4();
 172         cr4 &= ~mask;
 173         write_cr4(cr4);
 174 }
 175
 176 /* Stop speculative execution */
 177 static inline void sync_core(void)
 178 {
 179         int tmp;
 180         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 181 }
 182
 183 static inline void __monitor(const void *eax, unsigned long ecx,
 184                 unsigned long edx)
 185 {
 186         /* "monitor %eax,%ecx,%edx;" */
 187         asm volatile(
 188                 ".byte 0x0f,0x01,0xc8;"
 189                 : :"a" (eax), "c" (ecx), "d"(edx));
 190 }
 191
 192 static inline void __mwait(unsigned long eax, unsigned long ecx)
 193 {
 194         /* "mwait %eax,%ecx;" */
 195         asm volatile(
 196                 ".byte 0x0f,0x01,0xc9;"
 197                 : :"a" (eax), "c" (ecx));
 198 }
 199
 200 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 201
 202 /* from system description table in BIOS.  Mostly for MCA use, but
 203 others may find it useful. */
 204 extern unsigned int machine_id;
 205 extern unsigned int machine_submodel_id;
 206 extern unsigned int BIOS_revision;
 207 extern unsigned int mca_pentium_flag;
 208
 209 /* Boot loader type from the setup header */
 210 extern int bootloader_type;
 211
 212 /*
 213  * User space process size: 3GB (default).
 214  */
 215 #define TASK_SIZE       (PAGE_OFFSET)
 216
 217 /* This decides where the kernel will search for a free chunk of vm
 218  * space during mmap's.
 219  */
 220 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 221
 222 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 223
 224 extern void hard_disable_TSC(void);
 225 extern void disable_TSC(void);
 226 extern void hard_enable_TSC(void);
 227
 228 /*
 229  * Size of io_bitmap.
 230  */
 231 #define IO_BITMAP_BITS  65536
 232 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 233 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 234 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 235 #define INVALID_IO_BITMAP_OFFSET 0x8000
 236 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 237
 238 struct i387_fsave_struct {
 239         long    cwd;
 240         long    swd;
 241         long    twd;
 242         long    fip;
 243         long    fcs;
 244         long    foo;
 245         long    fos;
 246         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 247         long    status;         /* software status information */
 248 };
 249
 250 struct i387_fxsave_struct {
 251         unsigned short  cwd;
 252         unsigned short  swd;
 253         unsigned short  twd;
 254         unsigned short  fop;
 255         long    fip;
 256         long    fcs;
 257         long    foo;
 258         long    fos;
 259         long    mxcsr;
 260         long    mxcsr_mask;
 261         long    st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 262         long    xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
 263         long    padding[56];
 264 } __attribute__ ((aligned (16)));
 265
 266 struct i387_soft_struct {
 267         long    cwd;
 268         long    swd;
 269         long    twd;
 270         long    fip;
 271         long    fcs;
 272         long    foo;
 273         long    fos;
 274         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 275         unsigned char   ftop, changed, lookahead, no_update, rm, alimit;
 276         struct info     *info;
 277         unsigned long   entry_eip;
 278 };
 279
 280 union i387_union {
 281         struct i387_fsave_struct        fsave;
 282         struct i387_fxsave_struct       fxsave;
 283         struct i387_soft_struct soft;
 284 };
 285
 286 typedef struct {
 287         unsigned long seg;
 288 } mm_segment_t;
 289
 290 struct thread_struct;
 291
 292 /* This is the TSS defined by the hardware. */
 293 struct i386_hw_tss {
 294         unsigned short  back_link,__blh;
 295         unsigned long   esp0;
 296         unsigned short  ss0,__ss0h;
 297         unsigned long   esp1;
 298         unsigned short  ss1,__ss1h;     /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
 299         unsigned long   esp2;
 300         unsigned short  ss2,__ss2h;
 301         unsigned long   __cr3;
 302         unsigned long   eip;
 303         unsigned long   eflags;
 304         unsigned long   eax,ecx,edx,ebx;
 305         unsigned long   esp;
 306         unsigned long   ebp;
 307         unsigned long   esi;
 308         unsigned long   edi;
 309         unsigned short  es, __esh;
 310         unsigned short  cs, __csh;
 311         unsigned short  ss, __ssh;
 312         unsigned short  ds, __dsh;
 313         unsigned short  fs, __fsh;
 314         unsigned short  gs, __gsh;
 315         unsigned short  ldt, __ldth;
 316         unsigned short  trace, io_bitmap_base;
 317 } __attribute__((packed));
 318
 319 struct tss_struct {
 320         struct i386_hw_tss x86_tss;
 321
 322         /*
 323          * The extra 1 is there because the CPU will access an
 324          * additional byte beyond the end of the IO permission
 325          * bitmap. The extra byte must be all 1 bits, and must
 326          * be within the limit.
 327          */
 328         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 329         /*
 330          * Cache the current maximum and the last task that used the bitmap:
 331          */
 332         unsigned long io_bitmap_max;
 333         struct thread_struct *io_bitmap_owner;
 334         /*
 335          * pads the TSS to be cacheline-aligned (size is 0x100)
 336          */
 337         unsigned long __cacheline_filler[35];
 338         /*
 339          * .. and then another 0x100 bytes for emergency kernel stack
 340          */
 341         unsigned long stack[64];
 342 } __attribute__((packed));
 343
 344 #define ARCH_MIN_TASKALIGN      16
 345
 346 struct thread_struct {
 347 /* cached TLS descriptors. */
 348         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 349         unsigned long   esp0;
 350         unsigned long   sysenter_cs;
 351         unsigned long   eip;
 352         unsigned long   esp;
 353         unsigned long   fs;
 354         unsigned long   gs;
 355 /* Hardware debugging registers */
 356         unsigned long   debugreg[8];  /* %%db0-7 debug registers */
 357 /* fault info */
 358         unsigned long   cr2, trap_no, error_code;
 359 /* floating point info */
 360         union i387_union        i387;
 361 /* virtual 86 mode info */
 362         struct vm86_struct __user * vm86_info;
 363         unsigned long           screen_bitmap;
 364         unsigned long           v86flags, v86mask, saved_esp0;
 365         unsigned int            saved_fs, saved_gs;
 366 /* IO permissions */
 367         unsigned long   *io_bitmap_ptr;
 368         unsigned long   iopl;
 369 /* max allowed port in the bitmap, in bytes: */
 370         unsigned long   io_bitmap_max;
 371 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 372         unsigned long   debugctlmsr;
 373 };
 374
 375 #define INIT_THREAD  {                                                  \
 376         .esp0 = sizeof(init_stack) + (long)&init_stack,                 \
 377         .vm86_info = NULL,                                              \
 378         .sysenter_cs = __KERNEL_CS,                                     \
 379         .io_bitmap_ptr = NULL,                                          \
 380         .fs = __KERNEL_PERCPU,                                          \
 381 }
 382
 383 /*
 384  * Note that the .io_bitmap member must be extra-big. This is because
 385  * the CPU will access an additional byte beyond the end of the IO
 386  * permission bitmap. The extra byte must be all 1 bits, and must
 387  * be within the limit.
 388  */
 389 #define INIT_TSS  {                                                     \
 390         .x86_tss = {                                                    \
 391                 .esp0           = sizeof(init_stack) + (long)&init_stack, \
 392                 .ss0            = __KERNEL_DS,                          \
 393                 .ss1            = __KERNEL_CS,                          \
 394                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,             \
 395          },                                                             \
 396         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 397 }
 398
 399 #define start_thread(regs, new_eip, new_esp) do {               \
 400         __asm__("movl %0,%%gs": :"r" (0));                      \
 401         regs->fs = 0;                                           \
 402         set_fs(USER_DS);                                        \
 403         regs->ds = __USER_DS;                                   \
 404         regs->es = __USER_DS;                                   \
 405         regs->ss = __USER_DS;                                   \
 406         regs->cs = __USER_CS;                                   \
 407         regs->ip = new_eip;                                     \
 408         regs->sp = new_esp;                                     \
 409 } while (0)
 410
 411 /* Forward declaration, a strange C thing */
 412 struct task_struct;
 413 struct mm_struct;
 414
 415 /* Free all resources held by a thread. */
 416 extern void release_thread(struct task_struct *);
 417
 418 /* Prepare to copy thread state - unlazy all lazy status */
 419 extern void prepare_to_copy(struct task_struct *tsk);
 420
 421 /*
 422  * create a kernel thread without removing it from tasklists
 423  */
 424 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 425
 426 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 427
 428 unsigned long get_wchan(struct task_struct *p);
 429
 430 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 431 #define KSTK_TOP(info)                                                 \
 432 ({                                                                     \
 433        unsigned long *__ptr = (unsigned long *)(info);                 \
 434        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 435 })
 436
 437 /*
 438  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 439  * This is necessary to guarantee that the entire "struct pt_regs"
 440  * is accessable even if the CPU haven't stored the SS/ESP registers
 441  * on the stack (interrupt gate does not save these registers
 442  * when switching to the same priv ring).
 443  * Therefore beware: accessing the ss/esp fields of the
 444  * "struct pt_regs" is possible, but they may contain the
 445  * completely wrong values.
 446  */
 447 #define task_pt_regs(task)                                             \
 448 ({                                                                     \
 449        struct pt_regs *__regs__;                                       \
 450        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 451        __regs__ - 1;                                                   \
 452 })
 453
 454 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
 455 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
 456
 457
 458 struct microcode_header {
 459         unsigned int hdrver;
 460         unsigned int rev;
 461         unsigned int date;
 462         unsigned int sig;
 463         unsigned int cksum;
 464         unsigned int ldrver;
 465         unsigned int pf;
 466         unsigned int datasize;
 467         unsigned int totalsize;
 468         unsigned int reserved[3];
 469 };
 470
 471 struct microcode {
 472         struct microcode_header hdr;
 473         unsigned int bits[0];
 474 };
 475
 476 typedef struct microcode microcode_t;
 477 typedef struct microcode_header microcode_header_t;
 478
 479 /* microcode format is extended from prescott processors */
 480 struct extended_signature {
 481         unsigned int sig;
 482         unsigned int pf;
 483         unsigned int cksum;
 484 };
 485
 486 struct extended_sigtable {
 487         unsigned int count;
 488         unsigned int cksum;
 489         unsigned int reserved[3];
 490         struct extended_signature sigs[0];
 491 };
 492
 493 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 494 static inline void rep_nop(void)
 495 {
 496         __asm__ __volatile__("rep;nop": : :"memory");
 497 }
 498
 499 #define cpu_relax()     rep_nop()
 500
 501 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 502 {
 503         tss->x86_tss.esp0 = thread->esp0;
 504         /* This can only happen when SEP is enabled, no need to test "SEP"arately */
 505         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 506                 tss->x86_tss.ss1 = thread->sysenter_cs;
 507                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 508         }
 509 }
 510
 511
 512 static inline unsigned long native_get_debugreg(int regno)
 513 {
 514         unsigned long val = 0;  /* Damn you, gcc! */
 515
 516         switch (regno) {
 517         case 0:
 518                 asm("movl %%db0, %0" :"=r" (val)); break;
 519         case 1:
 520                 asm("movl %%db1, %0" :"=r" (val)); break;
 521         case 2:
 522                 asm("movl %%db2, %0" :"=r" (val)); break;
 523         case 3:
 524                 asm("movl %%db3, %0" :"=r" (val)); break;
 525         case 6:
 526                 asm("movl %%db6, %0" :"=r" (val)); break;
 527         case 7:
 528                 asm("movl %%db7, %0" :"=r" (val)); break;
 529         default:
 530                 BUG();
 531         }
 532         return val;
 533 }
 534
 535 static inline void native_set_debugreg(int regno, unsigned long value)
 536 {
 537         switch (regno) {
 538         case 0:
 539                 asm("movl %0,%%db0"     : /* no output */ :"r" (value));
 540                 break;
 541         case 1:
 542                 asm("movl %0,%%db1"     : /* no output */ :"r" (value));
 543                 break;
 544         case 2:
 545                 asm("movl %0,%%db2"     : /* no output */ :"r" (value));
 546                 break;
 547         case 3:
 548                 asm("movl %0,%%db3"     : /* no output */ :"r" (value));
 549                 break;
 550         case 6:
 551                 asm("movl %0,%%db6"     : /* no output */ :"r" (value));
 552                 break;
 553         case 7:
 554                 asm("movl %0,%%db7"     : /* no output */ :"r" (value));
 555                 break;
 556         default:
 557                 BUG();
 558         }
 559 }
 560
 561 /*
 562  * Set IOPL bits in EFLAGS from given mask
 563  */
 564 static inline void native_set_iopl_mask(unsigned mask)
 565 {
 566         unsigned int reg;
 567         __asm__ __volatile__ ("pushfl;"
 568                               "popl %0;"
 569                               "andl %1, %0;"
 570                               "orl %2, %0;"
 571                               "pushl %0;"
 572                               "popfl"
 573                                 : "=&r" (reg)
 574                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 575 }
 576
 577 #ifdef CONFIG_PARAVIRT
 578 #include <asm/paravirt.h>
 579 #else
 580 #define paravirt_enabled() 0
 581 #define __cpuid native_cpuid
 582
 583 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 584 {
 585         native_load_esp0(tss, thread);
 586 }
 587
 588 /*
 589  * These special macros can be used to get or set a debugging register
 590  */
 591 #define get_debugreg(var, register)                             \
 592         (var) = native_get_debugreg(register)
 593 #define set_debugreg(value, register)                           \
 594         native_set_debugreg(register, value)
 595
 596 #define set_iopl_mask native_set_iopl_mask
 597 #endif /* CONFIG_PARAVIRT */
 598
 599 /*
 600  * Generic CPUID function
 601  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 602  * resulting in stale register contents being returned.
 603  */
 604 static inline void cpuid(unsigned int op,
 605                          unsigned int *eax, unsigned int *ebx,
 606                          unsigned int *ecx, unsigned int *edx)
 607 {
 608         *eax = op;
 609         *ecx = 0;
 610         __cpuid(eax, ebx, ecx, edx);
 611 }
 612
 613 /* Some CPUID calls want 'count' to be placed in ecx */
 614 static inline void cpuid_count(unsigned int op, int count,
 615                                unsigned int *eax, unsigned int *ebx,
 616                                unsigned int *ecx, unsigned int *edx)
 617 {
 618         *eax = op;
 619         *ecx = count;
 620         __cpuid(eax, ebx, ecx, edx);
 621 }
 622
 623 /*
 624  * CPUID functions returning a single datum
 625  */
 626 static inline unsigned int cpuid_eax(unsigned int op)
 627 {
 628         unsigned int eax, ebx, ecx, edx;
 629
 630         cpuid(op, &eax, &ebx, &ecx, &edx);
 631         return eax;
 632 }
 633 static inline unsigned int cpuid_ebx(unsigned int op)
 634 {
 635         unsigned int eax, ebx, ecx, edx;
 636
 637         cpuid(op, &eax, &ebx, &ecx, &edx);
 638         return ebx;
 639 }
 640 static inline unsigned int cpuid_ecx(unsigned int op)
 641 {
 642         unsigned int eax, ebx, ecx, edx;
 643
 644         cpuid(op, &eax, &ebx, &ecx, &edx);
 645         return ecx;
 646 }
 647 static inline unsigned int cpuid_edx(unsigned int op)
 648 {
 649         unsigned int eax, ebx, ecx, edx;
 650
 651         cpuid(op, &eax, &ebx, &ecx, &edx);
 652         return edx;
 653 }
 654
 655 /* generic versions from gas */
 656 #define GENERIC_NOP1    ".byte 0x90\n"
 657 #define GENERIC_NOP2            ".byte 0x89,0xf6\n"
 658 #define GENERIC_NOP3        ".byte 0x8d,0x76,0x00\n"
 659 #define GENERIC_NOP4        ".byte 0x8d,0x74,0x26,0x00\n"
 660 #define GENERIC_NOP5        GENERIC_NOP1 GENERIC_NOP4
 661 #define GENERIC_NOP6    ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
 662 #define GENERIC_NOP7    ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
 663 #define GENERIC_NOP8    GENERIC_NOP1 GENERIC_NOP7
 664
 665 /* Opteron nops */
 666 #define K8_NOP1 GENERIC_NOP1
 667 #define K8_NOP2 ".byte 0x66,0x90\n"
 668 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 669 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 670 #define K8_NOP5 K8_NOP3 K8_NOP2
 671 #define K8_NOP6 K8_NOP3 K8_NOP3
 672 #define K8_NOP7 K8_NOP4 K8_NOP3
 673 #define K8_NOP8 K8_NOP4 K8_NOP4
 674
 675 /* K7 nops */
 676 /* uses eax dependencies (arbitary choice) */
 677 #define K7_NOP1  GENERIC_NOP1
 678 #define K7_NOP2 ".byte 0x8b,0xc0\n"
 679 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
 680 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
 681 #define K7_NOP5 K7_NOP4 ASM_NOP1
 682 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
 683 #define K7_NOP7        ".byte 0x8D,0x04,0x05,0,0,0,0\n"
 684 #define K7_NOP8        K7_NOP7 ASM_NOP1
 685
 686 /* P6 nops */
 687 /* uses eax dependencies (Intel-recommended choice) */
 688 #define P6_NOP1 GENERIC_NOP1
 689 #define P6_NOP2 ".byte 0x66,0x90\n"
 690 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
 691 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
 692 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
 693 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
 694 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
 695 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
 696
 697 #ifdef CONFIG_MK8
 698 #define ASM_NOP1 K8_NOP1
 699 #define ASM_NOP2 K8_NOP2
 700 #define ASM_NOP3 K8_NOP3
 701 #define ASM_NOP4 K8_NOP4
 702 #define ASM_NOP5 K8_NOP5
 703 #define ASM_NOP6 K8_NOP6
 704 #define ASM_NOP7 K8_NOP7
 705 #define ASM_NOP8 K8_NOP8
 706 #elif defined(CONFIG_MK7)
 707 #define ASM_NOP1 K7_NOP1
 708 #define ASM_NOP2 K7_NOP2
 709 #define ASM_NOP3 K7_NOP3
 710 #define ASM_NOP4 K7_NOP4
 711 #define ASM_NOP5 K7_NOP5
 712 #define ASM_NOP6 K7_NOP6
 713 #define ASM_NOP7 K7_NOP7
 714 #define ASM_NOP8 K7_NOP8
 715 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
 716       defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
 717       defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
 718 #define ASM_NOP1 P6_NOP1
 719 #define ASM_NOP2 P6_NOP2
 720 #define ASM_NOP3 P6_NOP3
 721 #define ASM_NOP4 P6_NOP4
 722 #define ASM_NOP5 P6_NOP5
 723 #define ASM_NOP6 P6_NOP6
 724 #define ASM_NOP7 P6_NOP7
 725 #define ASM_NOP8 P6_NOP8
 726 #else
 727 #define ASM_NOP1 GENERIC_NOP1
 728 #define ASM_NOP2 GENERIC_NOP2
 729 #define ASM_NOP3 GENERIC_NOP3
 730 #define ASM_NOP4 GENERIC_NOP4
 731 #define ASM_NOP5 GENERIC_NOP5
 732 #define ASM_NOP6 GENERIC_NOP6
 733 #define ASM_NOP7 GENERIC_NOP7
 734 #define ASM_NOP8 GENERIC_NOP8
 735 #endif
 736
 737 #define ASM_NOP_MAX 8
 738
 739 /* Prefetch instructions for Pentium III and AMD Athlon */
 740 /* It's not worth to care about 3dnow! prefetches for the K6
 741    because they are microcoded there and very slow.
 742    However we don't do prefetches for pre XP Athlons currently
 743    That should be fixed. */
 744 #define ARCH_HAS_PREFETCH
 745 static inline void prefetch(const void *x)
 746 {
 747         alternative_input(ASM_NOP4,
 748                           "prefetchnta (%1)",
 749                           X86_FEATURE_XMM,
 750                           "r" (x));
 751 }
 752
 753 #define ARCH_HAS_PREFETCH
 754 #define ARCH_HAS_PREFETCHW
 755 #define ARCH_HAS_SPINLOCK_PREFETCH
 756
 757 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 758    spinlocks to avoid one state transition in the cache coherency protocol. */
 759 static inline void prefetchw(const void *x)
 760 {
 761         alternative_input(ASM_NOP4,
 762                           "prefetchw (%1)",
 763                           X86_FEATURE_3DNOW,
 764                           "r" (x));
 765 }
 766 #define spin_lock_prefetch(x)   prefetchw(x)
 767
 768 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 769
 770 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 771
 772 extern unsigned long boot_option_idle_override;
 773 extern void enable_sep_cpu(void);
 774 extern int sysenter_setup(void);
 775
 776 /* Defined in head.S */
 777 extern struct Xgt_desc_struct early_gdt_descr;
 778
 779 extern void cpu_set_gdt(int);
 780 extern void switch_to_new_gdt(void);
 781 extern void cpu_init(void);
 782 extern void init_gdt(int cpu);
 783
 784 extern int force_mwait;
 785
 786 #endif /* __ASM_I386_PROCESSOR_H */