2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_X86_64_PROCESSOR_H
6 #define __ASM_X86_64_PROCESSOR_H
8 #include <asm/segment.h>
10 #include <asm/types.h>
11 #include <asm/sigcontext.h>
12 #include <asm/cpufeature.h>
13 #include <linux/threads.h>
15 #include <asm/current.h>
16 #include <asm/system.h>
17 #include <asm/mmsegment.h>
18 #include <asm/percpu.h>
19 #include <linux/personality.h>
20 #include <linux/cpumask.h>
21 #include <asm/desc_defs.h>
24 * CPU type and hardware bug flags. Kept separately for each CPU.
28 __u8 x86
; /* CPU family */
29 __u8 x86_vendor
; /* CPU vendor */
32 int cpuid_level
; /* Maximum supported CPUID level, -1=no CPUID */
33 __u32 x86_capability
[NCAPINTS
];
34 char x86_vendor_id
[16];
35 char x86_model_id
[64];
36 int x86_cache_size
; /* in KB */
38 int x86_cache_alignment
;
39 int x86_tlbsize
; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
40 __u8 x86_virt_bits
, x86_phys_bits
;
41 __u8 x86_max_cores
; /* cpuid returned max cores value */
42 __u8 x86_coreid_bits
; /* cpuid returned core id bits */
44 __u32 extended_cpuid_level
; /* Max extended CPUID function supported */
45 unsigned long loops_per_jiffy
;
47 cpumask_t llc_shared_map
; /* cpus sharing the last level cache */
51 __u8 booted_cores
; /* number of cores as seen by OS */
52 __u8 phys_proc_id
; /* Physical Processor id. */
53 __u8 cpu_core_id
; /* Core id. */
54 __u8 cpu_index
; /* index into per_cpu list */
56 } ____cacheline_aligned
;
58 #define X86_VENDOR_INTEL 0
59 #define X86_VENDOR_CYRIX 1
60 #define X86_VENDOR_AMD 2
61 #define X86_VENDOR_UMC 3
62 #define X86_VENDOR_NEXGEN 4
63 #define X86_VENDOR_CENTAUR 5
64 #define X86_VENDOR_TRANSMETA 7
65 #define X86_VENDOR_NUM 8
66 #define X86_VENDOR_UNKNOWN 0xff
69 DECLARE_PER_CPU(struct cpuinfo_x86
, cpu_info
);
70 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
71 #define current_cpu_data cpu_data(smp_processor_id())
73 #define cpu_data(cpu) boot_cpu_data
74 #define current_cpu_data boot_cpu_data
77 extern char ignore_irq13
;
79 extern void identify_cpu(struct cpuinfo_x86
*);
82 * User space process size. 47bits minus one guard page.
84 #define TASK_SIZE64 (0x800000000000UL - 4096)
86 /* This decides where the kernel will search for a free chunk of vm
87 * space during mmap's.
89 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
91 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
92 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
95 struct i387_fxsave_struct
{
104 u32 st_space
[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
105 u32 xmm_space
[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
107 } __attribute__ ((aligned (16)));
110 struct i387_fxsave_struct fxsave
;
113 extern struct cpuinfo_x86 boot_cpu_data
;
114 /* Save the original ist values for checking stack pointers during debugging */
116 unsigned long ist
[7];
118 DECLARE_PER_CPU(struct orig_ist
, orig_ist
);
120 #define INIT_THREAD { \
121 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
125 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
129 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
131 #define start_thread(regs,new_rip,new_rsp) do { \
132 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
134 (regs)->ip = (new_rip); \
135 (regs)->sp = (new_rsp); \
136 write_pda(oldrsp, (new_rsp)); \
137 (regs)->cs = __USER_CS; \
138 (regs)->ss = __USER_DS; \
139 (regs)->flags = 0x200; \
144 * Return saved PC of a blocked thread.
145 * What is this good for? it will be always the scheduler or ret_from_fork.
147 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
149 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
150 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
153 #if defined(CONFIG_MPSC) || defined(CONFIG_MCORE2)
154 #define ASM_NOP1 P6_NOP1
155 #define ASM_NOP2 P6_NOP2
156 #define ASM_NOP3 P6_NOP3
157 #define ASM_NOP4 P6_NOP4
158 #define ASM_NOP5 P6_NOP5
159 #define ASM_NOP6 P6_NOP6
160 #define ASM_NOP7 P6_NOP7
161 #define ASM_NOP8 P6_NOP8
163 #define ASM_NOP1 K8_NOP1
164 #define ASM_NOP2 K8_NOP2
165 #define ASM_NOP3 K8_NOP3
166 #define ASM_NOP4 K8_NOP4
167 #define ASM_NOP5 K8_NOP5
168 #define ASM_NOP6 K8_NOP6
169 #define ASM_NOP7 K8_NOP7
170 #define ASM_NOP8 K8_NOP8
174 #define K8_NOP1 ".byte 0x90\n"
175 #define K8_NOP2 ".byte 0x66,0x90\n"
176 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
177 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
178 #define K8_NOP5 K8_NOP3 K8_NOP2
179 #define K8_NOP6 K8_NOP3 K8_NOP3
180 #define K8_NOP7 K8_NOP4 K8_NOP3
181 #define K8_NOP8 K8_NOP4 K8_NOP4
184 /* uses eax dependencies (Intel-recommended choice) */
185 #define P6_NOP1 ".byte 0x90\n"
186 #define P6_NOP2 ".byte 0x66,0x90\n"
187 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
188 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
189 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
190 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
191 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
192 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
194 #define ASM_NOP_MAX 8
196 static inline void prefetchw(void *x
)
198 alternative_input("prefetcht0 (%1)",
205 #define stack_current() \
207 struct thread_info *ti; \
208 asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
213 #endif /* __ASM_X86_64_PROCESSOR_H */