include/asm-x86_64/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/alternative.h>
   7
   8 #ifdef __KERNEL__
   9
  10 #define __STR(x) #x
  11 #define STR(x) __STR(x)
  12
  13 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  14 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  15
  16 /* frame pointer must be last for get_wchan */
  17 #define SAVE_CONTEXT    "pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  18 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp\n\t"
  19
  20 #define __EXTRA_CLOBBER  \
  21         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  22
  23 #define switch_to(prev,next,last) \
  24         asm volatile(SAVE_CONTEXT                                                   \
  25                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  26                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  27                      "call __switch_to\n\t"                                       \
  28                      ".globl thread_return\n"                                   \
  29                      "thread_return:\n\t"                                           \
  30                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  31                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  32                      LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
  33                      "movq %%rax,%%rdi\n\t"                                       \
  34                      "jc   ret_from_fork\n\t"                                     \
  35                      RESTORE_CONTEXT                                                \
  36                      : "=a" (last)                                                \
  37                      : [next] "S" (next), [prev] "D" (prev),                      \
  38                        [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
  39                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  40                        [tif_fork] "i" (TIF_FORK),                         \
  41                        [thread_info] "i" (offsetof(struct task_struct, thread_info)), \
  42                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  43                      : "memory", "cc" __EXTRA_CLOBBER)
  44
  45 extern void load_gs_index(unsigned);
  46
  47 /*
  48  * Load a segment. Fall back on loading the zero
  49  * segment if something goes wrong..
  50  */
  51 #define loadsegment(seg,value)  \
  52         asm volatile("\n"                       \
  53                 "1:\t"                          \
  54                 "movl %k0,%%" #seg "\n"         \
  55                 "2:\n"                          \
  56                 ".section .fixup,\"ax\"\n"      \
  57                 "3:\t"                          \
  58                 "movl %1,%%" #seg "\n\t"        \
  59                 "jmp 2b\n"                      \
  60                 ".previous\n"                   \
  61                 ".section __ex_table,\"a\"\n\t" \
  62                 ".align 8\n\t"                  \
  63                 ".quad 1b,3b\n"                 \
  64                 ".previous"                     \
  65                 : :"r" (value), "r" (0))
  66
  67 /*
  68  * Clear and set 'TS' bit respectively
  69  */
  70 #define clts() __asm__ __volatile__ ("clts")
  71
  72 static inline unsigned long read_cr0(void)
  73 {
  74         unsigned long cr0;
  75         asm volatile("movq %%cr0,%0" : "=r" (cr0));
  76         return cr0;
  77 }
  78
  79 static inline void write_cr0(unsigned long val)
  80 {
  81         asm volatile("movq %0,%%cr0" :: "r" (val));
  82 }
  83
  84 static inline unsigned long read_cr3(void)
  85 {
  86         unsigned long cr3;
  87         asm("movq %%cr3,%0" : "=r" (cr3));
  88         return cr3;
  89 }
  90
  91 static inline unsigned long read_cr4(void)
  92 {
  93         unsigned long cr4;
  94         asm("movq %%cr4,%0" : "=r" (cr4));
  95         return cr4;
  96 }
  97
  98 static inline void write_cr4(unsigned long val)
  99 {
 100         asm volatile("movq %0,%%cr4" :: "r" (val));
 101 }
 102
 103 #define stts() write_cr0(8 | read_cr0())
 104
 105 #define wbinvd() \
 106         __asm__ __volatile__ ("wbinvd": : :"memory");
 107
 108 /*
 109  * On SMP systems, when the scheduler does migration-cost autodetection,
 110  * it needs a way to flush as much of the CPU's caches as possible.
 111  */
 112 static inline void sched_cacheflush(void)
 113 {
 114         wbinvd();
 115 }
 116
 117 #endif  /* __KERNEL__ */
 118
 119 #define nop() __asm__ __volatile__ ("nop")
 120
 121 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 122
 123 #define tas(ptr) (xchg((ptr),1))
 124
 125 #define __xg(x) ((volatile long *)(x))
 126
 127 static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
 128 {
 129         *ptr = val;
 130 }
 131
 132 #define _set_64bit set_64bit
 133
 134 /*
 135  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 136  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 137  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 138  */
 139 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 140 {
 141         switch (size) {
 142                 case 1:
 143                         __asm__ __volatile__("xchgb %b0,%1"
 144                                 :"=q" (x)
 145                                 :"m" (*__xg(ptr)), "0" (x)
 146                                 :"memory");
 147                         break;
 148                 case 2:
 149                         __asm__ __volatile__("xchgw %w0,%1"
 150                                 :"=r" (x)
 151                                 :"m" (*__xg(ptr)), "0" (x)
 152                                 :"memory");
 153                         break;
 154                 case 4:
 155                         __asm__ __volatile__("xchgl %k0,%1"
 156                                 :"=r" (x)
 157                                 :"m" (*__xg(ptr)), "0" (x)
 158                                 :"memory");
 159                         break;
 160                 case 8:
 161                         __asm__ __volatile__("xchgq %0,%1"
 162                                 :"=r" (x)
 163                                 :"m" (*__xg(ptr)), "0" (x)
 164                                 :"memory");
 165                         break;
 166         }
 167         return x;
 168 }
 169
 170 /*
 171  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 172  * store NEW in MEM.  Return the initial value in MEM.  Success is
 173  * indicated by comparing RETURN with OLD.
 174  */
 175
 176 #define __HAVE_ARCH_CMPXCHG 1
 177
 178 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 179                                       unsigned long new, int size)
 180 {
 181         unsigned long prev;
 182         switch (size) {
 183         case 1:
 184                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 185                                      : "=a"(prev)
 186                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 187                                      : "memory");
 188                 return prev;
 189         case 2:
 190                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 191                                      : "=a"(prev)
 192                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 193                                      : "memory");
 194                 return prev;
 195         case 4:
 196                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
 197                                      : "=a"(prev)
 198                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 199                                      : "memory");
 200                 return prev;
 201         case 8:
 202                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
 203                                      : "=a"(prev)
 204                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 205                                      : "memory");
 206                 return prev;
 207         }
 208         return old;
 209 }
 210
 211 #define cmpxchg(ptr,o,n)\
 212         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 213                                         (unsigned long)(n),sizeof(*(ptr))))
 214
 215 #ifdef CONFIG_SMP
 216 #define smp_mb()        mb()
 217 #define smp_rmb()       rmb()
 218 #define smp_wmb()       wmb()
 219 #define smp_read_barrier_depends()      do {} while(0)
 220 #else
 221 #define smp_mb()        barrier()
 222 #define smp_rmb()       barrier()
 223 #define smp_wmb()       barrier()
 224 #define smp_read_barrier_depends()      do {} while(0)
 225 #endif
 226
 227
 228 /*
 229  * Force strict CPU ordering.
 230  * And yes, this is required on UP too when we're talking
 231  * to devices.
 232  */
 233 #define mb()    asm volatile("mfence":::"memory")
 234 #define rmb()   asm volatile("lfence":::"memory")
 235
 236 #ifdef CONFIG_UNORDERED_IO
 237 #define wmb()   asm volatile("sfence" ::: "memory")
 238 #else
 239 #define wmb()   asm volatile("" ::: "memory")
 240 #endif
 241 #define read_barrier_depends()  do {} while(0)
 242 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 243 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 244
 245 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 246
 247 #include <linux/irqflags.h>
 248
 249 void cpu_idle_wait(void);
 250
 251 extern unsigned long arch_align_stack(unsigned long sp);
 252 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 253
 254 #endif