include/drm/exynos_drm.h

   1 /* exynos_drm.h
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  * Authors:
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *      Seung-Woo Kim <sw0312.kim@samsung.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  26  * OTHER DEALINGS IN THE SOFTWARE.
  27  */
  28
  29 #ifndef _EXYNOS_DRM_H_
  30 #define _EXYNOS_DRM_H_
  31
  32 #include "drm.h"
  33
  34 /**
  35  * User-desired buffer creation information structure.
  36  *
  37  * @size: user-desired memory allocation size.
  38  *      - this size value would be page-aligned internally.
  39  * @flags: user request for setting memory type or cache attributes.
  40  * @handle: returned a handle to created gem object.
  41  *      - this handle will be set by gem module of kernel side.
  42  */
  43 struct drm_exynos_gem_create {
  44         uint64_t size;
  45         unsigned int flags;
  46         unsigned int handle;
  47 };
  48
  49 /**
  50  * A structure for getting buffer offset.
  51  *
  52  * @handle: a pointer to gem object created.
  53  * @pad: just padding to be 64-bit aligned.
  54  * @offset: relatived offset value of the memory region allocated.
  55  *      - this value should be set by user.
  56  */
  57 struct drm_exynos_gem_map_off {
  58         unsigned int handle;
  59         unsigned int pad;
  60         uint64_t offset;
  61 };
  62
  63 /**
  64  * A structure for mapping buffer.
  65  *
  66  * @handle: a handle to gem object created.
  67  * @size: memory size to be mapped.
  68  * @mapped: having user virtual address mmaped.
  69  *      - this variable would be filled by exynos gem module
  70  *      of kernel side with user virtual address which is allocated
  71  *      by do_mmap().
  72  */
  73 struct drm_exynos_gem_mmap {
  74         unsigned int handle;
  75         unsigned int size;
  76         uint64_t mapped;
  77 };
  78
  79 /**
  80  * A structure to gem information.
  81  *
  82  * @handle: a handle to gem object created.
  83  * @flags: flag value including memory type and cache attribute and
  84  *      this value would be set by driver.
  85  * @size: size to memory region allocated by gem and this size would
  86  *      be set by driver.
  87  */
  88 struct drm_exynos_gem_info {
  89         unsigned int handle;
  90         unsigned int flags;
  91         uint64_t size;
  92 };
  93
  94 /**
  95  * A structure for user connection request of virtual display.
  96  *
  97  * @connection: indicate whether doing connetion or not by user.
  98  * @extensions: if this value is 1 then the vidi driver would need additional
  99  *      128bytes edid data.
 100  * @edid: the edid data pointer from user side.
 101  */
 102 struct drm_exynos_vidi_connection {
 103         unsigned int connection;
 104         unsigned int extensions;
 105         uint64_t edid;
 106 };
 107
 108 struct drm_exynos_plane_set_zpos {
 109         __u32 plane_id;
 110         __s32 zpos;
 111 };
 112
 113 /* memory type definitions. */
 114 enum e_drm_exynos_gem_mem_type {
 115         /* Physically Continuous memory and used as default. */
 116         EXYNOS_BO_CONTIG        = 0 << 0,
 117         /* Physically Non-Continuous memory. */
 118         EXYNOS_BO_NONCONTIG     = 1 << 0,
 119         /* non-cachable mapping and used as default. */
 120         EXYNOS_BO_NONCACHABLE   = 0 << 1,
 121         /* cachable mapping. */
 122         EXYNOS_BO_CACHABLE      = 1 << 1,
 123         /* write-combine mapping. */
 124         EXYNOS_BO_WC            = 1 << 2,
 125         EXYNOS_BO_MASK          = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
 126                                         EXYNOS_BO_WC
 127 };
 128
 129 struct drm_exynos_g2d_get_ver {
 130         __u32   major;
 131         __u32   minor;
 132 };
 133
 134 struct drm_exynos_g2d_cmd {
 135         __u32   offset;
 136         __u32   data;
 137 };
 138
 139 enum drm_exynos_g2d_event_type {
 140         G2D_EVENT_NOT,
 141         G2D_EVENT_NONSTOP,
 142         G2D_EVENT_STOP,         /* not yet */
 143 };
 144
 145 struct drm_exynos_g2d_set_cmdlist {
 146         __u64                                   cmd;
 147         __u64                                   cmd_gem;
 148         __u32                                   cmd_nr;
 149         __u32                                   cmd_gem_nr;
 150
 151         /* for g2d event */
 152         __u64                                   event_type;
 153         __u64                                   user_data;
 154 };
 155
 156 struct drm_exynos_g2d_exec {
 157         __u64                                   async;
 158 };
 159
 160 #define DRM_EXYNOS_GEM_CREATE           0x00
 161 #define DRM_EXYNOS_GEM_MAP_OFFSET       0x01
 162 #define DRM_EXYNOS_GEM_MMAP             0x02
 163 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
 164 #define DRM_EXYNOS_GEM_GET              0x04
 165 #define DRM_EXYNOS_PLANE_SET_ZPOS       0x06
 166 #define DRM_EXYNOS_VIDI_CONNECTION      0x07
 167
 168 /* G2D */
 169 #define DRM_EXYNOS_G2D_GET_VER          0x20
 170 #define DRM_EXYNOS_G2D_SET_CMDLIST      0x21
 171 #define DRM_EXYNOS_G2D_EXEC             0x22
 172
 173 #define DRM_IOCTL_EXYNOS_GEM_CREATE             DRM_IOWR(DRM_COMMAND_BASE + \
 174                 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
 175
 176 #define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
 177                 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
 178
 179 #define DRM_IOCTL_EXYNOS_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + \
 180                 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
 181
 182 #define DRM_IOCTL_EXYNOS_GEM_GET        DRM_IOWR(DRM_COMMAND_BASE + \
 183                 DRM_EXYNOS_GEM_GET,     struct drm_exynos_gem_info)
 184
 185 #define DRM_IOCTL_EXYNOS_PLANE_SET_ZPOS DRM_IOWR(DRM_COMMAND_BASE + \
 186                 DRM_EXYNOS_PLANE_SET_ZPOS, struct drm_exynos_plane_set_zpos)
 187
 188 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION        DRM_IOWR(DRM_COMMAND_BASE + \
 189                 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
 190
 191 #define DRM_IOCTL_EXYNOS_G2D_GET_VER            DRM_IOWR(DRM_COMMAND_BASE + \
 192                 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
 193 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST        DRM_IOWR(DRM_COMMAND_BASE + \
 194                 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
 195 #define DRM_IOCTL_EXYNOS_G2D_EXEC               DRM_IOWR(DRM_COMMAND_BASE + \
 196                 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
 197
 198 /* EXYNOS specific events */
 199 #define DRM_EXYNOS_G2D_EVENT            0x80000000
 200
 201 struct drm_exynos_g2d_event {
 202         struct drm_event        base;
 203         __u64                   user_data;
 204         __u32                   tv_sec;
 205         __u32                   tv_usec;
 206         __u32                   cmdlist_no;
 207         __u32                   reserved;
 208 };
 209
 210 #ifdef __KERNEL__
 211
 212 /**
 213  * A structure for lcd panel information.
 214  *
 215  * @timing: default video mode for initializing
 216  * @width_mm: physical size of lcd width.
 217  * @height_mm: physical size of lcd height.
 218  */
 219 struct exynos_drm_panel_info {
 220         struct fb_videomode timing;
 221         u32 width_mm;
 222         u32 height_mm;
 223 };
 224
 225 /**
 226  * Platform Specific Structure for DRM based FIMD.
 227  *
 228  * @panel: default panel info for initializing
 229  * @default_win: default window layer number to be used for UI.
 230  * @bpp: default bit per pixel.
 231  */
 232 struct exynos_drm_fimd_pdata {
 233         struct exynos_drm_panel_info panel;
 234         u32                             vidcon0;
 235         u32                             vidcon1;
 236         unsigned int                    default_win;
 237         unsigned int                    bpp;
 238 };
 239
 240 /**
 241  * Platform Specific Structure for DRM based HDMI.
 242  *
 243  * @hdmi_dev: device point to specific hdmi driver.
 244  * @mixer_dev: device point to specific mixer driver.
 245  *
 246  * this structure is used for common hdmi driver and each device object
 247  * would be used to access specific device driver(hdmi or mixer driver)
 248  */
 249 struct exynos_drm_common_hdmi_pd {
 250         struct device *hdmi_dev;
 251         struct device *mixer_dev;
 252 };
 253
 254 /**
 255  * Platform Specific Structure for DRM based HDMI core.
 256  *
 257  * @is_v13: set if hdmi version 13 is.
 258  * @cfg_hpd: function pointer to configure hdmi hotplug detection pin
 259  * @get_hpd: function pointer to get value of hdmi hotplug detection pin
 260  */
 261 struct exynos_drm_hdmi_pdata {
 262         bool is_v13;
 263         void (*cfg_hpd)(bool external);
 264         int (*get_hpd)(void);
 265 };
 266
 267 #endif  /* __KERNEL__ */
 268 #endif  /* _EXYNOS_DRM_H_ */