1 /* i386-opcode.h -- Intel 80386 opcode table
2 Copyright (C) 1989, 1991, Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 1, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 static const template i386_optab
[] = {
25 /* move instructions */
26 { "mov", 2, 0xa0, _
, DW
|NoModrm
, Disp32
, Acc
, 0 },
27 { "mov", 2, 0x88, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0 },
28 { "mov", 2, 0xb0, _
, ShortFormW
, Imm
, Reg
, 0 },
29 { "mov", 2, 0xc6, _
, W
|Modrm
, Imm
, Reg
|Mem
, 0 },
30 { "mov", 2, 0x8c, _
, D
|Modrm
, SReg3
|SReg2
, Reg16
|Mem16
, 0 },
31 /* move to/from control debug registers */
32 { "mov", 2, 0x0f20, _
, D
|Modrm
, Control
, Reg32
, 0},
33 { "mov", 2, 0x0f21, _
, D
|Modrm
, Debug
, Reg32
, 0},
34 { "mov", 2, 0x0f24, _
, D
|Modrm
, Test
, Reg32
, 0},
36 /* move with sign extend */
37 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
38 conflict with the "movs" string move instruction. Thus,
39 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
40 is not kosher; we must seperate the two instructions. */
41 {"movsbl", 2, 0x0fbe, _
, ReverseRegRegmem
|Modrm
, Reg8
|Mem
, Reg32
, 0},
42 {"movsbw", 2, 0x660fbe, _
, ReverseRegRegmem
|Modrm
, Reg8
|Mem
, Reg16
, 0},
43 {"movswl", 2, 0x0fbf, _
, ReverseRegRegmem
|Modrm
, Reg16
|Mem
, Reg32
, 0},
45 /* move with zero extend */
46 {"movzb", 2, 0x0fb6, _
, ReverseRegRegmem
|Modrm
, Reg8
|Mem
, Reg16
|Reg32
, 0},
47 {"movzwl", 2, 0x0fb7, _
, ReverseRegRegmem
|Modrm
, Reg16
|Mem
, Reg32
, 0},
49 /* push instructions */
50 {"push", 1, 0x50, _
, ShortForm
, WordReg
,0,0 },
51 {"push", 1, 0xff, 0x6, Modrm
, WordReg
|WordMem
, 0, 0 },
52 {"push", 1, 0x6a, _
, NoModrm
, Imm8S
, 0, 0},
53 {"push", 1, 0x68, _
, NoModrm
, Imm32
, 0, 0},
54 {"push", 1, 0x06, _
, Seg2ShortForm
, SReg2
,0,0 },
55 {"push", 1, 0x0fa0, _
, Seg3ShortForm
, SReg3
,0,0 },
57 {"pusha", 0, 0x60, _
, NoModrm
, 0, 0, 0 },
59 /* pop instructions */
60 {"pop", 1, 0x58, _
, ShortForm
, WordReg
,0,0 },
61 {"pop", 1, 0x8f, 0x0, Modrm
, WordReg
|WordMem
, 0, 0 },
62 #define POP_SEG_SHORT 0x7
63 {"pop", 1, 0x07, _
, Seg2ShortForm
, SReg2
,0,0 },
64 {"pop", 1, 0x0fa1, _
, Seg3ShortForm
, SReg3
,0,0 },
66 {"popa", 0, 0x61, _
, NoModrm
, 0, 0, 0 },
68 /* xchg exchange instructions
69 xchg commutes: we allow both operand orders */
70 {"xchg", 2, 0x90, _
, ShortForm
, WordReg
, Acc
, 0 },
71 {"xchg", 2, 0x90, _
, ShortForm
, Acc
, WordReg
, 0 },
72 {"xchg", 2, 0x86, _
, W
|Modrm
, Reg
, Reg
|Mem
, 0 },
73 {"xchg", 2, 0x86, _
, W
|Modrm
, Reg
|Mem
, Reg
, 0 },
75 /* in/out from ports */
76 {"in", 2, 0xe4, _
, W
|NoModrm
, Imm8
, Acc
, 0 },
77 {"in", 2, 0xec, _
, W
|NoModrm
, InOutPortReg
, Acc
, 0 },
78 {"out", 2, 0xe6, _
, W
|NoModrm
, Acc
, Imm8
, 0 },
79 {"out", 2, 0xee, _
, W
|NoModrm
, Acc
, InOutPortReg
, 0 },
81 /* load effective address */
82 {"lea", 2, 0x8d, _
, Modrm
, WordMem
, WordReg
, 0 },
84 /* load segment registers from memory */
85 {"lds", 2, 0xc5, _
, Modrm
, Mem
, Reg32
, 0},
86 {"les", 2, 0xc4, _
, Modrm
, Mem
, Reg32
, 0},
87 {"lfs", 2, 0x0fb4, _
, Modrm
, Mem
, Reg32
, 0},
88 {"lgs", 2, 0x0fb5, _
, Modrm
, Mem
, Reg32
, 0},
89 {"lss", 2, 0x0fb2, _
, Modrm
, Mem
, Reg32
, 0},
91 /* flags register instructions */
92 {"clc", 0, 0xf8, _
, NoModrm
, 0, 0, 0},
93 {"cld", 0, 0xfc, _
, NoModrm
, 0, 0, 0},
94 {"cli", 0, 0xfa, _
, NoModrm
, 0, 0, 0},
95 {"clts", 0, 0x0f06, _
, NoModrm
, 0, 0, 0},
96 {"cmc", 0, 0xf5, _
, NoModrm
, 0, 0, 0},
97 {"lahf", 0, 0x9f, _
, NoModrm
, 0, 0, 0},
98 {"sahf", 0, 0x9e, _
, NoModrm
, 0, 0, 0},
99 {"pushf", 0, 0x9c, _
, NoModrm
, 0, 0, 0},
100 {"popf", 0, 0x9d, _
, NoModrm
, 0, 0, 0},
101 {"stc", 0, 0xf9, _
, NoModrm
, 0, 0, 0},
102 {"std", 0, 0xfd, _
, NoModrm
, 0, 0, 0},
103 {"sti", 0, 0xfb, _
, NoModrm
, 0, 0, 0},
105 {"add", 2, 0x0, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
106 {"add", 2, 0x83, 0, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
107 {"add", 2, 0x4, _
, W
|NoModrm
, Imm
, Acc
, 0},
108 {"add", 2, 0x80, 0, W
|Modrm
, Imm
, Reg
|Mem
, 0},
110 {"inc", 1, 0x40, _
, ShortForm
, WordReg
, 0, 0},
111 {"inc", 1, 0xfe, 0, W
|Modrm
, Reg
|Mem
, 0, 0},
113 {"sub", 2, 0x28, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
114 {"sub", 2, 0x83, 5, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
115 {"sub", 2, 0x2c, _
, W
|NoModrm
, Imm
, Acc
, 0},
116 {"sub", 2, 0x80, 5, W
|Modrm
, Imm
, Reg
|Mem
, 0},
118 {"dec", 1, 0x48, _
, ShortForm
, WordReg
, 0, 0},
119 {"dec", 1, 0xfe, 1, W
|Modrm
, Reg
|Mem
, 0, 0},
121 {"sbb", 2, 0x18, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
122 {"sbb", 2, 0x83, 3, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
123 {"sbb", 2, 0x1c, _
, W
|NoModrm
, Imm
, Acc
, 0},
124 {"sbb", 2, 0x80, 3, W
|Modrm
, Imm
, Reg
|Mem
, 0},
126 {"cmp", 2, 0x38, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
127 {"cmp", 2, 0x83, 7, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
128 {"cmp", 2, 0x3c, _
, W
|NoModrm
, Imm
, Acc
, 0},
129 {"cmp", 2, 0x80, 7, W
|Modrm
, Imm
, Reg
|Mem
, 0},
131 {"test", 2, 0x84, _
, W
|Modrm
, Reg
|Mem
, Reg
, 0},
132 {"test", 2, 0x84, _
, W
|Modrm
, Reg
, Reg
|Mem
, 0},
133 {"test", 2, 0xa8, _
, W
|NoModrm
, Imm
, Acc
, 0},
134 {"test", 2, 0xf6, 0, W
|Modrm
, Imm
, Reg
|Mem
, 0},
136 {"and", 2, 0x20, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
137 {"and", 2, 0x83, 4, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
138 {"and", 2, 0x24, _
, W
|NoModrm
, Imm
, Acc
, 0},
139 {"and", 2, 0x80, 4, W
|Modrm
, Imm
, Reg
|Mem
, 0},
141 {"or", 2, 0x08, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
142 {"or", 2, 0x83, 1, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
143 {"or", 2, 0x0c, _
, W
|NoModrm
, Imm
, Acc
, 0},
144 {"or", 2, 0x80, 1, W
|Modrm
, Imm
, Reg
|Mem
, 0},
146 {"xor", 2, 0x30, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
147 {"xor", 2, 0x83, 6, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
148 {"xor", 2, 0x34, _
, W
|NoModrm
, Imm
, Acc
, 0},
149 {"xor", 2, 0x80, 6, W
|Modrm
, Imm
, Reg
|Mem
, 0},
151 {"adc", 2, 0x10, _
, DW
|Modrm
, Reg
, Reg
|Mem
, 0},
152 {"adc", 2, 0x83, 2, Modrm
, Imm8S
, WordReg
|WordMem
, 0},
153 {"adc", 2, 0x14, _
, W
|NoModrm
, Imm
, Acc
, 0},
154 {"adc", 2, 0x80, 2, W
|Modrm
, Imm
, Reg
|Mem
, 0},
156 {"neg", 1, 0xf6, 3, W
|Modrm
, Reg
|Mem
, 0, 0},
157 {"not", 1, 0xf6, 2, W
|Modrm
, Reg
|Mem
, 0, 0},
159 {"aaa", 0, 0x37, _
, NoModrm
, 0, 0, 0},
160 {"aas", 0, 0x3f, _
, NoModrm
, 0, 0, 0},
161 {"daa", 0, 0x27, _
, NoModrm
, 0, 0, 0},
162 {"das", 0, 0x2f, _
, NoModrm
, 0, 0, 0},
163 {"aad", 0, 0xd50a, _
, NoModrm
, 0, 0, 0},
164 {"aam", 0, 0xd40a, _
, NoModrm
, 0, 0, 0},
166 /* conversion insns */
167 /* conversion: intel naming */
168 {"cbw", 0, 0x6698, _
, NoModrm
, 0, 0, 0},
169 {"cwd", 0, 0x6699, _
, NoModrm
, 0, 0, 0},
170 {"cwde", 0, 0x98, _
, NoModrm
, 0, 0, 0},
171 {"cdq", 0, 0x99, _
, NoModrm
, 0, 0, 0},
173 {"cbtw", 0, 0x6698, _
, NoModrm
, 0, 0, 0},
174 {"cwtl", 0, 0x98, _
, NoModrm
, 0, 0, 0},
175 {"cwtd", 0, 0x6699, _
, NoModrm
, 0, 0, 0},
176 {"cltd", 0, 0x99, _
, NoModrm
, 0, 0, 0},
178 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
179 expanding 64-bit multiplies, and *cannot* be selected to accomplish
180 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
181 These multiplies can only be selected with single opearnd forms. */
182 {"mul", 1, 0xf6, 4, W
|Modrm
, Reg
|Mem
, 0, 0},
183 {"imul", 1, 0xf6, 5, W
|Modrm
, Reg
|Mem
, 0, 0},
188 /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
189 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
190 '%eax' in the reg field and '%ecx' in the regmem field if we did not
192 {"imul", 2, 0x0faf, _
, Modrm
|ReverseRegRegmem
, WordReg
|Mem
, WordReg
, 0},
193 {"imul", 3, 0x6b, _
, Modrm
|ReverseRegRegmem
, Imm8S
, WordReg
|Mem
, WordReg
},
194 {"imul", 3, 0x69, _
, Modrm
|ReverseRegRegmem
, Imm16
|Imm32
, WordReg
|Mem
, WordReg
},
196 imul with 2 operands mimicks imul with 3 by puting register both
197 in i.rm.reg & i.rm.regmem fields
199 {"imul", 2, 0x6b, _
, Modrm
|imulKludge
, Imm8S
, WordReg
, 0},
200 {"imul", 2, 0x69, _
, Modrm
|imulKludge
, Imm16
|Imm32
, WordReg
, 0},
201 {"div", 1, 0xf6, 6, W
|Modrm
, Reg
|Mem
, 0, 0},
202 {"div", 2, 0xf6, 6, W
|Modrm
, Reg
|Mem
, Acc
, 0},
203 {"idiv", 1, 0xf6, 7, W
|Modrm
, Reg
|Mem
, 0, 0},
204 {"idiv", 2, 0xf6, 7, W
|Modrm
, Reg
|Mem
, Acc
, 0},
206 {"rol", 2, 0xd0, 0, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
207 {"rol", 2, 0xc0, 0, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
208 {"rol", 2, 0xd2, 0, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
209 {"rol", 1, 0xd0, 0, W
|Modrm
, Reg
|Mem
, 0, 0},
211 {"ror", 2, 0xd0, 1, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
212 {"ror", 2, 0xc0, 1, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
213 {"ror", 2, 0xd2, 1, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
214 {"ror", 1, 0xd0, 1, W
|Modrm
, Reg
|Mem
, 0, 0},
216 {"rcl", 2, 0xd0, 2, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
217 {"rcl", 2, 0xc0, 2, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
218 {"rcl", 2, 0xd2, 2, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
219 {"rcl", 1, 0xd0, 2, W
|Modrm
, Reg
|Mem
, 0, 0},
221 {"rcr", 2, 0xd0, 3, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
222 {"rcr", 2, 0xc0, 3, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
223 {"rcr", 2, 0xd2, 3, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
224 {"rcr", 1, 0xd0, 3, W
|Modrm
, Reg
|Mem
, 0, 0},
226 {"sal", 2, 0xd0, 4, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
227 {"sal", 2, 0xc0, 4, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
228 {"sal", 2, 0xd2, 4, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
229 {"sal", 1, 0xd0, 4, W
|Modrm
, Reg
|Mem
, 0, 0},
230 {"shl", 2, 0xd0, 4, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
231 {"shl", 2, 0xc0, 4, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
232 {"shl", 2, 0xd2, 4, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
233 {"shl", 1, 0xd0, 4, W
|Modrm
, Reg
|Mem
, 0, 0},
235 {"shld", 3, 0x0fa4, _
, Modrm
, Imm8
, WordReg
, WordReg
|Mem
},
236 {"shld", 3, 0x0fa5, _
, Modrm
, ShiftCount
, WordReg
, WordReg
|Mem
},
238 {"shr", 2, 0xd0, 5, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
239 {"shr", 2, 0xc0, 5, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
240 {"shr", 2, 0xd2, 5, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
241 {"shr", 1, 0xd0, 5, W
|Modrm
, Reg
|Mem
, 0, 0},
243 {"shrd", 3, 0x0fac, _
, Modrm
, Imm8
, WordReg
, WordReg
|Mem
},
244 {"shrd", 3, 0x0fad, _
, Modrm
, ShiftCount
, WordReg
, WordReg
|Mem
},
246 {"sar", 2, 0xd0, 7, W
|Modrm
, Imm1
, Reg
|Mem
, 0},
247 {"sar", 2, 0xc0, 7, W
|Modrm
, Imm8
, Reg
|Mem
, 0},
248 {"sar", 2, 0xd2, 7, W
|Modrm
, ShiftCount
, Reg
|Mem
, 0},
249 {"sar", 1, 0xd0, 7, W
|Modrm
, Reg
|Mem
, 0, 0},
251 /* control transfer instructions */
252 #define CALL_PC_RELATIVE 0xe8
253 {"call", 1, 0xe8, _
, JumpDword
, Disp32
, 0, 0},
254 {"call", 1, 0xff, 2, Modrm
, Reg
|Mem
|JumpAbsolute
, 0, 0},
255 #define CALL_FAR_IMMEDIATE 0x9a
256 {"lcall", 2, 0x9a, _
, JumpInterSegment
, Imm16
, Abs32
, 0},
257 {"lcall", 1, 0xff, 3, Modrm
, Mem
, 0, 0},
259 #define JUMP_PC_RELATIVE 0xeb
260 {"jmp", 1, 0xeb, _
, Jump
, Disp
, 0, 0},
261 {"jmp", 1, 0xff, 4, Modrm
, Reg32
|Mem
|JumpAbsolute
, 0, 0},
262 #define JUMP_FAR_IMMEDIATE 0xea
263 {"ljmp", 2, 0xea, _
, JumpInterSegment
, Imm16
, Imm32
, 0},
264 {"ljmp", 1, 0xff, 5, Modrm
, Mem
, 0, 0},
266 {"ret", 0, 0xc3, _
, NoModrm
, 0, 0, 0},
267 {"ret", 1, 0xc2, _
, NoModrm
, Imm16
, 0, 0},
268 {"lret", 0, 0xcb, _
, NoModrm
, 0, 0, 0},
269 {"lret", 1, 0xca, _
, NoModrm
, Imm16
, 0, 0},
270 {"enter", 2, 0xc8, _
, NoModrm
, Imm16
, Imm8
, 0},
271 {"leave", 0, 0xc9, _
, NoModrm
, 0, 0, 0},
273 /* conditional jumps */
274 {"jo", 1, 0x70, _
, Jump
, Disp
, 0, 0},
276 {"jno", 1, 0x71, _
, Jump
, Disp
, 0, 0},
278 {"jb", 1, 0x72, _
, Jump
, Disp
, 0, 0},
279 {"jc", 1, 0x72, _
, Jump
, Disp
, 0, 0},
280 {"jnae", 1, 0x72, _
, Jump
, Disp
, 0, 0},
282 {"jnb", 1, 0x73, _
, Jump
, Disp
, 0, 0},
283 {"jnc", 1, 0x73, _
, Jump
, Disp
, 0, 0},
284 {"jae", 1, 0x73, _
, Jump
, Disp
, 0, 0},
286 {"je", 1, 0x74, _
, Jump
, Disp
, 0, 0},
287 {"jz", 1, 0x74, _
, Jump
, Disp
, 0, 0},
289 {"jne", 1, 0x75, _
, Jump
, Disp
, 0, 0},
290 {"jnz", 1, 0x75, _
, Jump
, Disp
, 0, 0},
292 {"jbe", 1, 0x76, _
, Jump
, Disp
, 0, 0},
293 {"jna", 1, 0x76, _
, Jump
, Disp
, 0, 0},
295 {"jnbe", 1, 0x77, _
, Jump
, Disp
, 0, 0},
296 {"ja", 1, 0x77, _
, Jump
, Disp
, 0, 0},
298 {"js", 1, 0x78, _
, Jump
, Disp
, 0, 0},
300 {"jns", 1, 0x79, _
, Jump
, Disp
, 0, 0},
302 {"jp", 1, 0x7a, _
, Jump
, Disp
, 0, 0},
303 {"jpe", 1, 0x7a, _
, Jump
, Disp
, 0, 0},
305 {"jnp", 1, 0x7b, _
, Jump
, Disp
, 0, 0},
306 {"jpo", 1, 0x7b, _
, Jump
, Disp
, 0, 0},
308 {"jl", 1, 0x7c, _
, Jump
, Disp
, 0, 0},
309 {"jnge", 1, 0x7c, _
, Jump
, Disp
, 0, 0},
311 {"jnl", 1, 0x7d, _
, Jump
, Disp
, 0, 0},
312 {"jge", 1, 0x7d, _
, Jump
, Disp
, 0, 0},
314 {"jle", 1, 0x7e, _
, Jump
, Disp
, 0, 0},
315 {"jng", 1, 0x7e, _
, Jump
, Disp
, 0, 0},
317 {"jnle", 1, 0x7f, _
, Jump
, Disp
, 0, 0},
318 {"jg", 1, 0x7f, _
, Jump
, Disp
, 0, 0},
320 /* these turn into pseudo operations when disp is larger than 8 bits */
321 #define IS_JUMP_ON_CX_ZERO(o) \
323 #define IS_JUMP_ON_ECX_ZERO(o) \
326 {"jcxz", 1, 0x67e3, _
, JumpByte
, Disp
, 0, 0},
327 {"jecxz", 1, 0xe3, _
, JumpByte
, Disp
, 0, 0},
329 #define IS_LOOP_ECX_TIMES(o) \
330 (o == 0xe2 || o == 0xe1 || o == 0xe0)
332 {"loop", 1, 0xe2, _
, JumpByte
, Disp
, 0, 0},
334 {"loopz", 1, 0xe1, _
, JumpByte
, Disp
, 0, 0},
335 {"loope", 1, 0xe1, _
, JumpByte
, Disp
, 0, 0},
337 {"loopnz", 1, 0xe0, _
, JumpByte
, Disp
, 0, 0},
338 {"loopne", 1, 0xe0, _
, JumpByte
, Disp
, 0, 0},
340 /* set byte on flag instructions */
341 {"seto", 1, 0x0f90, 0, Modrm
, Reg8
|Mem
, 0, 0},
343 {"setno", 1, 0x0f91, 0, Modrm
, Reg8
|Mem
, 0, 0},
345 {"setb", 1, 0x0f92, 0, Modrm
, Reg8
|Mem
, 0, 0},
346 {"setnae", 1, 0x0f92, 0, Modrm
, Reg8
|Mem
, 0, 0},
348 {"setnb", 1, 0x0f93, 0, Modrm
, Reg8
|Mem
, 0, 0},
349 {"setae", 1, 0x0f93, 0, Modrm
, Reg8
|Mem
, 0, 0},
351 {"sete", 1, 0x0f94, 0, Modrm
, Reg8
|Mem
, 0, 0},
352 {"setz", 1, 0x0f94, 0, Modrm
, Reg8
|Mem
, 0, 0},
354 {"setne", 1, 0x0f95, 0, Modrm
, Reg8
|Mem
, 0, 0},
355 {"setnz", 1, 0x0f95, 0, Modrm
, Reg8
|Mem
, 0, 0},
357 {"setbe", 1, 0x0f96, 0, Modrm
, Reg8
|Mem
, 0, 0},
358 {"setna", 1, 0x0f96, 0, Modrm
, Reg8
|Mem
, 0, 0},
360 {"setnbe", 1, 0x0f97, 0, Modrm
, Reg8
|Mem
, 0, 0},
361 {"seta", 1, 0x0f97, 0, Modrm
, Reg8
|Mem
, 0, 0},
363 {"sets", 1, 0x0f98, 0, Modrm
, Reg8
|Mem
, 0, 0},
365 {"setns", 1, 0x0f99, 0, Modrm
, Reg8
|Mem
, 0, 0},
367 {"setp", 1, 0x0f9a, 0, Modrm
, Reg8
|Mem
, 0, 0},
368 {"setpe", 1, 0x0f9a, 0, Modrm
, Reg8
|Mem
, 0, 0},
370 {"setnp", 1, 0x0f9b, 0, Modrm
, Reg8
|Mem
, 0, 0},
371 {"setpo", 1, 0x0f9b, 0, Modrm
, Reg8
|Mem
, 0, 0},
373 {"setl", 1, 0x0f9c, 0, Modrm
, Reg8
|Mem
, 0, 0},
374 {"setnge", 1, 0x0f9c, 0, Modrm
, Reg8
|Mem
, 0, 0},
376 {"setnl", 1, 0x0f9d, 0, Modrm
, Reg8
|Mem
, 0, 0},
377 {"setge", 1, 0x0f9d, 0, Modrm
, Reg8
|Mem
, 0, 0},
379 {"setle", 1, 0x0f9e, 0, Modrm
, Reg8
|Mem
, 0, 0},
380 {"setng", 1, 0x0f9e, 0, Modrm
, Reg8
|Mem
, 0, 0},
382 {"setnle", 1, 0x0f9f, 0, Modrm
, Reg8
|Mem
, 0, 0},
383 {"setg", 1, 0x0f9f, 0, Modrm
, Reg8
|Mem
, 0, 0},
385 #define IS_STRING_INSTRUCTION(o) \
386 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
387 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
390 /* string manipulation */
391 {"cmps", 0, 0xa6, _
, W
|NoModrm
, 0, 0, 0},
392 {"ins", 0, 0x6c, _
, W
|NoModrm
, 0, 0, 0},
393 {"outs", 0, 0x6e, _
, W
|NoModrm
, 0, 0, 0},
394 {"lods", 0, 0xac, _
, W
|NoModrm
, 0, 0, 0},
395 {"movs", 0, 0xa4, _
, W
|NoModrm
, 0, 0, 0},
396 {"scas", 0, 0xae, _
, W
|NoModrm
, 0, 0, 0},
397 {"stos", 0, 0xaa, _
, W
|NoModrm
, 0, 0, 0},
398 {"xlat", 0, 0xd7, _
, NoModrm
, 0, 0, 0},
400 /* bit manipulation */
401 {"bsf", 2, 0x0fbc, _
, Modrm
|ReverseRegRegmem
, Reg
|Mem
, Reg
, 0},
402 {"bsr", 2, 0x0fbd, _
, Modrm
|ReverseRegRegmem
, Reg
|Mem
, Reg
, 0},
403 {"bt", 2, 0x0fa3, _
, Modrm
, Reg
, Reg
|Mem
, 0},
404 {"bt", 2, 0x0fba, 4, Modrm
, Imm8
, Reg
|Mem
, 0},
405 {"btc", 2, 0x0fbb, _
, Modrm
, Reg
, Reg
|Mem
, 0},
406 {"btc", 2, 0x0fba, 7, Modrm
, Imm8
, Reg
|Mem
, 0},
407 {"btr", 2, 0x0fb3, _
, Modrm
, Reg
, Reg
|Mem
, 0},
408 {"btr", 2, 0x0fba, 6, Modrm
, Imm8
, Reg
|Mem
, 0},
409 {"bts", 2, 0x0fab, _
, Modrm
, Reg
, Reg
|Mem
, 0},
410 {"bts", 2, 0x0fba, 5, Modrm
, Imm8
, Reg
|Mem
, 0},
412 /* interrupts & op. sys insns */
413 /* See i386.c for conversion of 'int $3' into the special int 3 insn. */
414 #define INT_OPCODE 0xcd
415 #define INT3_OPCODE 0xcc
416 {"int", 1, 0xcd, _
, NoModrm
, Imm8
, 0, 0},
417 {"int3", 0, 0xcc, _
, NoModrm
, 0, 0, 0},
418 {"into", 0, 0xce, _
, NoModrm
, 0, 0, 0},
419 {"iret", 0, 0xcf, _
, NoModrm
, 0, 0, 0},
421 {"boundl", 2, 0x62, _
, Modrm
, Reg32
, Mem
, 0},
422 {"boundw", 2, 0x6662, _
, Modrm
, Reg16
, Mem
, 0},
424 {"hlt", 0, 0xf4, _
, NoModrm
, 0, 0, 0},
425 {"wait", 0, 0x9b, _
, NoModrm
, 0, 0, 0},
426 /* nop is actually 'xchgl %eax, %eax' */
427 {"nop", 0, 0x90, _
, NoModrm
, 0, 0, 0},
429 /* protection control */
430 {"arpl", 2, 0x63, _
, Modrm
, Reg16
, Reg16
|Mem
, 0},
431 {"lar", 2, 0x0f02, _
, Modrm
|ReverseRegRegmem
, WordReg
|Mem
, WordReg
, 0},
432 {"lgdt", 1, 0x0f01, 2, Modrm
, Mem
, 0, 0},
433 {"lidt", 1, 0x0f01, 3, Modrm
, Mem
, 0, 0},
434 {"lldt", 1, 0x0f00, 2, Modrm
, WordReg
|Mem
, 0, 0},
435 {"lmsw", 1, 0x0f01, 6, Modrm
, WordReg
|Mem
, 0, 0},
436 {"lsl", 2, 0x0f03, _
, Modrm
|ReverseRegRegmem
, WordReg
|Mem
, WordReg
, 0},
437 {"ltr", 1, 0x0f00, 3, Modrm
, WordReg
|Mem
, 0, 0},
439 {"sgdt", 1, 0x0f01, 0, Modrm
, Mem
, 0, 0},
440 {"sidt", 1, 0x0f01, 1, Modrm
, Mem
, 0, 0},
441 {"sldt", 1, 0x0f00, 0, Modrm
, WordReg
|Mem
, 0, 0},
442 {"smsw", 1, 0x0f01, 4, Modrm
, WordReg
|Mem
, 0, 0},
443 {"str", 1, 0x0f00, 1, Modrm
, Reg16
|Mem
, 0, 0},
445 {"verr", 1, 0x0f00, 4, Modrm
, WordReg
|Mem
, 0, 0},
446 {"verw", 1, 0x0f00, 5, Modrm
, WordReg
|Mem
, 0, 0},
448 /* floating point instructions */
451 {"fld", 1, 0xd9c0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
452 {"flds", 1, 0xd9, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem float */
453 {"fildl", 1, 0xdb, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem word */
454 {"fldl", 1, 0xdd, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem double */
455 {"fldl", 1, 0xd9c0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
456 {"filds", 1, 0xdf, 0, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem dword */
457 {"fildq", 1, 0xdf, 5, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem qword */
458 {"fldt", 1, 0xdb, 5, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem efloat */
459 {"fbld", 1, 0xdf, 4, Modrm
, Mem
, 0, 0}, /* %st0 <-- mem bcd */
462 {"fst", 1, 0xddd0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
463 {"fsts", 1, 0xd9, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem float */
464 {"fistl", 1, 0xdb, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem dword */
465 {"fstl", 1, 0xdd, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem double */
466 {"fstl", 1, 0xddd0, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
467 {"fists", 1, 0xdf, 2, Modrm
, Mem
, 0, 0}, /* %st0 --> mem word */
469 /* store (with pop) */
470 {"fstp", 1, 0xddd8, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
471 {"fstps", 1, 0xd9, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem float */
472 {"fistpl", 1, 0xdb, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem word */
473 {"fstpl", 1, 0xdd, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem double */
474 {"fstpl", 1, 0xddd8, _
, ShortForm
, FloatReg
, 0, 0}, /* register */
475 {"fistps", 1, 0xdf, 3, Modrm
, Mem
, 0, 0}, /* %st0 --> mem dword */
476 {"fistpq", 1, 0xdf, 7, Modrm
, Mem
, 0, 0}, /* %st0 --> mem qword */
477 {"fstpt", 1, 0xdb, 7, Modrm
, Mem
, 0, 0}, /* %st0 --> mem efloat */
478 {"fbstp", 1, 0xdf, 6, Modrm
, Mem
, 0, 0}, /* %st0 --> mem bcd */
480 /* exchange %st<n> with %st0 */
481 {"fxch", 1, 0xd9c8, _
, ShortForm
, FloatReg
, 0, 0},
483 /* comparison (without pop) */
484 {"fcom", 1, 0xd8d0, _
, ShortForm
, FloatReg
, 0, 0},
485 {"fcoms", 1, 0xd8, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem float */
486 {"ficoml", 1, 0xda, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem word */
487 {"fcoml", 1, 0xdc, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem double */
488 {"fcoml", 1, 0xd8d0, _
, ShortForm
, FloatReg
, 0, 0},
489 {"ficoms", 1, 0xde, 2, Modrm
, Mem
, 0, 0}, /* compare %st0, mem dword */
491 /* comparison (with pop) */
492 {"fcomp", 1, 0xd8d8, _
, ShortForm
, FloatReg
, 0, 0},
493 {"fcomps", 1, 0xd8, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem float */
494 {"ficompl", 1, 0xda, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem word */
495 {"fcompl", 1, 0xdc, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem double */
496 {"fcompl", 1, 0xd8d8, _
, ShortForm
, FloatReg
, 0, 0},
497 {"ficomps", 1, 0xde, 3, Modrm
, Mem
, 0, 0}, /* compare %st0, mem dword */
498 {"fcompp", 0, 0xded9, _
, NoModrm
, 0, 0, 0}, /* compare %st0, %st1 & pop twice */
500 /* unordered comparison (with pop) */
501 {"fucom", 1, 0xdde0, _
, ShortForm
, FloatReg
, 0, 0},
502 {"fucomp", 1, 0xdde8, _
, ShortForm
, FloatReg
, 0, 0},
503 {"fucompp", 0, 0xdae9, _
, NoModrm
, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */
505 {"ftst", 0, 0xd9e4, _
, NoModrm
, 0, 0, 0}, /* test %st0 */
506 {"fxam", 0, 0xd9e5, _
, NoModrm
, 0, 0, 0}, /* examine %st0 */
508 /* load constants into %st0 */
509 {"fld1", 0, 0xd9e8, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- 1.0 */
510 {"fldl2t", 0, 0xd9e9, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- log2(10) */
511 {"fldl2e", 0, 0xd9ea, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- log2(e) */
512 {"fldpi", 0, 0xd9eb, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- pi */
513 {"fldlg2", 0, 0xd9ec, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- log10(2) */
514 {"fldln2", 0, 0xd9ed, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- ln(2) */
515 {"fldz", 0, 0xd9ee, _
, NoModrm
, 0, 0, 0}, /* %st0 <-- 0.0 */
520 {"fadd", 1, 0xd8c0, _
, ShortForm
, FloatReg
, 0, 0},
521 {"fadd", 2, 0xd8c0, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
522 {"fadd", 0, 0xdcc1, _
, NoModrm
, 0, 0, 0}, /* alias for fadd %st, %st(1) */
523 {"faddp", 1, 0xdac0, _
, ShortForm
, FloatReg
, 0, 0},
524 {"faddp", 2, 0xdac0, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
525 {"faddp", 0, 0xdec1, _
, NoModrm
, 0, 0, 0}, /* alias for faddp %st, %st(1) */
526 {"fadds", 1, 0xd8, 0, Modrm
, Mem
, 0, 0},
527 {"fiaddl", 1, 0xda, 0, Modrm
, Mem
, 0, 0},
528 {"faddl", 1, 0xdc, 0, Modrm
, Mem
, 0, 0},
529 {"fiadds", 1, 0xde, 0, Modrm
, Mem
, 0, 0},
532 /* Note: intel has decided that certain of these operations are reversed
533 in assembler syntax. */
534 {"fsub", 1, 0xd8e0, _
, ShortForm
, FloatReg
, 0, 0},
535 {"fsub", 2, 0xd8e0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
536 #ifdef NON_BROKEN_OPCODES
537 {"fsub", 2, 0xdce8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
539 {"fsub", 2, 0xdce0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
541 {"fsub", 0, 0xdce1, _
, NoModrm
, 0, 0, 0},
542 {"fsubp", 1, 0xdae0, _
, ShortForm
, FloatReg
, 0, 0},
543 {"fsubp", 2, 0xdae0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
544 #ifdef NON_BROKEN_OPCODES
545 {"fsubp", 2, 0xdee8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
547 {"fsubp", 2, 0xdee0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
549 {"fsubp", 0, 0xdee1, _
, NoModrm
, 0, 0, 0},
550 {"fsubs", 1, 0xd8, 4, Modrm
, Mem
, 0, 0},
551 {"fisubl", 1, 0xda, 4, Modrm
, Mem
, 0, 0},
552 {"fsubl", 1, 0xdc, 4, Modrm
, Mem
, 0, 0},
553 {"fisubs", 1, 0xde, 4, Modrm
, Mem
, 0, 0},
556 {"fsubr", 1, 0xd8e8, _
, ShortForm
, FloatReg
, 0, 0},
557 {"fsubr", 2, 0xd8e8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
558 #ifdef NON_BROKEN_OPCODES
559 {"fsubr", 2, 0xdce0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
561 {"fsubr", 2, 0xdce8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
563 {"fsubr", 0, 0xdce9, _
, NoModrm
, 0, 0, 0},
564 {"fsubrp", 1, 0xdae8, _
, ShortForm
, FloatReg
, 0, 0},
565 {"fsubrp", 2, 0xdae8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
566 #ifdef NON_BROKEN_OPCODES
567 {"fsubrp", 2, 0xdee0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
569 {"fsubrp", 2, 0xdee8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
571 {"fsubrp", 0, 0xdee9, _
, NoModrm
, 0, 0, 0},
572 {"fsubrs", 1, 0xd8, 5, Modrm
, Mem
, 0, 0},
573 {"fisubrl", 1, 0xda, 5, Modrm
, Mem
, 0, 0},
574 {"fsubrl", 1, 0xdc, 5, Modrm
, Mem
, 0, 0},
575 {"fisubrs", 1, 0xde, 5, Modrm
, Mem
, 0, 0},
578 {"fmul", 1, 0xd8c8, _
, ShortForm
, FloatReg
, 0, 0},
579 {"fmul", 2, 0xd8c8, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
580 {"fmul", 0, 0xdcc9, _
, NoModrm
, 0, 0, 0},
581 {"fmulp", 1, 0xdac8, _
, ShortForm
, FloatReg
, 0, 0},
582 {"fmulp", 2, 0xdac8, _
, ShortForm
|FloatD
, FloatReg
, FloatAcc
, 0},
583 {"fmulp", 0, 0xdec9, _
, NoModrm
, 0, 0, 0},
584 {"fmuls", 1, 0xd8, 1, Modrm
, Mem
, 0, 0},
585 {"fimull", 1, 0xda, 1, Modrm
, Mem
, 0, 0},
586 {"fmull", 1, 0xdc, 1, Modrm
, Mem
, 0, 0},
587 {"fimuls", 1, 0xde, 1, Modrm
, Mem
, 0, 0},
590 /* Note: intel has decided that certain of these operations are reversed
591 in assembler syntax. */
592 {"fdiv", 1, 0xd8f0, _
, ShortForm
, FloatReg
, 0, 0},
593 {"fdiv", 2, 0xd8f0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
594 #ifdef NON_BROKEN_OPCODES
595 {"fdiv", 2, 0xdcf8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
597 {"fdiv", 2, 0xdcf0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
599 {"fdiv", 0, 0xdcf1, _
, NoModrm
, 0, 0, 0},
600 {"fdivp", 1, 0xdaf0, _
, ShortForm
, FloatReg
, 0, 0},
601 {"fdivp", 2, 0xdaf0, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
602 #ifdef NON_BROKEN_OPCODES
603 {"fdivp", 2, 0xdef8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
605 {"fdivp", 2, 0xdef0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
607 {"fdivp", 0, 0xdef1, _
, NoModrm
, 0, 0, 0},
608 {"fdivs", 1, 0xd8, 6, Modrm
, Mem
, 0, 0},
609 {"fidivl", 1, 0xda, 6, Modrm
, Mem
, 0, 0},
610 {"fdivl", 1, 0xdc, 6, Modrm
, Mem
, 0, 0},
611 {"fidivs", 1, 0xde, 6, Modrm
, Mem
, 0, 0},
614 {"fdivr", 1, 0xd8f8, _
, ShortForm
, FloatReg
, 0, 0},
615 {"fdivr", 2, 0xd8f8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
616 #ifdef NON_BROKEN_OPCODES
617 {"fdivr", 2, 0xdcf0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
619 {"fdivr", 2, 0xdcf8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
621 {"fdivr", 0, 0xdcf9, _
, NoModrm
, 0, 0, 0},
622 {"fdivrp", 1, 0xdaf8, _
, ShortForm
, FloatReg
, 0, 0},
623 {"fdivrp", 2, 0xdaf8, _
, ShortForm
, FloatReg
, FloatAcc
, 0},
624 #ifdef NON_BROKEN_OPCODES
625 {"fdivrp", 2, 0xdef0, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
627 {"fdivrp", 2, 0xdef8, _
, ShortForm
, FloatAcc
, FloatReg
, 0},
629 {"fdivrp", 0, 0xdef9, _
, NoModrm
, 0, 0, 0},
630 {"fdivrs", 1, 0xd8, 7, Modrm
, Mem
, 0, 0},
631 {"fidivrl", 1, 0xda, 7, Modrm
, Mem
, 0, 0},
632 {"fdivrl", 1, 0xdc, 7, Modrm
, Mem
, 0, 0},
633 {"fidivrs", 1, 0xde, 7, Modrm
, Mem
, 0, 0},
635 {"f2xm1", 0, 0xd9f0, _
, NoModrm
, 0, 0, 0},
636 {"fyl2x", 0, 0xd9f1, _
, NoModrm
, 0, 0, 0},
637 {"fptan", 0, 0xd9f2, _
, NoModrm
, 0, 0, 0},
638 {"fpatan", 0, 0xd9f3, _
, NoModrm
, 0, 0, 0},
639 {"fxtract", 0, 0xd9f4, _
, NoModrm
, 0, 0, 0},
640 {"fprem1", 0, 0xd9f5, _
, NoModrm
, 0, 0, 0},
641 {"fdecstp", 0, 0xd9f6, _
, NoModrm
, 0, 0, 0},
642 {"fincstp", 0, 0xd9f7, _
, NoModrm
, 0, 0, 0},
643 {"fprem", 0, 0xd9f8, _
, NoModrm
, 0, 0, 0},
644 {"fyl2xp1", 0, 0xd9f9, _
, NoModrm
, 0, 0, 0},
645 {"fsqrt", 0, 0xd9fa, _
, NoModrm
, 0, 0, 0},
646 {"fsincos", 0, 0xd9fb, _
, NoModrm
, 0, 0, 0},
647 {"frndint", 0, 0xd9fc, _
, NoModrm
, 0, 0, 0},
648 {"fscale", 0, 0xd9fd, _
, NoModrm
, 0, 0, 0},
649 {"fsin", 0, 0xd9fe, _
, NoModrm
, 0, 0, 0},
650 {"fcos", 0, 0xd9ff, _
, NoModrm
, 0, 0, 0},
652 {"fchs", 0, 0xd9e0, _
, NoModrm
, 0, 0, 0},
653 {"fabs", 0, 0xd9e1, _
, NoModrm
, 0, 0, 0},
655 /* processor control */
656 {"fninit", 0, 0xdbe3, _
, NoModrm
, 0, 0, 0},
657 {"finit", 0, 0xdbe3, _
, NoModrm
, 0, 0, 0},
658 {"fldcw", 1, 0xd9, 5, Modrm
, Mem
, 0, 0},
659 {"fnstcw", 1, 0xd9, 7, Modrm
, Mem
, 0, 0},
660 {"fstcw", 1, 0xd9, 7, Modrm
, Mem
, 0, 0},
661 {"fnstsw", 1, 0xdfe0, _
, NoModrm
, Acc
, 0, 0},
662 {"fnstsw", 1, 0xdd, 7, Modrm
, Mem
, 0, 0},
663 {"fnstsw", 0, 0xdfe0, _
, NoModrm
, 0, 0, 0},
664 {"fstsw", 1, 0xdfe0, _
, NoModrm
, Acc
, 0, 0},
665 {"fstsw", 1, 0xdd, 7, Modrm
, Mem
, 0, 0},
666 {"fstsw", 0, 0xdfe0, _
, NoModrm
, 0, 0, 0},
667 {"fnclex", 0, 0xdbe2, _
, NoModrm
, 0, 0, 0},
668 {"fclex", 0, 0xdbe2, _
, NoModrm
, 0, 0, 0},
670 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
671 instructions; i'm not sure how to add them or how they are different.
672 My 386/387 book offers no details about this.
674 {"fnstenv", 1, 0xd9, 6, Modrm
, Mem
, 0, 0},
675 {"fstenv", 1, 0xd9, 6, Modrm
, Mem
, 0, 0},
676 {"fldenv", 1, 0xd9, 4, Modrm
, Mem
, 0, 0},
677 {"fnsave", 1, 0xdd, 6, Modrm
, Mem
, 0, 0},
678 {"fsave", 1, 0xdd, 6, Modrm
, Mem
, 0, 0},
679 {"frstor", 1, 0xdd, 4, Modrm
, Mem
, 0, 0},
681 {"ffree", 1, 0xddc0, _
, ShortForm
, FloatReg
, 0, 0},
682 {"fnop", 0, 0xd9d0, _
, NoModrm
, 0, 0, 0},
683 {"fwait", 0, 0x9b, _
, NoModrm
, 0, 0, 0},
686 opcode prefixes; we allow them as seperate insns too
687 (see prefix table below)
689 {"aword", 0, 0x67, _
, NoModrm
, 0, 0, 0},
690 {"word", 0, 0x66, _
, NoModrm
, 0, 0, 0},
691 {"lock", 0, 0xf0, _
, NoModrm
, 0, 0, 0},
692 {"cs", 0, 0x2e, _
, NoModrm
, 0, 0, 0},
693 {"ds", 0, 0x3e, _
, NoModrm
, 0, 0, 0},
694 {"es", 0, 0x26, _
, NoModrm
, 0, 0, 0},
695 {"fs", 0, 0x64, _
, NoModrm
, 0, 0, 0},
696 {"gs", 0, 0x65, _
, NoModrm
, 0, 0, 0},
697 {"ss", 0, 0x36, _
, NoModrm
, 0, 0, 0},
698 {"rep", 0, 0xf3, _
, NoModrm
, 0, 0, 0},
699 {"repe", 0, 0xf3, _
, NoModrm
, 0, 0, 0},
700 { "repne", 0, 0xf2, _
, NoModrm
, 0, 0, 0},
702 {"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */
706 static const template *i386_optab_end
707 = i386_optab
+ sizeof (i386_optab
)/sizeof(i386_optab
[0]);
709 /* 386 register table */
711 static const reg_entry i386_regtab
[] = {
713 {"al", Reg8
|Acc
, 0}, {"cl", Reg8
|ShiftCount
, 1}, {"dl", Reg8
, 2},
715 {"ah", Reg8
, 4}, {"ch", Reg8
, 5}, {"dh", Reg8
, 6}, {"bh", Reg8
, 7},
717 {"ax", Reg16
|Acc
, 0}, {"cx", Reg16
, 1}, {"dx", Reg16
|InOutPortReg
, 2}, {"bx", Reg16
, 3},
718 {"sp", Reg16
, 4}, {"bp", Reg16
, 5}, {"si", Reg16
, 6}, {"di", Reg16
, 7},
720 {"eax", Reg32
|Acc
, 0}, {"ecx", Reg32
, 1}, {"edx", Reg32
, 2}, {"ebx", Reg32
, 3},
721 {"esp", Reg32
, 4}, {"ebp", Reg32
, 5}, {"esi", Reg32
, 6}, {"edi", Reg32
, 7},
722 /* segment registers */
723 {"es", SReg2
, 0}, {"cs", SReg2
, 1}, {"ss", SReg2
, 2},
724 {"ds", SReg2
, 3}, {"fs", SReg3
, 4}, {"gs", SReg3
, 5},
725 /* control registers */
726 {"cr0", Control
, 0}, {"cr2", Control
, 2}, {"cr3", Control
, 3},
727 /* debug registers */
728 {"db0", Debug
, 0}, {"db1", Debug
, 1}, {"db2", Debug
, 2},
729 {"db3", Debug
, 3}, {"db6", Debug
, 6}, {"db7", Debug
, 7},
731 {"tr6", Test
, 6}, {"tr7", Test
, 7},
732 /* float registers */
733 {"st(0)", FloatReg
|FloatAcc
, 0},
734 {"st", FloatReg
|FloatAcc
, 0},
735 {"st(1)", FloatReg
, 1}, {"st(2)", FloatReg
, 2},
736 {"st(3)", FloatReg
, 3}, {"st(4)", FloatReg
, 4}, {"st(5)", FloatReg
, 5},
737 {"st(6)", FloatReg
, 6}, {"st(7)", FloatReg
, 7}
740 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
742 static const reg_entry
*i386_regtab_end
743 = i386_regtab
+ sizeof(i386_regtab
)/sizeof(i386_regtab
[0]);
746 static const seg_entry cs
= { "cs", 0x2e };
747 static const seg_entry ds
= { "ds", 0x3e };
748 static const seg_entry ss
= { "ss", 0x36 };
749 static const seg_entry es
= { "es", 0x26 };
750 static const seg_entry fs
= { "fs", 0x64 };
751 static const seg_entry gs
= { "gs", 0x65 };
752 static const seg_entry null
= { "", 0x0 };
755 This table is used to store the default segment register implied by all
756 possible memory addressing modes.
757 It is indexed by the mode & modrm entries of the modrm byte as follows:
758 index = (mode<<3) | modrm;
760 static const seg_entry
*one_byte_segment_defaults
[] = {
762 &ds
, &ds
, &ds
, &ds
, &null
, &ds
, &ds
, &ds
,
764 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
766 &ds
, &ds
, &ds
, &ds
, &null
, &ss
, &ds
, &ds
,
767 /* mode 3 --- not a memory reference; never referenced */
770 static const seg_entry
*two_byte_segment_defaults
[] = {
772 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
774 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
776 &ds
, &ds
, &ds
, &ds
, &ss
, &ds
, &ds
, &ds
,
777 /* mode 3 --- not a memory reference; never referenced */
780 static const prefix_entry i386_prefixtab
[] = {
781 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
782 * (How is this useful?) */
783 #define WORD_PREFIX_OPCODE 0x66
784 { "data16", 0x66 }, /* operand size prefix */
785 { "lock", 0xf0 }, /* bus lock prefix */
786 { "wait", 0x9b }, /* wait for coprocessor */
787 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
788 { "es", 0x26 }, { "fs", 0x64 },
789 { "gs", 0x65 }, { "ss", 0x36 },
790 /* REPE & REPNE used to detect rep/repne with a non-string instruction */
793 { "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */
797 static const prefix_entry
*i386_prefixtab_end
798 = i386_prefixtab
+ sizeof(i386_prefixtab
)/sizeof(i386_prefixtab
[0]);
800 /* end of i386-opcode.h */