include/i960-opcode.h

   1 /* Basic 80960 instruction formats.
   2  *
   3  * The 'COJ' instructions are actually COBR instructions with the 'b' in
   4  * the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if necessary:
   5  * if the displacement will not fit in 13 bits, the assembler will replace them
   6  * with the corresponding compare and branch instructions.
   7  *
   8  * All of the 'MEMn' instructions are the same format; the 'n' in the name
   9  * indicates the default index scale factor (the size of the datum operated on).
  10  *
  11  * The FBRA formats are not actually an instruction format.  They are the
  12  * "convenience directives" for branching on floating-point comparisons,
  13  * each of which generates 2 instructions (a 'bno' and one other branch).
  14  *
  15  * The CALLJ format is not actually an instruction format.  It indicates that
  16  * the instruction generated (a CTRL-format 'call') should have its relocation
  17  * specially flagged for link-time replacement with a 'bal' or 'calls' if
  18  * appropriate.
  19  */
  20
  21 /* $Id$ */
  22
  23 #define CTRL    0
  24 #define COBR    1
  25 #define COJ     2
  26 #define REG     3
  27 #define MEM1    4
  28 #define MEM2    5
  29 #define MEM4    6
  30 #define MEM8    7
  31 #define MEM12   8
  32 #define MEM16   9
  33 #define FBRA    10
  34 #define CALLJ   11
  35
  36 /* Masks for the mode bits in REG format instructions */
  37 #define M1              0x0800
  38 #define M2              0x1000
  39 #define M3              0x2000
  40
  41 /* Generate the 12-bit opcode for a REG format instruction by placing the
  42  * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
  43  * 7-10.
  44  */
  45
  46 #define REG_OPC(opc)    ((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
  47
  48 /* Generate a template for a REG format instruction:  place the opcode bits
  49  * in the appropriate fields and OR in mode bits for the operands that will not
  50  * be used.  I.e.,
  51  *              set m1=1, if src1 will not be used
  52  *              set m2=1, if src2 will not be used
  53  *              set m3=1, if dst  will not be used
  54  *
  55  * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
  56  * The information is also useful to us because some 1-operand REG instructions
  57  * use the src1 field, others the dst field; and some 2-operand REG instructions
  58  * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
  59  */
  60 #define R_0(opc)        ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands      */
  61 #define R_1(opc)        ( REG_OPC(opc) | M2 | M3 )      /* 1 operand: src1  */
  62 #define R_1D(opc)       ( REG_OPC(opc) | M1 | M2 )      /* 1 operand: dst   */
  63 #define R_2(opc)        ( REG_OPC(opc) | M3 )           /* 2 ops: src1/src2 */
  64 #define R_2D(opc)       ( REG_OPC(opc) | M2 )           /* 2 ops: src1/dst  */
  65 #define R_3(opc)        ( REG_OPC(opc) )                /* 3 operands       */
  66
  67 /* DESCRIPTOR BYTES FOR REGISTER OPERANDS
  68  *
  69  * Interpret names as follows:
  70  *      R:   global or local register only
  71  *      RS:  global, local, or (if target allows) special-function register only
  72  *      RL:  global or local register, or integer literal
  73  *      RSL: global, local, or (if target allows) special-function register;
  74  *              or integer literal
  75  *      F:   global, local, or floating-point register
  76  *      FL:  global, local, or floating-point register; or literal (including
  77  *              floating point)
  78  *
  79  * A number appended to a name indicates that registers must be aligned,
  80  * as follows:
  81  *      2: register number must be multiple of 2
  82  *      4: register number must be multiple of 4
  83  */
  84
  85 #define SFR     0x10            /* Mask for the "sfr-OK" bit */
  86 #define LIT     0x08            /* Mask for the "literal-OK" bit */
  87 #define FP      0x04            /* Mask for "floating-point-OK" bit */
  88
  89 /* This macro ors the bits together.  Note that 'align' is a mask
  90  * for the low 0, 1, or 2 bits of the register number, as appropriate.
  91  */
  92 #define OP(align,lit,fp,sfr)    ( align | lit | fp | sfr )
  93
  94 #define R       OP( 0, 0,   0,  0   )
  95 #define RS      OP( 0, 0,   0,  SFR )
  96 #define RL      OP( 0, LIT, 0,  0   )
  97 #define RSL     OP( 0, LIT, 0,  SFR )
  98 #define F       OP( 0, 0,   FP, 0   )
  99 #define FL      OP( 0, LIT, FP, 0   )
 100 #define R2      OP( 1, 0,   0,  0   )
 101 #define RL2     OP( 1, LIT, 0,  0   )
 102 #define F2      OP( 1, 0,   FP, 0   )
 103 #define FL2     OP( 1, LIT, FP, 0   )
 104 #define R4      OP( 3, 0,   0,  0   )
 105 #define RL4     OP( 3, LIT, 0,  0   )
 106 #define F4      OP( 3, 0,   FP, 0   )
 107 #define FL4     OP( 3, LIT, FP, 0   )
 108
 109 #define M       0x7f    /* Memory operand (MEMA & MEMB format instructions) */
 110
 111 /* Macros to extract info from the register operand descriptor byte 'od'.
 112  */
 113 #define SFR_OK(od)      (od & SFR)      /* TRUE if sfr operand allowed */
 114 #define LIT_OK(od)      (od & LIT)      /* TRUE if literal operand allowed */
 115 #define FP_OK(od)       (od & FP)       /* TRUE if floating-point op allowed */
 116 #define REG_ALIGN(od,n) ((od & 0x3 & n) == 0)
 117                                         /* TRUE if reg #n is properly aligned */
 118 #define MEMOP(od)       (od == M)       /* TRUE if operand is a memory operand*/
 119
 120 /* Description of a single i80960 instruction */
 121 struct i960_opcode {
 122         long opcode;    /* 32 bits, constant fields filled in, rest zeroed */
 123         char *name;     /* Assembler mnemonic                              */
 124         short iclass;   /* Class: see #defines below                       */
 125         char format;    /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ      */
 126         char num_ops;   /* Number of operands                              */
 127         char operand[3];/* Operand descriptors; same order as assembler instr */
 128 };
 129
 130 /* Classes of 960 intructions:
 131  *      - each instruction falls into one class.
 132  *      - each target architecture supports one or more classes.
 133  *
 134  * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
 135  */
 136 #define I_BASE  0x01    /* 80960 base instruction set   */
 137 #define I_CX    0x02    /* 80960Cx instruction          */
 138 #define I_DEC   0x04    /* Decimal instruction          */
 139 #define I_FP    0x08    /* Floating point instruction   */
 140 #define I_KX    0x10    /* 80960Kx instruction          */
 141 #define I_MIL   0x20    /* Military instruction         */
 142 #define I_CASIM 0x40    /* CA simulator instruction     */
 143
 144 /******************************************************************************
 145  *
 146  *              TABLE OF i960 INSTRUCTION DESCRIPTIONS
 147  *
 148  ******************************************************************************/
 149
 150 const struct i960_opcode i960_opcodes[] = {
 151
 152         /* if a CTRL instruction has an operand, it's always a displacement */
 153
 154         { 0x09000000,   "callj",        I_BASE, CALLJ,  1 },/*default=='call'*/
 155         { 0x08000000,   "b",            I_BASE, CTRL,   1 },
 156         { 0x09000000,   "call",         I_BASE, CTRL,   1 },
 157         { 0x0a000000,   "ret",          I_BASE, CTRL,   0 },
 158         { 0x0b000000,   "bal",          I_BASE, CTRL,   1 },
 159         { 0x10000000,   "bno",          I_BASE, CTRL,   1 },
 160         { 0x10000000,   "bf",           I_BASE, CTRL,   1 }, /* same as bno */
 161         { 0x10000000,   "bru",          I_BASE, CTRL,   1 }, /* same as bno */
 162         { 0x11000000,   "bg",           I_BASE, CTRL,   1 },
 163         { 0x11000000,   "brg",          I_BASE, CTRL,   1 }, /* same as bg */
 164         { 0x12000000,   "be",           I_BASE, CTRL,   1 },
 165         { 0x12000000,   "bre",          I_BASE, CTRL,   1 }, /* same as be */
 166         { 0x13000000,   "bge",          I_BASE, CTRL,   1 },
 167         { 0x13000000,   "brge",         I_BASE, CTRL,   1 }, /* same as bge */
 168         { 0x14000000,   "bl",           I_BASE, CTRL,   1 },
 169         { 0x14000000,   "brl",          I_BASE, CTRL,   1 }, /* same as bl */
 170         { 0x15000000,   "bne",          I_BASE, CTRL,   1 },
 171         { 0x15000000,   "brlg",         I_BASE, CTRL,   1 }, /* same as bne */
 172         { 0x16000000,   "ble",          I_BASE, CTRL,   1 },
 173         { 0x16000000,   "brle",         I_BASE, CTRL,   1 }, /* same as ble */
 174         { 0x17000000,   "bo",           I_BASE, CTRL,   1 },
 175         { 0x17000000,   "bt",           I_BASE, CTRL,   1 }, /* same as bo */
 176         { 0x17000000,   "bro",          I_BASE, CTRL,   1 }, /* same as bo */
 177         { 0x18000000,   "faultno",      I_BASE, CTRL,   0 },
 178         { 0x18000000,   "faultf",       I_BASE, CTRL,   0 }, /*same as faultno*/
 179         { 0x19000000,   "faultg",       I_BASE, CTRL,   0 },
 180         { 0x1a000000,   "faulte",       I_BASE, CTRL,   0 },
 181         { 0x1b000000,   "faultge",      I_BASE, CTRL,   0 },
 182         { 0x1c000000,   "faultl",       I_BASE, CTRL,   0 },
 183         { 0x1d000000,   "faultne",      I_BASE, CTRL,   0 },
 184         { 0x1e000000,   "faultle",      I_BASE, CTRL,   0 },
 185         { 0x1f000000,   "faulto",       I_BASE, CTRL,   0 },
 186         { 0x1f000000,   "faultt",       I_BASE, CTRL,   0 }, /* syn for faulto */
 187
 188         { 0x01000000,   "syscall",      I_CASIM,CTRL,   0 },
 189
 190         /* If a COBR (or COJ) has 3 operands, the last one is always a
 191          * displacement and does not appear explicitly in the table.
 192          */
 193
 194         { 0x20000000,   "testno",       I_BASE, COBR,   1, R            },
 195         { 0x21000000,   "testg",        I_BASE, COBR,   1, R            },
 196         { 0x22000000,   "teste",        I_BASE, COBR,   1, R            },
 197         { 0x23000000,   "testge",       I_BASE, COBR,   1, R            },
 198         { 0x24000000,   "testl",        I_BASE, COBR,   1, R            },
 199         { 0x25000000,   "testne",       I_BASE, COBR,   1, R            },
 200         { 0x26000000,   "testle",       I_BASE, COBR,   1, R            },
 201         { 0x27000000,   "testo",        I_BASE, COBR,   1, R            },
 202         { 0x30000000,   "bbc",          I_BASE, COBR,   3, RL, RS       },
 203         { 0x31000000,   "cmpobg",       I_BASE, COBR,   3, RL, RS       },
 204         { 0x32000000,   "cmpobe",       I_BASE, COBR,   3, RL, RS       },
 205         { 0x33000000,   "cmpobge",      I_BASE, COBR,   3, RL, RS       },
 206         { 0x34000000,   "cmpobl",       I_BASE, COBR,   3, RL, RS       },
 207         { 0x35000000,   "cmpobne",      I_BASE, COBR,   3, RL, RS       },
 208         { 0x36000000,   "cmpoble",      I_BASE, COBR,   3, RL, RS       },
 209         { 0x37000000,   "bbs",          I_BASE, COBR,   3, RL, RS       },
 210         { 0x38000000,   "cmpibno",      I_BASE, COBR,   3, RL, RS       },
 211         { 0x39000000,   "cmpibg",       I_BASE, COBR,   3, RL, RS       },
 212         { 0x3a000000,   "cmpibe",       I_BASE, COBR,   3, RL, RS       },
 213         { 0x3b000000,   "cmpibge",      I_BASE, COBR,   3, RL, RS       },
 214         { 0x3c000000,   "cmpibl",       I_BASE, COBR,   3, RL, RS       },
 215         { 0x3d000000,   "cmpibne",      I_BASE, COBR,   3, RL, RS       },
 216         { 0x3e000000,   "cmpible",      I_BASE, COBR,   3, RL, RS       },
 217         { 0x3f000000,   "cmpibo",       I_BASE, COBR,   3, RL, RS       },
 218         { 0x31000000,   "cmpojg",       I_BASE, COJ,    3, RL, RS       },
 219         { 0x32000000,   "cmpoje",       I_BASE, COJ,    3, RL, RS       },
 220         { 0x33000000,   "cmpojge",      I_BASE, COJ,    3, RL, RS       },
 221         { 0x34000000,   "cmpojl",       I_BASE, COJ,    3, RL, RS       },
 222         { 0x35000000,   "cmpojne",      I_BASE, COJ,    3, RL, RS       },
 223         { 0x36000000,   "cmpojle",      I_BASE, COJ,    3, RL, RS       },
 224         { 0x38000000,   "cmpijno",      I_BASE, COJ,    3, RL, RS       },
 225         { 0x39000000,   "cmpijg",       I_BASE, COJ,    3, RL, RS       },
 226         { 0x3a000000,   "cmpije",       I_BASE, COJ,    3, RL, RS       },
 227         { 0x3b000000,   "cmpijge",      I_BASE, COJ,    3, RL, RS       },
 228         { 0x3c000000,   "cmpijl",       I_BASE, COJ,    3, RL, RS       },
 229         { 0x3d000000,   "cmpijne",      I_BASE, COJ,    3, RL, RS       },
 230         { 0x3e000000,   "cmpijle",      I_BASE, COJ,    3, RL, RS       },
 231         { 0x3f000000,   "cmpijo",       I_BASE, COJ,    3, RL, RS       },
 232
 233         { 0x80000000,   "ldob",         I_BASE, MEM1,   2, M,  R        },
 234         { 0x82000000,   "stob",         I_BASE, MEM1,   2, R , M        },
 235         { 0x84000000,   "bx",           I_BASE, MEM1,   1, M            },
 236         { 0x85000000,   "balx",         I_BASE, MEM1,   2, M,  R        },
 237         { 0x86000000,   "callx",        I_BASE, MEM1,   1, M            },
 238         { 0x88000000,   "ldos",         I_BASE, MEM2,   2, M,  R        },
 239         { 0x8a000000,   "stos",         I_BASE, MEM2,   2, R , M        },
 240         { 0x8c000000,   "lda",          I_BASE, MEM1,   2, M,  R        },
 241         { 0x90000000,   "ld",           I_BASE, MEM4,   2, M,  R        },
 242         { 0x92000000,   "st",           I_BASE, MEM4,   2, R , M        },
 243         { 0x98000000,   "ldl",          I_BASE, MEM8,   2, M,  R2       },
 244         { 0x9a000000,   "stl",          I_BASE, MEM8,   2, R2 ,M        },
 245         { 0xa0000000,   "ldt",          I_BASE, MEM12,  2, M,  R4       },
 246         { 0xa2000000,   "stt",          I_BASE, MEM12,  2, R4 ,M        },
 247         { 0xb0000000,   "ldq",          I_BASE, MEM16,  2, M,  R4       },
 248         { 0xb2000000,   "stq",          I_BASE, MEM16,  2, R4 ,M        },
 249         { 0xc0000000,   "ldib",         I_BASE, MEM1,   2, M,  R        },
 250         { 0xc2000000,   "stib",         I_BASE, MEM1,   2, R , M        },
 251         { 0xc8000000,   "ldis",         I_BASE, MEM2,   2, M,  R        },
 252         { 0xca000000,   "stis",         I_BASE, MEM2,   2, R , M        },
 253
 254         { R_3(0x580),   "notbit",       I_BASE, REG,    3, RSL,RSL,RS   },
 255         { R_3(0x581),   "and",          I_BASE, REG,    3, RSL,RSL,RS   },
 256         { R_3(0x582),   "andnot",       I_BASE, REG,    3, RSL,RSL,RS   },
 257         { R_3(0x583),   "setbit",       I_BASE, REG,    3, RSL,RSL,RS   },
 258         { R_3(0x584),   "notand",       I_BASE, REG,    3, RSL,RSL,RS   },
 259         { R_3(0x586),   "xor",          I_BASE, REG,    3, RSL,RSL,RS   },
 260         { R_3(0x587),   "or",           I_BASE, REG,    3, RSL,RSL,RS   },
 261         { R_3(0x588),   "nor",          I_BASE, REG,    3, RSL,RSL,RS   },
 262         { R_3(0x589),   "xnor",         I_BASE, REG,    3, RSL,RSL,RS   },
 263         { R_2D(0x58a),  "not",          I_BASE, REG,    2, RSL,RS       },
 264         { R_3(0x58b),   "ornot",        I_BASE, REG,    3, RSL,RSL,RS   },
 265         { R_3(0x58c),   "clrbit",       I_BASE, REG,    3, RSL,RSL,RS   },
 266         { R_3(0x58d),   "notor",        I_BASE, REG,    3, RSL,RSL,RS   },
 267         { R_3(0x58e),   "nand",         I_BASE, REG,    3, RSL,RSL,RS   },
 268         { R_3(0x58f),   "alterbit",     I_BASE, REG,    3, RSL,RSL,RS   },
 269         { R_3(0x590),   "addo",         I_BASE, REG,    3, RSL,RSL,RS   },
 270         { R_3(0x591),   "addi",         I_BASE, REG,    3, RSL,RSL,RS   },
 271         { R_3(0x592),   "subo",         I_BASE, REG,    3, RSL,RSL,RS   },
 272         { R_3(0x593),   "subi",         I_BASE, REG,    3, RSL,RSL,RS   },
 273         { R_3(0x598),   "shro",         I_BASE, REG,    3, RSL,RSL,RS   },
 274         { R_3(0x59a),   "shrdi",        I_BASE, REG,    3, RSL,RSL,RS   },
 275         { R_3(0x59b),   "shri",         I_BASE, REG,    3, RSL,RSL,RS   },
 276         { R_3(0x59c),   "shlo",         I_BASE, REG,    3, RSL,RSL,RS   },
 277         { R_3(0x59d),   "rotate",       I_BASE, REG,    3, RSL,RSL,RS   },
 278         { R_3(0x59e),   "shli",         I_BASE, REG,    3, RSL,RSL,RS   },
 279         { R_2(0x5a0),   "cmpo",         I_BASE, REG,    2, RSL,RSL      },
 280         { R_2(0x5a1),   "cmpi",         I_BASE, REG,    2, RSL,RSL      },
 281         { R_2(0x5a2),   "concmpo",      I_BASE, REG,    2, RSL,RSL      },
 282         { R_2(0x5a3),   "concmpi",      I_BASE, REG,    2, RSL,RSL      },
 283         { R_3(0x5a4),   "cmpinco",      I_BASE, REG,    3, RSL,RSL,RS   },
 284         { R_3(0x5a5),   "cmpinci",      I_BASE, REG,    3, RSL,RSL,RS   },
 285         { R_3(0x5a6),   "cmpdeco",      I_BASE, REG,    3, RSL,RSL,RS   },
 286         { R_3(0x5a7),   "cmpdeci",      I_BASE, REG,    3, RSL,RSL,RS   },
 287         { R_2(0x5ac),   "scanbyte",     I_BASE, REG,    2, RSL,RSL      },
 288         { R_2(0x5ae),   "chkbit",       I_BASE, REG,    2, RSL,RSL      },
 289         { R_3(0x5b0),   "addc",         I_BASE, REG,    3, RSL,RSL,RS   },
 290         { R_3(0x5b2),   "subc",         I_BASE, REG,    3, RSL,RSL,RS   },
 291         { R_2D(0x5cc),  "mov",          I_BASE, REG,    2, RSL,RS       },
 292         { R_2D(0x5dc),  "movl",         I_BASE, REG,    2, RL2,R2       },
 293         { R_2D(0x5ec),  "movt",         I_BASE, REG,    2, RL4,R4       },
 294         { R_2D(0x5fc),  "movq",         I_BASE, REG,    2, RL4,R4       },
 295         { R_3(0x610),   "atmod",        I_BASE, REG,    3, RS, RSL,R    },
 296         { R_3(0x612),   "atadd",        I_BASE, REG,    3, RS, RSL,RS   },
 297         { R_2D(0x640),  "spanbit",      I_BASE, REG,    2, RSL,RS       },
 298         { R_2D(0x641),  "scanbit",      I_BASE, REG,    2, RSL,RS       },
 299         { R_3(0x645),   "modac",        I_BASE, REG,    3, RSL,RSL,RS   },
 300         { R_3(0x650),   "modify",       I_BASE, REG,    3, RSL,RSL,R    },
 301         { R_3(0x651),   "extract",      I_BASE, REG,    3, RSL,RSL,R    },
 302         { R_3(0x654),   "modtc",        I_BASE, REG,    3, RSL,RSL,RS   },
 303         { R_3(0x655),   "modpc",        I_BASE, REG,    3, RSL,RSL,R    },
 304         { R_1(0x660),   "calls",        I_BASE, REG,    1, RSL          },
 305         { R_0(0x66b),   "mark",         I_BASE, REG,    0,              },
 306         { R_0(0x66c),   "fmark",        I_BASE, REG,    0,              },
 307         { R_0(0x66d),   "flushreg",     I_BASE, REG,    0,              },
 308         { R_0(0x66f),   "syncf",        I_BASE, REG,    0,              },
 309         { R_3(0x670),   "emul",         I_BASE, REG,    3, RSL,RSL,R2   },
 310         { R_3(0x671),   "ediv",         I_BASE, REG,    3, RSL,RL2,RS   },
 311         { R_2D(0x672),  "cvtadr",       I_CASIM,REG,    2, RL, R2       },
 312         { R_3(0x701),   "mulo",         I_BASE, REG,    3, RSL,RSL,RS   },
 313         { R_3(0x708),   "remo",         I_BASE, REG,    3, RSL,RSL,RS   },
 314         { R_3(0x70b),   "divo",         I_BASE, REG,    3, RSL,RSL,RS   },
 315         { R_3(0x741),   "muli",         I_BASE, REG,    3, RSL,RSL,RS   },
 316         { R_3(0x748),   "remi",         I_BASE, REG,    3, RSL,RSL,RS   },
 317         { R_3(0x749),   "modi",         I_BASE, REG,    3, RSL,RSL,RS   },
 318         { R_3(0x74b),   "divi",         I_BASE, REG,    3, RSL,RSL,RS   },
 319
 320         /* Floating-point instructions */
 321
 322         { R_2D(0x674),  "cvtir",        I_FP,   REG,    2, RL, F        },
 323         { R_2D(0x675),  "cvtilr",       I_FP,   REG,    2, RL, F        },
 324         { R_3(0x676),   "scalerl",      I_FP,   REG,    3, RL, FL2,F2   },
 325         { R_3(0x677),   "scaler",       I_FP,   REG,    3, RL, FL, F    },
 326         { R_3(0x680),   "atanr",        I_FP,   REG,    3, FL, FL, F    },
 327         { R_3(0x681),   "logepr",       I_FP,   REG,    3, FL, FL, F    },
 328         { R_3(0x682),   "logr",         I_FP,   REG,    3, FL, FL, F    },
 329         { R_3(0x683),   "remr",         I_FP,   REG,    3, FL, FL, F    },
 330         { R_2(0x684),   "cmpor",        I_FP,   REG,    2, FL, FL       },
 331         { R_2(0x685),   "cmpr",         I_FP,   REG,    2, FL, FL       },
 332         { R_2D(0x688),  "sqrtr",        I_FP,   REG,    2, FL, F        },
 333         { R_2D(0x689),  "expr",         I_FP,   REG,    2, FL, F        },
 334         { R_2D(0x68a),  "logbnr",       I_FP,   REG,    2, FL, F        },
 335         { R_2D(0x68b),  "roundr",       I_FP,   REG,    2, FL, F        },
 336         { R_2D(0x68c),  "sinr",         I_FP,   REG,    2, FL, F        },
 337         { R_2D(0x68d),  "cosr",         I_FP,   REG,    2, FL, F        },
 338         { R_2D(0x68e),  "tanr",         I_FP,   REG,    2, FL, F        },
 339         { R_1(0x68f),   "classr",       I_FP,   REG,    1, FL           },
 340         { R_3(0x690),   "atanrl",       I_FP,   REG,    3, FL2,FL2,F2   },
 341         { R_3(0x691),   "logeprl",      I_FP,   REG,    3, FL2,FL2,F2   },
 342         { R_3(0x692),   "logrl",        I_FP,   REG,    3, FL2,FL2,F2   },
 343         { R_3(0x693),   "remrl",        I_FP,   REG,    3, FL2,FL2,F2   },
 344         { R_2(0x694),   "cmporl",       I_FP,   REG,    2, FL2,FL2      },
 345         { R_2(0x695),   "cmprl",        I_FP,   REG,    2, FL2,FL2      },
 346         { R_2D(0x698),  "sqrtrl",       I_FP,   REG,    2, FL2,F2       },
 347         { R_2D(0x699),  "exprl",        I_FP,   REG,    2, FL2,F2       },
 348         { R_2D(0x69a),  "logbnrl",      I_FP,   REG,    2, FL2,F2       },
 349         { R_2D(0x69b),  "roundrl",      I_FP,   REG,    2, FL2,F2       },
 350         { R_2D(0x69c),  "sinrl",        I_FP,   REG,    2, FL2,F2       },
 351         { R_2D(0x69d),  "cosrl",        I_FP,   REG,    2, FL2,F2       },
 352         { R_2D(0x69e),  "tanrl",        I_FP,   REG,    2, FL2,F2       },
 353         { R_1(0x69f),   "classrl",      I_FP,   REG,    1, FL2          },
 354         { R_2D(0x6c0),  "cvtri",        I_FP,   REG,    2, FL, R        },
 355         { R_2D(0x6c1),  "cvtril",       I_FP,   REG,    2, FL, R2       },
 356         { R_2D(0x6c2),  "cvtzri",       I_FP,   REG,    2, FL, R        },
 357         { R_2D(0x6c3),  "cvtzril",      I_FP,   REG,    2, FL, R2       },
 358         { R_2D(0x6c9),  "movr",         I_FP,   REG,    2, FL, F        },
 359         { R_2D(0x6d9),  "movrl",        I_FP,   REG,    2, FL2,F2       },
 360         { R_2D(0x6e1),  "movre",        I_FP,   REG,    2, FL4,F4       },
 361         { R_3(0x6e2),   "cpysre",       I_FP,   REG,    3, FL4,FL4,F4   },
 362         { R_3(0x6e3),   "cpyrsre",      I_FP,   REG,    3, FL4,FL4,F4   },
 363         { R_3(0x78b),   "divr",         I_FP,   REG,    3, FL, FL, F    },
 364         { R_3(0x78c),   "mulr",         I_FP,   REG,    3, FL, FL, F    },
 365         { R_3(0x78d),   "subr",         I_FP,   REG,    3, FL, FL, F    },
 366         { R_3(0x78f),   "addr",         I_FP,   REG,    3, FL, FL, F    },
 367         { R_3(0x79b),   "divrl",        I_FP,   REG,    3, FL2,FL2,F2   },
 368         { R_3(0x79c),   "mulrl",        I_FP,   REG,    3, FL2,FL2,F2   },
 369         { R_3(0x79d),   "subrl",        I_FP,   REG,    3, FL2,FL2,F2   },
 370         { R_3(0x79f),   "addrl",        I_FP,   REG,    3, FL2,FL2,F2   },
 371
 372         /* These are the floating point branch instructions.  Each actually
 373          * generates 2 branch instructions:  the first a CTRL instruction with
 374          * the indicated opcode, and the second a 'bno'.
 375          */
 376
 377         { 0x12000000,   "brue",         I_FP,   FBRA,   1       },
 378         { 0x11000000,   "brug",         I_FP,   FBRA,   1       },
 379         { 0x13000000,   "bruge",        I_FP,   FBRA,   1       },
 380         { 0x14000000,   "brul",         I_FP,   FBRA,   1       },
 381         { 0x16000000,   "brule",        I_FP,   FBRA,   1       },
 382         { 0x15000000,   "brulg",        I_FP,   FBRA,   1       },
 383
 384
 385         /* Decimal instructions */
 386
 387         { R_3(0x642),   "daddc",        I_DEC,  REG,    3, RSL,RSL,RS   },
 388         { R_3(0x643),   "dsubc",        I_DEC,  REG,    3, RSL,RSL,RS   },
 389         { R_2D(0x644),  "dmovt",        I_DEC,  REG,    2, RSL,RS       },
 390
 391
 392         /* KX extensions */
 393
 394         { R_2(0x600),   "synmov",       I_KX,   REG,    2, R,  R        },
 395         { R_2(0x601),   "synmovl",      I_KX,   REG,    2, R,  R        },
 396         { R_2(0x602),   "synmovq",      I_KX,   REG,    2, R,  R        },
 397         { R_2D(0x615),  "synld",        I_KX,   REG,    2, R,  R        },
 398
 399
 400         /* MC extensions */
 401
 402         { R_3(0x603),   "cmpstr",       I_MIL,  REG,    3, R,  R,  RL   },
 403         { R_3(0x604),   "movqstr",      I_MIL,  REG,    3, R,  R,  RL   },
 404         { R_3(0x605),   "movstr",       I_MIL,  REG,    3, R,  R,  RL   },
 405         { R_2D(0x613),  "inspacc",      I_MIL,  REG,    2, R,  R        },
 406         { R_2D(0x614),  "ldphy",        I_MIL,  REG,    2, R,  R        },
 407         { R_3(0x617),   "fill",         I_MIL,  REG,    3, R,  RL, RL   },
 408         { R_2D(0x646),  "condrec",      I_MIL,  REG,    2, R,  R        },
 409         { R_2D(0x656),  "receive",      I_MIL,  REG,    2, R,  R        },
 410         { R_3(0x662),   "send",         I_MIL,  REG,    3, R,  RL, R    },
 411         { R_1(0x663),   "sendserv",     I_MIL,  REG,    1, R            },
 412         { R_1(0x664),   "resumprcs",    I_MIL,  REG,    1, R            },
 413         { R_1(0x665),   "schedprcs",    I_MIL,  REG,    1, R            },
 414         { R_0(0x666),   "saveprcs",     I_MIL,  REG,    0,              },
 415         { R_1(0x668),   "condwait",     I_MIL,  REG,    1, R            },
 416         { R_1(0x669),   "wait",         I_MIL,  REG,    1, R            },
 417         { R_1(0x66a),   "signal",       I_MIL,  REG,    1, R            },
 418         { R_1D(0x673),  "ldtime",       I_MIL,  REG,    1, R2           },
 419
 420
 421         /* CX extensions */
 422
 423         { R_3(0x5d8),   "eshro",        I_CX,   REG,    3, RSL,RSL,RS   },
 424         { R_3(0x630),   "sdma",         I_CX,   REG,    3, RSL,RSL,RL   },
 425         { R_3(0x631),   "udma",         I_CX,   REG,    0               },
 426         { R_3(0x659),   "sysctl",       I_CX,   REG,    3, RSL,RSL,RL   },
 427
 428
 429         /* END OF TABLE */
 430
 431         { 0,            NULL,           0,      0 }
 432 };
 433
 434  /* end of i960-opcode.h */