2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __KVM_ARM_VGIC_H
17 #define __KVM_ARM_VGIC_H
19 #include <linux/kernel.h>
20 #include <linux/kvm.h>
21 #include <linux/irqreturn.h>
22 #include <linux/spinlock.h>
23 #include <linux/types.h>
24 #include <kvm/iodev.h>
25 #include <linux/list.h>
27 #define VGIC_V3_MAX_CPUS 255
28 #define VGIC_V2_MAX_CPUS 8
29 #define VGIC_NR_IRQS_LEGACY 256
30 #define VGIC_NR_SGIS 16
31 #define VGIC_NR_PPIS 16
32 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
33 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
34 #define VGIC_MAX_SPI 1019
35 #define VGIC_MAX_RESERVED 1023
36 #define VGIC_MIN_LPI 8192
39 VGIC_V2
, /* Good ol' GICv2 */
40 VGIC_V3
, /* New fancy GICv3 */
43 /* same for all guests, as depending only on the _host's_ GIC model */
45 /* type of the host GIC */
48 /* Physical address of vgic virtual cpu interface */
49 phys_addr_t vcpu_base
;
51 /* virtual control interface mapping */
52 void __iomem
*vctrl_base
;
54 /* Number of implemented list registers */
57 /* Maintenance IRQ number */
58 unsigned int maint_irq
;
60 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
63 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
64 bool can_emulate_gicv2
;
67 extern struct vgic_global kvm_vgic_global_state
;
69 #define VGIC_V2_MAX_LRS (1 << 6)
70 #define VGIC_V3_MAX_LRS 16
71 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
73 enum vgic_irq_config
{
79 spinlock_t irq_lock
; /* Protects the content of the struct */
80 struct list_head lpi_list
; /* Used to link all LPIs together */
81 struct list_head ap_list
;
83 struct kvm_vcpu
*vcpu
; /* SGIs and PPIs: The VCPU
84 * SPIs and LPIs: The VCPU whose ap_list
88 struct kvm_vcpu
*target_vcpu
; /* The VCPU that this interrupt should
89 * be sent to, as a result of the
90 * targets reg (v2) or the
94 u32 intid
; /* Guest visible INTID */
96 bool line_level
; /* Level only */
97 bool soft_pending
; /* Level only */
98 bool active
; /* not used for LPIs */
100 bool hw
; /* Tied to HW IRQ */
101 struct kref refcount
; /* Used for LPIs */
102 u32 hwintid
; /* HW INTID number */
104 u8 targets
; /* GICv2 target VCPUs mask */
105 u32 mpidr
; /* GICv3 target VCPU */
107 u8 source
; /* GICv2 SGIs only */
109 enum vgic_irq_config config
; /* Level or edge */
112 struct vgic_register_region
;
122 struct vgic_io_device
{
125 struct kvm_vcpu
*redist_vcpu
;
126 struct vgic_its
*its
;
128 const struct vgic_register_region
*regions
;
129 enum iodev_type iodev_type
;
131 struct kvm_io_device dev
;
135 /* The base address of the ITS control register frame */
140 struct vgic_io_device iodev
;
142 /* These registers correspond to GITS_BASER{0,1} */
143 u64 baser_device_table
;
144 u64 baser_coll_table
;
146 /* Protects the command queue */
147 struct mutex cmd_lock
;
152 /* Protects the device and collection lists */
153 struct mutex its_lock
;
154 struct list_head device_list
;
155 struct list_head collection_list
;
163 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
166 /* Do injected MSIs require an additional device ID? */
167 bool msis_require_devid
;
171 /* TODO: Consider moving to global state */
172 /* Virtual control interface mapping */
173 void __iomem
*vctrl_base
;
175 /* base addresses in guest physical address space: */
176 gpa_t vgic_dist_base
; /* distributor */
178 /* either a GICv2 CPU interface */
180 /* or a number of GICv3 redistributor regions */
181 gpa_t vgic_redist_base
;
184 /* distributor enabled */
187 struct vgic_irq
*spis
;
189 struct vgic_io_device dist_iodev
;
194 * Contains the attributes and gpa of the LPI configuration table.
195 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
196 * one address across all redistributors.
197 * GICv3 spec: 6.1.2 "LPI Configuration tables"
201 /* Protects the lpi_list and the count value below. */
202 spinlock_t lpi_list_lock
;
203 struct list_head lpi_list_head
;
207 struct vgic_v2_cpu_if
{
210 u32 vgic_misr
; /* Saved only */
211 u64 vgic_eisr
; /* Saved only */
212 u64 vgic_elrsr
; /* Saved only */
214 u32 vgic_lr
[VGIC_V2_MAX_LRS
];
217 struct vgic_v3_cpu_if
{
218 #ifdef CONFIG_KVM_ARM_VGIC_V3
221 u32 vgic_sre
; /* Restored only, change ignored */
222 u32 vgic_misr
; /* Saved only */
223 u32 vgic_eisr
; /* Saved only */
224 u32 vgic_elrsr
; /* Saved only */
227 u64 vgic_lr
[VGIC_V3_MAX_LRS
];
232 /* CPU vif control registers for world switch */
234 struct vgic_v2_cpu_if vgic_v2
;
235 struct vgic_v3_cpu_if vgic_v3
;
238 unsigned int used_lrs
;
239 struct vgic_irq private_irqs
[VGIC_NR_PRIVATE_IRQS
];
241 spinlock_t ap_list_lock
; /* Protects the ap_list */
244 * List of IRQs that this VCPU should consider because they are either
245 * Active or Pending (hence the name; AP list), or because they recently
246 * were one of the two and need to be migrated off this list to another
249 struct list_head ap_list_head
;
254 * Members below are used with GICv3 emulation only and represent
255 * parts of the redistributor.
257 struct vgic_io_device rd_iodev
;
258 struct vgic_io_device sgi_iodev
;
260 /* Contains the attributes and gpa of the LPI pending tables. */
266 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
);
267 void kvm_vgic_early_init(struct kvm
*kvm
);
268 int kvm_vgic_create(struct kvm
*kvm
, u32 type
);
269 void kvm_vgic_destroy(struct kvm
*kvm
);
270 void kvm_vgic_vcpu_early_init(struct kvm_vcpu
*vcpu
);
271 void kvm_vgic_vcpu_destroy(struct kvm_vcpu
*vcpu
);
272 int kvm_vgic_map_resources(struct kvm
*kvm
);
273 int kvm_vgic_hyp_init(void);
275 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int intid
,
277 int kvm_vgic_inject_mapped_irq(struct kvm
*kvm
, int cpuid
, unsigned int intid
,
279 int kvm_vgic_map_phys_irq(struct kvm_vcpu
*vcpu
, u32 virt_irq
, u32 phys_irq
);
280 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu
*vcpu
, unsigned int virt_irq
);
281 bool kvm_vgic_map_is_active(struct kvm_vcpu
*vcpu
, unsigned int virt_irq
);
283 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
);
285 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
286 #define vgic_initialized(k) ((k)->arch.vgic.initialized)
287 #define vgic_ready(k) ((k)->arch.vgic.ready)
288 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
289 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
291 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu
*vcpu
);
292 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
);
293 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
);
295 #ifdef CONFIG_KVM_ARM_VGIC_V3
296 void vgic_v3_dispatch_sgi(struct kvm_vcpu
*vcpu
, u64 reg
);
298 static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu
*vcpu
, u64 reg
)
304 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
306 * The host's GIC naturally limits the maximum amount of VCPUs a guest
309 static inline int kvm_vgic_get_max_vcpus(void)
311 return kvm_vgic_global_state
.max_gic_vcpus
;
314 int kvm_send_userspace_msi(struct kvm
*kvm
, struct kvm_msi
*msi
);
316 #endif /* __KVM_ARM_VGIC_H */