include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17  */
  18
  19 #ifndef __ASM_ARM_KVM_VGIC_H
  20 #define __ASM_ARM_KVM_VGIC_H
  21
  22 #include <linux/kernel.h>
  23 #include <linux/kvm.h>
  24 #include <linux/irqreturn.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/types.h>
  27 #include <linux/irqchip/arm-gic.h>
  28
  29 #define VGIC_NR_IRQS            256
  30 #define VGIC_NR_SGIS            16
  31 #define VGIC_NR_PPIS            16
  32 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  33 #define VGIC_NR_SHARED_IRQS     (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
  34 #define VGIC_MAX_CPUS           KVM_MAX_VCPUS
  35
  36 #define VGIC_V2_MAX_LRS         (1 << 6)
  37
  38 /* Sanity checks... */
  39 #if (VGIC_MAX_CPUS > 8)
  40 #error  Invalid number of CPU interfaces
  41 #endif
  42
  43 #if (VGIC_NR_IRQS & 31)
  44 #error "VGIC_NR_IRQS must be a multiple of 32"
  45 #endif
  46
  47 #if (VGIC_NR_IRQS > 1024)
  48 #error "VGIC_NR_IRQS must be <= 1024"
  49 #endif
  50
  51 /*
  52  * The GIC distributor registers describing interrupts have two parts:
  53  * - 32 per-CPU interrupts (SGI + PPI)
  54  * - a bunch of shared interrupts (SPI)
  55  */
  56 struct vgic_bitmap {
  57         union {
  58                 u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
  59                 DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
  60         } percpu[VGIC_MAX_CPUS];
  61         union {
  62                 u32 reg[VGIC_NR_SHARED_IRQS / 32];
  63                 DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
  64         } shared;
  65 };
  66
  67 struct vgic_bytemap {
  68         u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
  69         u32 shared[VGIC_NR_SHARED_IRQS  / 4];
  70 };
  71
  72 struct kvm_vcpu;
  73
  74 #define LR_STATE_PENDING        (1 << 0)
  75 #define LR_STATE_ACTIVE         (1 << 1)
  76 #define LR_STATE_MASK           (3 << 0)
  77 #define LR_EOI_INT              (1 << 2)
  78
  79 struct vgic_lr {
  80         u16     irq;
  81         u8      source;
  82         u8      state;
  83 };
  84
  85 struct vgic_vmcr {
  86         u32     ctlr;
  87         u32     abpr;
  88         u32     bpr;
  89         u32     pmr;
  90 };
  91
  92 struct vgic_ops {
  93         struct vgic_lr  (*get_lr)(const struct kvm_vcpu *, int);
  94         void    (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
  95         void    (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
  96         u64     (*get_elrsr)(const struct kvm_vcpu *vcpu);
  97         u64     (*get_eisr)(const struct kvm_vcpu *vcpu);
  98         u32     (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
  99         void    (*enable_underflow)(struct kvm_vcpu *vcpu);
 100         void    (*disable_underflow)(struct kvm_vcpu *vcpu);
 101         void    (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 102         void    (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 103         void    (*enable)(struct kvm_vcpu *vcpu);
 104 };
 105
 106 struct vgic_params {
 107         /* Physical address of vgic virtual cpu interface */
 108         phys_addr_t     vcpu_base;
 109         /* Number of list registers */
 110         u32             nr_lr;
 111         /* Interrupt number */
 112         unsigned int    maint_irq;
 113         /* Virtual control interface base address */
 114         void __iomem    *vctrl_base;
 115 };
 116
 117 struct vgic_dist {
 118 #ifdef CONFIG_KVM_ARM_VGIC
 119         spinlock_t              lock;
 120         bool                    ready;
 121
 122         /* Virtual control interface mapping */
 123         void __iomem            *vctrl_base;
 124
 125         /* Distributor and vcpu interface mapping in the guest */
 126         phys_addr_t             vgic_dist_base;
 127         phys_addr_t             vgic_cpu_base;
 128
 129         /* Distributor enabled */
 130         u32                     enabled;
 131
 132         /* Interrupt enabled (one bit per IRQ) */
 133         struct vgic_bitmap      irq_enabled;
 134
 135         /* Interrupt 'pin' level */
 136         struct vgic_bitmap      irq_state;
 137
 138         /* Level-triggered interrupt in progress */
 139         struct vgic_bitmap      irq_active;
 140
 141         /* Interrupt priority. Not used yet. */
 142         struct vgic_bytemap     irq_priority;
 143
 144         /* Level/edge triggered */
 145         struct vgic_bitmap      irq_cfg;
 146
 147         /* Source CPU per SGI and target CPU */
 148         u8                      irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
 149
 150         /* Target CPU for each IRQ */
 151         u8                      irq_spi_cpu[VGIC_NR_SHARED_IRQS];
 152         struct vgic_bitmap      irq_spi_target[VGIC_MAX_CPUS];
 153
 154         /* Bitmap indicating which CPU has something pending */
 155         unsigned long           irq_pending_on_cpu;
 156 #endif
 157 };
 158
 159 struct vgic_v2_cpu_if {
 160         u32             vgic_hcr;
 161         u32             vgic_vmcr;
 162         u32             vgic_misr;      /* Saved only */
 163         u32             vgic_eisr[2];   /* Saved only */
 164         u32             vgic_elrsr[2];  /* Saved only */
 165         u32             vgic_apr;
 166         u32             vgic_lr[VGIC_V2_MAX_LRS];
 167 };
 168
 169 struct vgic_cpu {
 170 #ifdef CONFIG_KVM_ARM_VGIC
 171         /* per IRQ to LR mapping */
 172         u8              vgic_irq_lr_map[VGIC_NR_IRQS];
 173
 174         /* Pending interrupts on this VCPU */
 175         DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
 176         DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
 177
 178         /* Bitmap of used/free list registers */
 179         DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
 180
 181         /* Number of list registers on this CPU */
 182         int             nr_lr;
 183
 184         /* CPU vif control registers for world switch */
 185         union {
 186                 struct vgic_v2_cpu_if   vgic_v2;
 187         };
 188 #endif
 189 };
 190
 191 #define LR_EMPTY        0xff
 192
 193 #define INT_STATUS_EOI          (1 << 0)
 194 #define INT_STATUS_UNDERFLOW    (1 << 1)
 195
 196 struct kvm;
 197 struct kvm_vcpu;
 198 struct kvm_run;
 199 struct kvm_exit_mmio;
 200
 201 #ifdef CONFIG_KVM_ARM_VGIC
 202 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 203 int kvm_vgic_hyp_init(void);
 204 int kvm_vgic_init(struct kvm *kvm);
 205 int kvm_vgic_create(struct kvm *kvm);
 206 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
 207 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 208 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 209 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
 210                         bool level);
 211 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 212 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
 213                       struct kvm_exit_mmio *mmio);
 214
 215 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.vctrl_base))
 216 #define vgic_initialized(k)     ((k)->arch.vgic.ready)
 217
 218 int vgic_v2_probe(struct device_node *vgic_node,
 219                   const struct vgic_ops **ops,
 220                   const struct vgic_params **params);
 221
 222 #else
 223 static inline int kvm_vgic_hyp_init(void)
 224 {
 225         return 0;
 226 }
 227
 228 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
 229 {
 230         return 0;
 231 }
 232
 233 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
 234 {
 235         return -ENXIO;
 236 }
 237
 238 static inline int kvm_vgic_init(struct kvm *kvm)
 239 {
 240         return 0;
 241 }
 242
 243 static inline int kvm_vgic_create(struct kvm *kvm)
 244 {
 245         return 0;
 246 }
 247
 248 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
 249 {
 250         return 0;
 251 }
 252
 253 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
 254 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
 255
 256 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
 257                                       unsigned int irq_num, bool level)
 258 {
 259         return 0;
 260 }
 261
 262 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
 263 {
 264         return 0;
 265 }
 266
 267 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
 268                                     struct kvm_exit_mmio *mmio)
 269 {
 270         return false;
 271 }
 272
 273 static inline int irqchip_in_kernel(struct kvm *kvm)
 274 {
 275         return 0;
 276 }
 277
 278 static inline bool vgic_initialized(struct kvm *kvm)
 279 {
 280         return true;
 281 }
 282 #endif
 283
 284 #endif