include/linux/amba/pl08x.h

   1 /*
   2  * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
   3  *
   4  * Copyright (C) 2005 ARM Ltd
   5  * Copyright (C) 2010 ST-Ericsson SA
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * pl08x information required by platform code
  12  *
  13  * Please credit ARM.com
  14  * Documentation: ARM DDI 0196D
  15  */
  16
  17 #ifndef AMBA_PL08X_H
  18 #define AMBA_PL08X_H
  19
  20 /* We need sizes of structs from this header */
  21 #include <linux/dmaengine.h>
  22 #include <linux/interrupt.h>
  23
  24 struct pl08x_lli;
  25 struct pl08x_driver_data;
  26
  27 /* Bitmasks for selecting AHB ports for DMA transfers */
  28 enum {
  29         PL08X_AHB1 = (1 << 0),
  30         PL08X_AHB2 = (1 << 1)
  31 };
  32
  33 /**
  34  * struct pl08x_channel_data - data structure to pass info between
  35  * platform and PL08x driver regarding channel configuration
  36  * @bus_id: name of this device channel, not just a device name since
  37  * devices may have more than one channel e.g. "foo_tx"
  38  * @min_signal: the minimum DMA signal number to be muxed in for this
  39  * channel (for platforms supporting muxed signals). If you have
  40  * static assignments, make sure this is set to the assigned signal
  41  * number, PL08x have 16 possible signals in number 0 thru 15 so
  42  * when these are not enough they often get muxed (in hardware)
  43  * disabling simultaneous use of the same channel for two devices.
  44  * @max_signal: the maximum DMA signal number to be muxed in for
  45  * the channel. Set to the same as min_signal for
  46  * devices with static assignments
  47  * @muxval: a number usually used to poke into some mux regiser to
  48  * mux in the signal to this channel
  49  * @cctl_opt: default options for the channel control register
  50  * @addr: source/target address in physical memory for this DMA channel,
  51  * can be the address of a FIFO register for burst requests for example.
  52  * This can be left undefined if the PrimeCell API is used for configuring
  53  * this.
  54  * @single: the device connected to this channel will request single DMA
  55  * transfers, not bursts. (Bursts are default.)
  56  * @periph_buses: the device connected to this channel is accessible via
  57  * these buses (use PL08X_AHB1 | PL08X_AHB2).
  58  */
  59 struct pl08x_channel_data {
  60         char *bus_id;
  61         int min_signal;
  62         int max_signal;
  63         u32 muxval;
  64         u32 cctl;
  65         dma_addr_t addr;
  66         bool single;
  67         u8 periph_buses;
  68 };
  69
  70 /**
  71  * Struct pl08x_bus_data - information of source or destination
  72  * busses for a transfer
  73  * @addr: current address
  74  * @maxwidth: the maximum width of a transfer on this bus
  75  * @buswidth: the width of this bus in bytes: 1, 2 or 4
  76  */
  77 struct pl08x_bus_data {
  78         dma_addr_t addr;
  79         u8 maxwidth;
  80         u8 buswidth;
  81 };
  82
  83 /**
  84  * struct pl08x_phy_chan - holder for the physical channels
  85  * @id: physical index to this channel
  86  * @lock: a lock to use when altering an instance of this struct
  87  * @signal: the physical signal (aka channel) serving this physical channel
  88  * right now
  89  * @serving: the virtual channel currently being served by this physical
  90  * channel
  91  * @locked: channel unavailable for the system, e.g. dedicated to secure
  92  * world
  93  */
  94 struct pl08x_phy_chan {
  95         unsigned int id;
  96         void __iomem *base;
  97         spinlock_t lock;
  98         int signal;
  99         struct pl08x_dma_chan *serving;
 100         bool locked;
 101 };
 102
 103 /**
 104  * struct pl08x_sg - structure containing data per sg
 105  * @src_addr: src address of sg
 106  * @dst_addr: dst address of sg
 107  * @len: transfer len in bytes
 108  * @node: node for txd's dsg_list
 109  */
 110 struct pl08x_sg {
 111         dma_addr_t src_addr;
 112         dma_addr_t dst_addr;
 113         size_t len;
 114         struct list_head node;
 115 };
 116
 117 /**
 118  * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
 119  * @tx: async tx descriptor
 120  * @node: node for txd list for channels
 121  * @dsg_list: list of children sg's
 122  * @direction: direction of transfer
 123  * @llis_bus: DMA memory address (physical) start for the LLIs
 124  * @llis_va: virtual memory address start for the LLIs
 125  * @cctl: control reg values for current txd
 126  * @ccfg: config reg values for current txd
 127  */
 128 struct pl08x_txd {
 129         struct dma_async_tx_descriptor tx;
 130         struct list_head node;
 131         struct list_head dsg_list;
 132         enum dma_transfer_direction direction;
 133         dma_addr_t llis_bus;
 134         struct pl08x_lli *llis_va;
 135         /* Default cctl value for LLIs */
 136         u32 cctl;
 137         /*
 138          * Settings to be put into the physical channel when we
 139          * trigger this txd.  Other registers are in llis_va[0].
 140          */
 141         u32 ccfg;
 142 };
 143
 144 /**
 145  * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
 146  * states
 147  * @PL08X_CHAN_IDLE: the channel is idle
 148  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
 149  * channel and is running a transfer on it
 150  * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
 151  * channel, but the transfer is currently paused
 152  * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
 153  * channel to become available (only pertains to memcpy channels)
 154  */
 155 enum pl08x_dma_chan_state {
 156         PL08X_CHAN_IDLE,
 157         PL08X_CHAN_RUNNING,
 158         PL08X_CHAN_PAUSED,
 159         PL08X_CHAN_WAITING,
 160 };
 161
 162 /**
 163  * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
 164  * @chan: wrappped abstract channel
 165  * @phychan: the physical channel utilized by this channel, if there is one
 166  * @phychan_hold: if non-zero, hold on to the physical channel even if we
 167  * have no pending entries
 168  * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
 169  * @name: name of channel
 170  * @cd: channel platform data
 171  * @runtime_addr: address for RX/TX according to the runtime config
 172  * @runtime_direction: current direction of this channel according to
 173  * runtime config
 174  * @pend_list: queued transactions pending on this channel
 175  * @at: active transaction on this channel
 176  * @lock: a lock for this channel data
 177  * @host: a pointer to the host (internal use)
 178  * @state: whether the channel is idle, paused, running etc
 179  * @slave: whether this channel is a device (slave) or for memcpy
 180  * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
 181  * channels. Fill with 'true' if peripheral should be flow controller. Direction
 182  * will be selected at Runtime.
 183  * @waiting: a TX descriptor on this channel which is waiting for a physical
 184  * channel to become available
 185  */
 186 struct pl08x_dma_chan {
 187         struct dma_chan chan;
 188         struct pl08x_phy_chan *phychan;
 189         int phychan_hold;
 190         struct tasklet_struct tasklet;
 191         char *name;
 192         const struct pl08x_channel_data *cd;
 193         dma_addr_t src_addr;
 194         dma_addr_t dst_addr;
 195         u32 src_cctl;
 196         u32 dst_cctl;
 197         enum dma_transfer_direction runtime_direction;
 198         struct list_head pend_list;
 199         struct pl08x_txd *at;
 200         spinlock_t lock;
 201         struct pl08x_driver_data *host;
 202         enum pl08x_dma_chan_state state;
 203         bool slave;
 204         bool device_fc;
 205         struct pl08x_txd *waiting;
 206 };
 207
 208 /**
 209  * struct pl08x_platform_data - the platform configuration for the PL08x
 210  * PrimeCells.
 211  * @slave_channels: the channels defined for the different devices on the
 212  * platform, all inclusive, including multiplexed channels. The available
 213  * physical channels will be multiplexed around these signals as they are
 214  * requested, just enumerate all possible channels.
 215  * @get_signal: request a physical signal to be used for a DMA transfer
 216  * immediately: if there is some multiplexing or similar blocking the use
 217  * of the channel the transfer can be denied by returning less than zero,
 218  * else it returns the allocated signal number
 219  * @put_signal: indicate to the platform that this physical signal is not
 220  * running any DMA transfer and multiplexing can be recycled
 221  * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
 222  * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
 223  */
 224 struct pl08x_platform_data {
 225         const struct pl08x_channel_data *slave_channels;
 226         unsigned int num_slave_channels;
 227         struct pl08x_channel_data memcpy_channel;
 228         int (*get_signal)(const struct pl08x_channel_data *);
 229         void (*put_signal)(const struct pl08x_channel_data *, int);
 230         u8 lli_buses;
 231         u8 mem_buses;
 232 };
 233
 234 #ifdef CONFIG_AMBA_PL08X
 235 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
 236 #else
 237 static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 238 {
 239         return false;
 240 }
 241 #endif
 242
 243 #endif  /* AMBA_PL08X_H */