include/linux/amba/pl08x.h

   1 /*
   2  * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
   3  *
   4  * Copyright (C) 2005 ARM Ltd
   5  * Copyright (C) 2010 ST-Ericsson SA
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * pl08x information required by platform code
  12  *
  13  * Please credit ARM.com
  14  * Documentation: ARM DDI 0196D
  15  *
  16  */
  17
  18 #ifndef AMBA_PL08X_H
  19 #define AMBA_PL08X_H
  20
  21 /* We need sizes of structs from this header */
  22 #include <linux/dmaengine.h>
  23 #include <linux/interrupt.h>
  24
  25 struct pl08x_lli;
  26 struct pl08x_driver_data;
  27
  28 /**
  29  * struct pl08x_channel_data - data structure to pass info between
  30  * platform and PL08x driver regarding channel configuration
  31  * @bus_id: name of this device channel, not just a device name since
  32  * devices may have more than one channel e.g. "foo_tx"
  33  * @min_signal: the minimum DMA signal number to be muxed in for this
  34  * channel (for platforms supporting muxed signals). If you have
  35  * static assignments, make sure this is set to the assigned signal
  36  * number, PL08x have 16 possible signals in number 0 thru 15 so
  37  * when these are not enough they often get muxed (in hardware)
  38  * disabling simultaneous use of the same channel for two devices.
  39  * @max_signal: the maximum DMA signal number to be muxed in for
  40  * the channel. Set to the same as min_signal for
  41  * devices with static assignments
  42  * @muxval: a number usually used to poke into some mux regiser to
  43  * mux in the signal to this channel
  44  * @cctl_opt: default options for the channel control register
  45  * @addr: source/target address in physical memory for this DMA channel,
  46  * can be the address of a FIFO register for burst requests for example.
  47  * This can be left undefined if the PrimeCell API is used for configuring
  48  * this.
  49  * @circular_buffer: whether the buffer passed in is circular and
  50  * shall simply be looped round round (like a record baby round
  51  * round round round)
  52  * @single: the device connected to this channel will request single
  53  * DMA transfers, not bursts. (Bursts are default.)
  54  */
  55 struct pl08x_channel_data {
  56         char *bus_id;
  57         int min_signal;
  58         int max_signal;
  59         u32 muxval;
  60         u32 cctl;
  61         dma_addr_t addr;
  62         bool circular_buffer;
  63         bool single;
  64 };
  65
  66 /**
  67  * Struct pl08x_bus_data - information of source or destination
  68  * busses for a transfer
  69  * @addr: current address
  70  * @maxwidth: the maximum width of a transfer on this bus
  71  * @buswidth: the width of this bus in bytes: 1, 2 or 4
  72  * @fill_bytes: bytes required to fill to the next bus memory
  73  * boundary
  74  */
  75 struct pl08x_bus_data {
  76         dma_addr_t addr;
  77         u8 maxwidth;
  78         u8 buswidth;
  79         size_t fill_bytes;
  80 };
  81
  82 /**
  83  * struct pl08x_phy_chan - holder for the physical channels
  84  * @id: physical index to this channel
  85  * @lock: a lock to use when altering an instance of this struct
  86  * @signal: the physical signal (aka channel) serving this
  87  * physical channel right now
  88  * @serving: the virtual channel currently being served by this
  89  * physical channel
  90  */
  91 struct pl08x_phy_chan {
  92         unsigned int id;
  93         void __iomem *base;
  94         spinlock_t lock;
  95         int signal;
  96         struct pl08x_dma_chan *serving;
  97 };
  98
  99 /**
 100  * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
 101  * @llis_bus: DMA memory address (physical) start for the LLIs
 102  * @llis_va: virtual memory address start for the LLIs
 103  */
 104 struct pl08x_txd {
 105         struct dma_async_tx_descriptor tx;
 106         struct list_head node;
 107         enum dma_data_direction direction;
 108         struct pl08x_bus_data srcbus;
 109         struct pl08x_bus_data dstbus;
 110         size_t len;
 111         dma_addr_t llis_bus;
 112         void *llis_va;
 113         bool active;
 114         /* Default cctl value for LLIs */
 115         u32 cctl;
 116         /*
 117          * Settings to be put into the physical channel when we
 118          * trigger this txd.  Other registers are in llis_va[0].
 119          */
 120         u32 ccfg;
 121 };
 122
 123 /**
 124  * struct pl08x_dma_chan_state - holds the PL08x specific virtual
 125  * channel states
 126  * @PL08X_CHAN_IDLE: the channel is idle
 127  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
 128  * channel and is running a transfer on it
 129  * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
 130  * channel, but the transfer is currently paused
 131  * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
 132  * channel to become available (only pertains to memcpy channels)
 133  */
 134 enum pl08x_dma_chan_state {
 135         PL08X_CHAN_IDLE,
 136         PL08X_CHAN_RUNNING,
 137         PL08X_CHAN_PAUSED,
 138         PL08X_CHAN_WAITING,
 139 };
 140
 141 /**
 142  * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
 143  * @chan: wrappped abstract channel
 144  * @phychan: the physical channel utilized by this channel, if there is one
 145  * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
 146  * @name: name of channel
 147  * @cd: channel platform data
 148  * @runtime_addr: address for RX/TX according to the runtime config
 149  * @runtime_direction: current direction of this channel according to
 150  * runtime config
 151  * @lc: last completed transaction on this channel
 152  * @desc_list: queued transactions pending on this channel
 153  * @at: active transaction on this channel
 154  * @lockflags: sometimes we let a lock last between two function calls,
 155  * especially prep/submit, and then we need to store the IRQ flags
 156  * in the channel state, here
 157  * @lock: a lock for this channel data
 158  * @host: a pointer to the host (internal use)
 159  * @state: whether the channel is idle, paused, running etc
 160  * @slave: whether this channel is a device (slave) or for memcpy
 161  * @waiting: a TX descriptor on this channel which is waiting for
 162  * a physical channel to become available
 163  */
 164 struct pl08x_dma_chan {
 165         struct dma_chan chan;
 166         struct pl08x_phy_chan *phychan;
 167         struct tasklet_struct tasklet;
 168         char *name;
 169         struct pl08x_channel_data *cd;
 170         dma_addr_t runtime_addr;
 171         enum dma_data_direction runtime_direction;
 172         dma_cookie_t lc;
 173         struct list_head desc_list;
 174         struct pl08x_txd *at;
 175         unsigned long lockflags;
 176         spinlock_t lock;
 177         struct pl08x_driver_data *host;
 178         enum pl08x_dma_chan_state state;
 179         bool slave;
 180         struct pl08x_txd *waiting;
 181 };
 182
 183 /**
 184  * struct pl08x_platform_data - the platform configuration for the
 185  * PL08x PrimeCells.
 186  * @slave_channels: the channels defined for the different devices on the
 187  * platform, all inclusive, including multiplexed channels. The available
 188  * physical channels will be multiplexed around these signals as they
 189  * are requested, just enumerate all possible channels.
 190  * @get_signal: request a physical signal to be used for a DMA
 191  * transfer immediately: if there is some multiplexing or similar blocking
 192  * the use of the channel the transfer can be denied by returning
 193  * less than zero, else it returns the allocated signal number
 194  * @put_signal: indicate to the platform that this physical signal is not
 195  * running any DMA transfer and multiplexing can be recycled
 196  * @bus_bit_lli: Bit[0] of the address indicated which AHB bus master the
 197  * LLI addresses are on 0/1 Master 1/2.
 198  */
 199 struct pl08x_platform_data {
 200         struct pl08x_channel_data *slave_channels;
 201         unsigned int num_slave_channels;
 202         struct pl08x_channel_data memcpy_channel;
 203         int (*get_signal)(struct pl08x_dma_chan *);
 204         void (*put_signal)(struct pl08x_dma_chan *);
 205 };
 206
 207 #ifdef CONFIG_AMBA_PL08X
 208 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
 209 #else
 210 static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 211 {
 212         return false;
 213 }
 214 #endif
 215
 216 #endif  /* AMBA_PL08X_H */