include/linux/clk/ti.h

   1 /*
   2  * TI clock drivers support
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #ifndef __LINUX_CLK_TI_H__
  16 #define __LINUX_CLK_TI_H__
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/clkdev.h>
  20
  21 /**
  22  * struct dpll_data - DPLL registers and integration data
  23  * @mult_div1_reg: register containing the DPLL M and N bitfields
  24  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
  25  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
  26  * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
  27  * @clk_ref: struct clk_hw pointer to the clock's reference clock input
  28  * @control_reg: register containing the DPLL mode bitfield
  29  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
  30  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
  31  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
  32  * @last_rounded_m4xen: cache of the last M4X result of
  33  *                      omap4_dpll_regm4xen_round_rate()
  34  * @last_rounded_lpmode: cache of the last lpmode result of
  35  *                       omap4_dpll_lpmode_recalc()
  36  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
  37  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
  38  * @min_divider: minimum valid non-bypass divider value (actual)
  39  * @max_divider: maximum valid non-bypass divider value (actual)
  40  * @max_rate: maximum clock rate for the DPLL
  41  * @modes: possible values of @enable_mask
  42  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
  43  * @idlest_reg: register containing the DPLL idle status bitfield
  44  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
  45  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
  46  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
  47  * @dcc_rate: rate atleast which DCC @dcc_mask must be set
  48  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
  49  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
  50  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
  51  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
  52  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
  53  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
  54  * @flags: DPLL type/features (see below)
  55  *
  56  * Possible values for @flags:
  57  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
  58  *
  59  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
  60  *
  61  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
  62  * correct to only have one @clk_bypass pointer.
  63  *
  64  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
  65  * @last_rounded_n) should be separated from the runtime-fixed fields
  66  * and placed into a different structure, so that the runtime-fixed data
  67  * can be placed into read-only space.
  68  */
  69 struct dpll_data {
  70         void __iomem            *mult_div1_reg;
  71         u32                     mult_mask;
  72         u32                     div1_mask;
  73         struct clk_hw           *clk_bypass;
  74         struct clk_hw           *clk_ref;
  75         void __iomem            *control_reg;
  76         u32                     enable_mask;
  77         unsigned long           last_rounded_rate;
  78         u16                     last_rounded_m;
  79         u8                      last_rounded_m4xen;
  80         u8                      last_rounded_lpmode;
  81         u16                     max_multiplier;
  82         u8                      last_rounded_n;
  83         u8                      min_divider;
  84         u16                     max_divider;
  85         unsigned long           max_rate;
  86         u8                      modes;
  87         void __iomem            *autoidle_reg;
  88         void __iomem            *idlest_reg;
  89         u32                     autoidle_mask;
  90         u32                     freqsel_mask;
  91         u32                     idlest_mask;
  92         u32                     dco_mask;
  93         u32                     sddiv_mask;
  94         u32                     dcc_mask;
  95         unsigned long           dcc_rate;
  96         u32                     lpmode_mask;
  97         u32                     m4xen_mask;
  98         u8                      auto_recal_bit;
  99         u8                      recal_en_bit;
 100         u8                      recal_st_bit;
 101         u8                      flags;
 102 };
 103
 104 struct clk_hw_omap;
 105
 106 /**
 107  * struct clk_hw_omap_ops - OMAP clk ops
 108  * @find_idlest: find idlest register information for a clock
 109  * @find_companion: find companion clock register information for a clock,
 110  *                  basically converts CM_ICLKEN* <-> CM_FCLKEN*
 111  * @allow_idle: enables autoidle hardware functionality for a clock
 112  * @deny_idle: prevent autoidle hardware functionality for a clock
 113  */
 114 struct clk_hw_omap_ops {
 115         void    (*find_idlest)(struct clk_hw_omap *oclk,
 116                                void __iomem **idlest_reg,
 117                                u8 *idlest_bit, u8 *idlest_val);
 118         void    (*find_companion)(struct clk_hw_omap *oclk,
 119                                   void __iomem **other_reg,
 120                                   u8 *other_bit);
 121         void    (*allow_idle)(struct clk_hw_omap *oclk);
 122         void    (*deny_idle)(struct clk_hw_omap *oclk);
 123 };
 124
 125 /**
 126  * struct clk_hw_omap - OMAP struct clk
 127  * @node: list_head connecting this clock into the full clock list
 128  * @enable_reg: register to write to enable the clock (see @enable_bit)
 129  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
 130  * @flags: see "struct clk.flags possibilities" above
 131  * @clksel_reg: for clksel clks, register va containing src/divisor select
 132  * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
 133  * @clksel: for clksel clks, pointer to struct clksel for this clock
 134  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
 135  * @clkdm_name: clockdomain name that this clock is contained in
 136  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
 137  * @ops: clock ops for this clock
 138  */
 139 struct clk_hw_omap {
 140         struct clk_hw           hw;
 141         struct list_head        node;
 142         unsigned long           fixed_rate;
 143         u8                      fixed_div;
 144         void __iomem            *enable_reg;
 145         u8                      enable_bit;
 146         u8                      flags;
 147         void __iomem            *clksel_reg;
 148         u32                     clksel_mask;
 149         const struct clksel     *clksel;
 150         struct dpll_data        *dpll_data;
 151         const char              *clkdm_name;
 152         struct clockdomain      *clkdm;
 153         const struct clk_hw_omap_ops    *ops;
 154 };
 155
 156 /*
 157  * struct clk_hw_omap.flags possibilities
 158  *
 159  * XXX document the rest of the clock flags here
 160  *
 161  * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
 162  *     with 32bit ops, by default OMAP1 uses 16bit ops.
 163  * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
 164  * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
 165  *     clock is put to no-idle mode.
 166  * ENABLE_ON_INIT: Clock is enabled on init.
 167  * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
 168  *     disable. This inverts the behavior making '0' enable and '1' disable.
 169  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
 170  *     bits share the same register.  This flag allows the
 171  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
 172  *     should be used.  This is a temporary solution - a better approach
 173  *     would be to associate clock type-specific data with the clock,
 174  *     similar to the struct dpll_data approach.
 175  * MEMMAP_ADDRESSING: Use memmap addressing to access clock registers.
 176  */
 177 #define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
 178 #define CLOCK_IDLE_CONTROL      (1 << 1)
 179 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
 180 #define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
 181 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
 182 #define CLOCK_CLKOUTX2          (1 << 5)
 183 #define MEMMAP_ADDRESSING       (1 << 6)
 184
 185 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
 186 #define DPLL_LOW_POWER_STOP     0x1
 187 #define DPLL_LOW_POWER_BYPASS   0x5
 188 #define DPLL_LOCKED             0x7
 189
 190 /* DPLL Type and DCO Selection Flags */
 191 #define DPLL_J_TYPE             0x1
 192
 193 /* Static memmap indices */
 194 enum {
 195         TI_CLKM_CM = 0,
 196         TI_CLKM_CM2,
 197         TI_CLKM_PRM,
 198         TI_CLKM_SCRM,
 199         TI_CLKM_CTRL,
 200         TI_CLKM_PLLSS,
 201         CLK_MAX_MEMMAPS
 202 };
 203
 204 /**
 205  * struct clk_omap_reg - OMAP register declaration
 206  * @offset: offset from the master IP module base address
 207  * @index: index of the master IP module
 208  */
 209 struct clk_omap_reg {
 210         u16 offset;
 211         u16 index;
 212 };
 213
 214 /**
 215  * struct ti_clk_ll_ops - low-level ops for clocks
 216  * @clk_readl: pointer to register read function
 217  * @clk_writel: pointer to register write function
 218  * @clkdm_clk_enable: pointer to clockdomain enable function
 219  * @clkdm_clk_disable: pointer to clockdomain disable function
 220  * @cm_wait_module_ready: pointer to CM module wait ready function
 221  * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
 222  *
 223  * Low-level ops are generally used by the basic clock types (clk-gate,
 224  * clk-mux, clk-divider etc.) to provide support for various low-level
 225  * hadrware interfaces (direct MMIO, regmap etc.), and is initialized
 226  * by board code. Low-level ops also contain some other platform specific
 227  * operations not provided directly by clock drivers.
 228  */
 229 struct ti_clk_ll_ops {
 230         u32     (*clk_readl)(void __iomem *reg);
 231         void    (*clk_writel)(u32 val, void __iomem *reg);
 232         int     (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
 233         int     (*clkdm_clk_disable)(struct clockdomain *clkdm,
 234                                      struct clk *clk);
 235         int     (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
 236                                         u8 idlest_shift);
 237         int     (*cm_split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
 238                                        u8 *idlest_reg_id);
 239 };
 240
 241 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 242
 243 void omap2_init_clk_clkdm(struct clk_hw *clk);
 244 int omap2_clk_disable_autoidle_all(void);
 245 int omap2_clk_enable_autoidle_all(void);
 246 int omap2_clk_allow_idle(struct clk *clk);
 247 int omap2_clk_deny_idle(struct clk *clk);
 248 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
 249                                     unsigned long parent_rate);
 250 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
 251                              unsigned long parent_rate);
 252 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
 253 void omap2xxx_clkt_vps_init(void);
 254 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 255
 256 void ti_dt_clk_init_retry_clks(void);
 257 void ti_dt_clockdomains_setup(void);
 258 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
 259
 260 struct regmap;
 261
 262 int omap2_clk_provider_init(struct device_node *parent, int index,
 263                             struct regmap *syscon, void __iomem *mem);
 264 void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
 265
 266 int omap3430_dt_clk_init(void);
 267 int omap3630_dt_clk_init(void);
 268 int am35xx_dt_clk_init(void);
 269 int dm814x_dt_clk_init(void);
 270 int dm816x_dt_clk_init(void);
 271 int omap4xxx_dt_clk_init(void);
 272 int omap5xxx_dt_clk_init(void);
 273 int dra7xx_dt_clk_init(void);
 274 int am33xx_dt_clk_init(void);
 275 int am43xx_dt_clk_init(void);
 276 int omap2420_dt_clk_init(void);
 277 int omap2430_dt_clk_init(void);
 278
 279 struct ti_clk_features {
 280         u32 flags;
 281         long fint_min;
 282         long fint_max;
 283         long fint_band1_max;
 284         long fint_band2_min;
 285         u8 dpll_bypass_vals;
 286         u8 cm_idlest_val;
 287 };
 288
 289 #define TI_CLK_DPLL_HAS_FREQSEL                 BIT(0)
 290 #define TI_CLK_DPLL4_DENY_REPROGRAM             BIT(1)
 291 #define TI_CLK_DISABLE_CLKDM_CONTROL            BIT(2)
 292 #define TI_CLK_ERRATA_I810                      BIT(3)
 293
 294 void ti_clk_setup_features(struct ti_clk_features *features);
 295 const struct ti_clk_features *ti_clk_get_features(void);
 296
 297 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
 298
 299 #ifdef CONFIG_ATAGS
 300 int omap3430_clk_legacy_init(void);
 301 int omap3430es1_clk_legacy_init(void);
 302 int omap36xx_clk_legacy_init(void);
 303 int am35xx_clk_legacy_init(void);
 304 #else
 305 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
 306 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
 307 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
 308 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
 309 #endif
 310
 311
 312 #endif