2 * linux/include/linux/clk-provider.h
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
14 #include <linux/clk.h>
18 #ifdef CONFIG_COMMON_CLK
21 * flags used across common struct clk. these flags should only affect the
22 * top-level framework. custom flags for dealing with hardware specifics
23 * belong in struct clk_foo
25 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
26 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
27 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
28 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
29 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
30 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
31 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
32 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
33 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
40 * struct clk_ops - Callback operations for hardware clocks; these are to
41 * be provided by the clock implementation, and will be called by drivers
42 * through the clk_* api.
44 * @prepare: Prepare the clock for enabling. This must not return until
45 * the clock is fully prepared, and it's safe to call clk_enable.
46 * This callback is intended to allow clock implementations to
47 * do any initialisation that may sleep. Called with
50 * @unprepare: Release the clock from its prepared state. This will typically
51 * undo any work done in the @prepare callback. Called with
54 * @is_prepared: Queries the hardware to determine if the clock is prepared.
55 * This function is allowed to sleep. Optional, if this op is not
56 * set then the prepare count will be used.
58 * @unprepare_unused: Unprepare the clock atomically. Only called from
59 * clk_disable_unused for prepare clocks with special needs.
60 * Called with prepare mutex held. This function may sleep.
62 * @enable: Enable the clock atomically. This must not return until the
63 * clock is generating a valid clock signal, usable by consumer
64 * devices. Called with enable_lock held. This function must not
67 * @disable: Disable the clock atomically. Called with enable_lock held.
68 * This function must not sleep.
70 * @is_enabled: Queries the hardware to determine if the clock is enabled.
71 * This function must not sleep. Optional, if this op is not
72 * set then the enable count will be used.
74 * @disable_unused: Disable the clock atomically. Only called from
75 * clk_disable_unused for gate clocks with special needs.
76 * Called with enable_lock held. This function must not
79 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
80 * parent rate is an input parameter. It is up to the caller to
81 * ensure that the prepare_mutex is held across this call.
82 * Returns the calculated rate. Optional, but recommended - if
83 * this op is not set then clock rate will be initialized to 0.
85 * @round_rate: Given a target rate as input, returns the closest rate actually
86 * supported by the clock. The parent rate is an input/output
89 * @determine_rate: Given a target rate as input, returns the closest rate
90 * actually supported by the clock, and optionally the parent clock
91 * that should be used to provide the clock rate.
93 * @set_parent: Change the input source of this clock; for clocks with multiple
94 * possible parents specify a new parent by passing in the index
95 * as a u8 corresponding to the parent in either the .parent_names
96 * or .parents arrays. This function in affect translates an
97 * array index into the value programmed into the hardware.
98 * Returns 0 on success, -EERROR otherwise.
100 * @get_parent: Queries the hardware to determine the parent of a clock. The
101 * return value is a u8 which specifies the index corresponding to
102 * the parent clock. This index can be applied to either the
103 * .parent_names or .parents arrays. In short, this function
104 * translates the parent value read from hardware into an array
105 * index. Currently only called when the clock is initialized by
106 * __clk_init. This callback is mandatory for clocks with
107 * multiple parents. It is optional (and unnecessary) for clocks
108 * with 0 or 1 parents.
110 * @set_rate: Change the rate of this clock. The requested rate is specified
111 * by the second argument, which should typically be the return
112 * of .round_rate call. The third argument gives the parent rate
113 * which is likely helpful for most .set_rate implementation.
114 * Returns 0 on success, -EERROR otherwise.
116 * @set_rate_and_parent: Change the rate and the parent of this clock. The
117 * requested rate is specified by the second argument, which
118 * should typically be the return of .round_rate call. The
119 * third argument gives the parent rate which is likely helpful
120 * for most .set_rate_and_parent implementation. The fourth
121 * argument gives the parent index. This callback is optional (and
122 * unnecessary) for clocks with 0 or 1 parents as well as
123 * for clocks that can tolerate switching the rate and the parent
124 * separately via calls to .set_parent and .set_rate.
125 * Returns 0 on success, -EERROR otherwise.
127 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
128 * is expressed in ppb (parts per billion). The parent accuracy is
129 * an input parameter.
130 * Returns the calculated accuracy. Optional - if this op is not
131 * set then clock accuracy will be initialized to parent accuracy
132 * or 0 (perfect clock) if clock has no parent.
134 * @get_phase: Queries the hardware to get the current phase of a clock.
135 * Returned values are 0-359 degrees on success, negative
136 * error codes on failure.
138 * @set_phase: Shift the phase this clock signal in degrees specified
139 * by the second argument. Valid values for degrees are
140 * 0-359. Return 0 on success, otherwise -EERROR.
142 * @init: Perform platform-specific initialization magic.
143 * This is not not used by any of the basic clock types.
144 * Please consider other ways of solving initialization problems
145 * before using this callback, as its use is discouraged.
147 * @debug_init: Set up type-specific debugfs entries for this clock. This
148 * is called once, after the debugfs directory entry for this
149 * clock has been created. The dentry pointer representing that
150 * directory is provided as an argument. Called with
151 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
154 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
155 * implementations to split any work between atomic (enable) and sleepable
156 * (prepare) contexts. If enabling a clock requires code that might sleep,
157 * this must be done in clk_prepare. Clock enable code that will never be
158 * called in a sleepable context may be implemented in clk_enable.
160 * Typically, drivers will call clk_prepare when a clock may be needed later
161 * (eg. when a device is opened), and clk_enable when the clock is actually
162 * required (eg. from an interrupt). Note that clk_prepare MUST have been
163 * called before clk_enable.
166 int (*prepare
)(struct clk_hw
*hw
);
167 void (*unprepare
)(struct clk_hw
*hw
);
168 int (*is_prepared
)(struct clk_hw
*hw
);
169 void (*unprepare_unused
)(struct clk_hw
*hw
);
170 int (*enable
)(struct clk_hw
*hw
);
171 void (*disable
)(struct clk_hw
*hw
);
172 int (*is_enabled
)(struct clk_hw
*hw
);
173 void (*disable_unused
)(struct clk_hw
*hw
);
174 unsigned long (*recalc_rate
)(struct clk_hw
*hw
,
175 unsigned long parent_rate
);
176 long (*round_rate
)(struct clk_hw
*hw
, unsigned long rate
,
177 unsigned long *parent_rate
);
178 long (*determine_rate
)(struct clk_hw
*hw
,
180 unsigned long min_rate
,
181 unsigned long max_rate
,
182 unsigned long *best_parent_rate
,
183 struct clk_hw
**best_parent_hw
);
184 int (*set_parent
)(struct clk_hw
*hw
, u8 index
);
185 u8 (*get_parent
)(struct clk_hw
*hw
);
186 int (*set_rate
)(struct clk_hw
*hw
, unsigned long rate
,
187 unsigned long parent_rate
);
188 int (*set_rate_and_parent
)(struct clk_hw
*hw
,
190 unsigned long parent_rate
, u8 index
);
191 unsigned long (*recalc_accuracy
)(struct clk_hw
*hw
,
192 unsigned long parent_accuracy
);
193 int (*get_phase
)(struct clk_hw
*hw
);
194 int (*set_phase
)(struct clk_hw
*hw
, int degrees
);
195 void (*init
)(struct clk_hw
*hw
);
196 int (*debug_init
)(struct clk_hw
*hw
, struct dentry
*dentry
);
200 * struct clk_init_data - holds init data that's common to all clocks and is
201 * shared between the clock provider and the common clock framework.
204 * @ops: operations this clock supports
205 * @parent_names: array of string names for all possible parents
206 * @num_parents: number of possible parents
207 * @flags: framework-level hints and quirks
209 struct clk_init_data
{
211 const struct clk_ops
*ops
;
212 const char **parent_names
;
218 * struct clk_hw - handle for traversing from a struct clk to its corresponding
219 * hardware-specific structure. struct clk_hw should be declared within struct
220 * clk_foo and then referenced by the struct clk instance that uses struct
223 * @core: pointer to the struct clk_core instance that points back to this
224 * struct clk_hw instance
226 * @clk: pointer to the per-user struct clk instance that can be used to call
229 * @init: pointer to struct clk_init_data that contains the init data shared
230 * with the common clock framework.
233 struct clk_core
*core
;
235 const struct clk_init_data
*init
;
239 * DOC: Basic clock implementations common to many platforms
241 * Each basic clock hardware type is comprised of a structure describing the
242 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
243 * unique flags for that hardware type, a registration function and an
244 * alternative macro for static initialization
248 * struct clk_fixed_rate - fixed-rate clock
249 * @hw: handle between common and hardware-specific interfaces
250 * @fixed_rate: constant frequency of clock
252 struct clk_fixed_rate
{
254 unsigned long fixed_rate
;
255 unsigned long fixed_accuracy
;
259 extern const struct clk_ops clk_fixed_rate_ops
;
260 struct clk
*clk_register_fixed_rate(struct device
*dev
, const char *name
,
261 const char *parent_name
, unsigned long flags
,
262 unsigned long fixed_rate
);
263 struct clk
*clk_register_fixed_rate_with_accuracy(struct device
*dev
,
264 const char *name
, const char *parent_name
, unsigned long flags
,
265 unsigned long fixed_rate
, unsigned long fixed_accuracy
);
267 void of_fixed_clk_setup(struct device_node
*np
);
270 * struct clk_gate - gating clock
272 * @hw: handle between common and hardware-specific interfaces
273 * @reg: register controlling gate
274 * @bit_idx: single bit controlling gate
275 * @flags: hardware-specific flags
276 * @lock: register lock
278 * Clock which can gate its output. Implements .enable & .disable
281 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
282 * enable the clock. Setting this flag does the opposite: setting the bit
283 * disable the clock and clearing it enables the clock
284 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
285 * of this register, and mask of gate bits are in higher 16-bit of this
286 * register. While setting the gate bits, higher 16-bit should also be
287 * updated to indicate changing gate bits.
297 #define CLK_GATE_SET_TO_DISABLE BIT(0)
298 #define CLK_GATE_HIWORD_MASK BIT(1)
300 extern const struct clk_ops clk_gate_ops
;
301 struct clk
*clk_register_gate(struct device
*dev
, const char *name
,
302 const char *parent_name
, unsigned long flags
,
303 void __iomem
*reg
, u8 bit_idx
,
304 u8 clk_gate_flags
, spinlock_t
*lock
);
305 void clk_unregister_gate(struct clk
*clk
);
307 struct clk_div_table
{
313 * struct clk_divider - adjustable divider clock
315 * @hw: handle between common and hardware-specific interfaces
316 * @reg: register containing the divider
317 * @shift: shift to the divider bit field
318 * @width: width of the divider bit field
319 * @table: array of value/divider pairs, last entry should have div = 0
320 * @lock: register lock
322 * Clock with an adjustable divider affecting its output frequency. Implements
323 * .recalc_rate, .set_rate and .round_rate
326 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
327 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
328 * the raw value read from the register, with the value of zero considered
329 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
330 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
331 * the hardware register
332 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
333 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
334 * Some hardware implementations gracefully handle this case and allow a
335 * zero divisor by not modifying their input clock
336 * (divide by one / bypass).
337 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
338 * of this register, and mask of divider bits are in higher 16-bit of this
339 * register. While setting the divider bits, higher 16-bit should also be
340 * updated to indicate changing divider bits.
341 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
342 * to the closest integer instead of the up one.
343 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
344 * not be changed by the clock framework.
352 const struct clk_div_table
*table
;
356 #define CLK_DIVIDER_ONE_BASED BIT(0)
357 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
358 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
359 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
360 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
361 #define CLK_DIVIDER_READ_ONLY BIT(5)
363 extern const struct clk_ops clk_divider_ops
;
365 unsigned long divider_recalc_rate(struct clk_hw
*hw
, unsigned long parent_rate
,
366 unsigned int val
, const struct clk_div_table
*table
,
367 unsigned long flags
);
368 long divider_round_rate(struct clk_hw
*hw
, unsigned long rate
,
369 unsigned long *prate
, const struct clk_div_table
*table
,
370 u8 width
, unsigned long flags
);
371 int divider_get_val(unsigned long rate
, unsigned long parent_rate
,
372 const struct clk_div_table
*table
, u8 width
,
373 unsigned long flags
);
375 struct clk
*clk_register_divider(struct device
*dev
, const char *name
,
376 const char *parent_name
, unsigned long flags
,
377 void __iomem
*reg
, u8 shift
, u8 width
,
378 u8 clk_divider_flags
, spinlock_t
*lock
);
379 struct clk
*clk_register_divider_table(struct device
*dev
, const char *name
,
380 const char *parent_name
, unsigned long flags
,
381 void __iomem
*reg
, u8 shift
, u8 width
,
382 u8 clk_divider_flags
, const struct clk_div_table
*table
,
384 void clk_unregister_divider(struct clk
*clk
);
387 * struct clk_mux - multiplexer clock
389 * @hw: handle between common and hardware-specific interfaces
390 * @reg: register controlling multiplexer
391 * @shift: shift to multiplexer bit field
392 * @width: width of mutliplexer bit field
393 * @flags: hardware-specific flags
394 * @lock: register lock
396 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
400 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
401 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
402 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
403 * register, and mask of mux bits are in higher 16-bit of this register.
404 * While setting the mux bits, higher 16-bit should also be updated to
405 * indicate changing mux bits.
406 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
419 #define CLK_MUX_INDEX_ONE BIT(0)
420 #define CLK_MUX_INDEX_BIT BIT(1)
421 #define CLK_MUX_HIWORD_MASK BIT(2)
422 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
423 #define CLK_MUX_ROUND_CLOSEST BIT(4)
425 extern const struct clk_ops clk_mux_ops
;
426 extern const struct clk_ops clk_mux_ro_ops
;
428 struct clk
*clk_register_mux(struct device
*dev
, const char *name
,
429 const char **parent_names
, u8 num_parents
, unsigned long flags
,
430 void __iomem
*reg
, u8 shift
, u8 width
,
431 u8 clk_mux_flags
, spinlock_t
*lock
);
433 struct clk
*clk_register_mux_table(struct device
*dev
, const char *name
,
434 const char **parent_names
, u8 num_parents
, unsigned long flags
,
435 void __iomem
*reg
, u8 shift
, u32 mask
,
436 u8 clk_mux_flags
, u32
*table
, spinlock_t
*lock
);
438 void clk_unregister_mux(struct clk
*clk
);
440 void of_fixed_factor_clk_setup(struct device_node
*node
);
443 * struct clk_fixed_factor - fixed multiplier and divider clock
445 * @hw: handle between common and hardware-specific interfaces
449 * Clock with a fixed multiplier and divider. The output frequency is the
450 * parent clock rate divided by div and multiplied by mult.
451 * Implements .recalc_rate, .set_rate and .round_rate
454 struct clk_fixed_factor
{
460 extern struct clk_ops clk_fixed_factor_ops
;
461 struct clk
*clk_register_fixed_factor(struct device
*dev
, const char *name
,
462 const char *parent_name
, unsigned long flags
,
463 unsigned int mult
, unsigned int div
);
466 * struct clk_fractional_divider - adjustable fractional divider clock
468 * @hw: handle between common and hardware-specific interfaces
469 * @reg: register containing the divider
470 * @mshift: shift to the numerator bit field
471 * @mwidth: width of the numerator bit field
472 * @nshift: shift to the denominator bit field
473 * @nwidth: width of the denominator bit field
474 * @lock: register lock
476 * Clock with adjustable fractional divider affecting its output frequency.
479 struct clk_fractional_divider
{
490 extern const struct clk_ops clk_fractional_divider_ops
;
491 struct clk
*clk_register_fractional_divider(struct device
*dev
,
492 const char *name
, const char *parent_name
, unsigned long flags
,
493 void __iomem
*reg
, u8 mshift
, u8 mwidth
, u8 nshift
, u8 nwidth
,
494 u8 clk_divider_flags
, spinlock_t
*lock
);
497 * struct clk_composite - aggregate clock of mux, divider and gate clocks
499 * @hw: handle between common and hardware-specific interfaces
500 * @mux_hw: handle between composite and hardware-specific mux clock
501 * @rate_hw: handle between composite and hardware-specific rate clock
502 * @gate_hw: handle between composite and hardware-specific gate clock
503 * @mux_ops: clock ops for mux
504 * @rate_ops: clock ops for rate
505 * @gate_ops: clock ops for gate
507 struct clk_composite
{
511 struct clk_hw
*mux_hw
;
512 struct clk_hw
*rate_hw
;
513 struct clk_hw
*gate_hw
;
515 const struct clk_ops
*mux_ops
;
516 const struct clk_ops
*rate_ops
;
517 const struct clk_ops
*gate_ops
;
520 struct clk
*clk_register_composite(struct device
*dev
, const char *name
,
521 const char **parent_names
, int num_parents
,
522 struct clk_hw
*mux_hw
, const struct clk_ops
*mux_ops
,
523 struct clk_hw
*rate_hw
, const struct clk_ops
*rate_ops
,
524 struct clk_hw
*gate_hw
, const struct clk_ops
*gate_ops
,
525 unsigned long flags
);
528 * struct clk_gpio_gate - gpio gated clock
530 * @hw: handle between common and hardware-specific interfaces
531 * @gpiod: gpio descriptor
533 * Clock with a gpio control for enabling and disabling the parent clock.
534 * Implements .enable, .disable and .is_enabled
539 struct gpio_desc
*gpiod
;
542 extern const struct clk_ops clk_gpio_gate_ops
;
543 struct clk
*clk_register_gpio_gate(struct device
*dev
, const char *name
,
544 const char *parent_name
, struct gpio_desc
*gpio
,
545 unsigned long flags
);
547 void of_gpio_clk_gate_setup(struct device_node
*node
);
550 * clk_register - allocate a new clock, register it and return an opaque cookie
551 * @dev: device that is registering this clock
552 * @hw: link to hardware-specific clock data
554 * clk_register is the primary interface for populating the clock tree with new
555 * clock nodes. It returns a pointer to the newly allocated struct clk which
556 * cannot be dereferenced by driver code but may be used in conjuction with the
557 * rest of the clock API. In the event of an error clk_register will return an
558 * error code; drivers must test for an error code after calling clk_register.
560 struct clk
*clk_register(struct device
*dev
, struct clk_hw
*hw
);
561 struct clk
*devm_clk_register(struct device
*dev
, struct clk_hw
*hw
);
563 void clk_unregister(struct clk
*clk
);
564 void devm_clk_unregister(struct device
*dev
, struct clk
*clk
);
566 /* helper functions */
567 const char *__clk_get_name(struct clk
*clk
);
568 struct clk_hw
*__clk_get_hw(struct clk
*clk
);
569 u8
__clk_get_num_parents(struct clk
*clk
);
570 struct clk
*__clk_get_parent(struct clk
*clk
);
571 struct clk
*clk_get_parent_by_index(struct clk
*clk
, u8 index
);
572 unsigned int __clk_get_enable_count(struct clk
*clk
);
573 unsigned long __clk_get_rate(struct clk
*clk
);
574 unsigned long __clk_get_flags(struct clk
*clk
);
575 bool __clk_is_prepared(struct clk
*clk
);
576 bool __clk_is_enabled(struct clk
*clk
);
577 struct clk
*__clk_lookup(const char *name
);
578 long __clk_mux_determine_rate(struct clk_hw
*hw
, unsigned long rate
,
579 unsigned long min_rate
,
580 unsigned long max_rate
,
581 unsigned long *best_parent_rate
,
582 struct clk_hw
**best_parent_p
);
583 unsigned long __clk_determine_rate(struct clk_hw
*core
,
585 unsigned long min_rate
,
586 unsigned long max_rate
);
587 long __clk_mux_determine_rate_closest(struct clk_hw
*hw
, unsigned long rate
,
588 unsigned long min_rate
,
589 unsigned long max_rate
,
590 unsigned long *best_parent_rate
,
591 struct clk_hw
**best_parent_p
);
593 static inline void __clk_hw_set_clk(struct clk_hw
*dst
, struct clk_hw
*src
)
596 dst
->core
= src
->core
;
600 * FIXME clock api without lock protection
602 unsigned long __clk_round_rate(struct clk
*clk
, unsigned long rate
);
606 typedef void (*of_clk_init_cb_t
)(struct device_node
*);
608 struct clk_onecell_data
{
610 unsigned int clk_num
;
613 extern struct of_device_id __clk_of_table
;
615 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
618 int of_clk_add_provider(struct device_node
*np
,
619 struct clk
*(*clk_src_get
)(struct of_phandle_args
*args
,
622 void of_clk_del_provider(struct device_node
*np
);
623 struct clk
*of_clk_src_simple_get(struct of_phandle_args
*clkspec
,
625 struct clk
*of_clk_src_onecell_get(struct of_phandle_args
*clkspec
, void *data
);
626 int of_clk_get_parent_count(struct device_node
*np
);
627 const char *of_clk_get_parent_name(struct device_node
*np
, int index
);
629 void of_clk_init(const struct of_device_id
*matches
);
631 #else /* !CONFIG_OF */
633 static inline int of_clk_add_provider(struct device_node
*np
,
634 struct clk
*(*clk_src_get
)(struct of_phandle_args
*args
,
640 #define of_clk_del_provider(np) \
642 static inline struct clk
*of_clk_src_simple_get(
643 struct of_phandle_args
*clkspec
, void *data
)
645 return ERR_PTR(-ENOENT
);
647 static inline struct clk
*of_clk_src_onecell_get(
648 struct of_phandle_args
*clkspec
, void *data
)
650 return ERR_PTR(-ENOENT
);
652 static inline const char *of_clk_get_parent_name(struct device_node
*np
,
657 #define of_clk_init(matches) \
659 #endif /* CONFIG_OF */
662 * wrap access to peripherals in accessor routines
663 * for improved portability across platforms
666 #if IS_ENABLED(CONFIG_PPC)
668 static inline u32
clk_readl(u32 __iomem
*reg
)
670 return ioread32be(reg
);
673 static inline void clk_writel(u32 val
, u32 __iomem
*reg
)
675 iowrite32be(val
, reg
);
678 #else /* platform dependent I/O accessors */
680 static inline u32
clk_readl(u32 __iomem
*reg
)
685 static inline void clk_writel(u32 val
, u32 __iomem
*reg
)
690 #endif /* platform dependent I/O accessors */
692 #ifdef CONFIG_DEBUG_FS
693 struct dentry
*clk_debugfs_add_file(struct clk_hw
*hw
, char *name
, umode_t mode
,
694 void *data
, const struct file_operations
*fops
);
697 #endif /* CONFIG_COMMON_CLK */
698 #endif /* CLK_PROVIDER_H */