2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
21 #ifndef LINUX_DMAENGINE_H
22 #define LINUX_DMAENGINE_H
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/uio.h>
27 #include <linux/bug.h>
28 #include <linux/scatterlist.h>
29 #include <linux/bitmap.h>
30 #include <linux/types.h>
34 * typedef dma_cookie_t - an opaque DMA cookie
36 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
38 typedef s32 dma_cookie_t
;
39 #define DMA_MIN_COOKIE 1
41 static inline int dma_submit_error(dma_cookie_t cookie
)
43 return cookie
< 0 ? cookie
: 0;
47 * enum dma_status - DMA transaction status
48 * @DMA_COMPLETE: transaction completed
49 * @DMA_IN_PROGRESS: transaction not yet processed
50 * @DMA_PAUSED: transaction is paused
51 * @DMA_ERROR: transaction failed
61 * enum dma_transaction_type - DMA transaction types/indexes
63 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
64 * automatically set as dma devices are registered.
66 enum dma_transaction_type
{
79 /* last transaction type for creation of the capabilities mask */
84 * enum dma_transfer_direction - dma transfer mode and direction indicator
85 * @DMA_MEM_TO_MEM: Async/Memcpy mode
86 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
87 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
88 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
90 enum dma_transfer_direction
{
99 * Interleaved Transfer Request
100 * ----------------------------
101 * A chunk is collection of contiguous bytes to be transfered.
102 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
103 * ICGs may or maynot change between chunks.
104 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
105 * that when repeated an integral number of times, specifies the transfer.
106 * A transfer template is specification of a Frame, the number of times
107 * it is to be repeated and other per-transfer attributes.
109 * Practically, a client driver would have ready a template for each
110 * type of transfer it is going to need during its lifetime and
111 * set only 'src_start' and 'dst_start' before submitting the requests.
114 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
115 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
122 * struct data_chunk - Element of scatter-gather list that makes a frame.
123 * @size: Number of bytes to read from source.
124 * size_dst := fn(op, size_src), so doesn't mean much for destination.
125 * @icg: Number of bytes to jump after last src/dst address of this
126 * chunk and before first src/dst address for next chunk.
127 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
128 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
136 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
138 * @src_start: Bus address of source for the first chunk.
139 * @dst_start: Bus address of destination for the first chunk.
140 * @dir: Specifies the type of Source and Destination.
141 * @src_inc: If the source address increments after reading from it.
142 * @dst_inc: If the destination address increments after writing to it.
143 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
144 * Otherwise, source is read contiguously (icg ignored).
145 * Ignored if src_inc is false.
146 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
147 * Otherwise, destination is filled contiguously (icg ignored).
148 * Ignored if dst_inc is false.
149 * @numf: Number of frames in this template.
150 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
151 * @sgl: Array of {chunk,icg} pairs that make up a frame.
153 struct dma_interleaved_template
{
154 dma_addr_t src_start
;
155 dma_addr_t dst_start
;
156 enum dma_transfer_direction dir
;
163 struct data_chunk sgl
[0];
167 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
168 * control completion, and communicate status.
169 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
171 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
172 * acknowledges receipt, i.e. has has a chance to establish any dependency
174 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
175 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
176 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
177 * sources that were the result of a previous operation, in the case of a PQ
178 * operation it continues the calculation with new sources
179 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
180 * on the result of this operation
182 enum dma_ctrl_flags
{
183 DMA_PREP_INTERRUPT
= (1 << 0),
184 DMA_CTRL_ACK
= (1 << 1),
185 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
186 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
187 DMA_PREP_CONTINUE
= (1 << 4),
188 DMA_PREP_FENCE
= (1 << 5),
192 * enum sum_check_bits - bit position of pq_check_flags
194 enum sum_check_bits
{
200 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
201 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
202 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
204 enum sum_check_flags
{
205 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
206 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
211 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
212 * See linux/cpumask.h
214 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
217 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
218 * @memcpy_count: transaction counter
219 * @bytes_transferred: byte counter
222 struct dma_chan_percpu
{
224 unsigned long memcpy_count
;
225 unsigned long bytes_transferred
;
229 * struct dma_chan - devices supply DMA channels, clients use them
230 * @device: ptr to the dma device who supplies this channel, always !%NULL
231 * @cookie: last cookie value returned to client
232 * @completed_cookie: last completed cookie for this channel
233 * @chan_id: channel ID for sysfs
234 * @dev: class device for sysfs
235 * @device_node: used to add this to the device chan list
236 * @local: per-cpu pointer to a struct dma_chan_percpu
237 * @client_count: how many clients are using this channel
238 * @table_count: number of appearances in the mem-to-mem allocation table
239 * @private: private data for certain client-channel associations
242 struct dma_device
*device
;
244 dma_cookie_t completed_cookie
;
248 struct dma_chan_dev
*dev
;
250 struct list_head device_node
;
251 struct dma_chan_percpu __percpu
*local
;
258 * struct dma_chan_dev - relate sysfs device node to backing channel device
259 * @chan: driver channel device
260 * @device: sysfs device
261 * @dev_id: parent dma_device dev_id
262 * @idr_ref: reference count to gate release of dma_device dev_id
264 struct dma_chan_dev
{
265 struct dma_chan
*chan
;
266 struct device device
;
272 * enum dma_slave_buswidth - defines bus width of the DMA slave
273 * device, source or target buses
275 enum dma_slave_buswidth
{
276 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
277 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
278 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
279 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
280 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
281 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
282 DMA_SLAVE_BUSWIDTH_16_BYTES
= 16,
283 DMA_SLAVE_BUSWIDTH_32_BYTES
= 32,
284 DMA_SLAVE_BUSWIDTH_64_BYTES
= 64,
288 * struct dma_slave_config - dma slave channel runtime config
289 * @direction: whether the data shall go in or out on this slave
290 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
291 * legal values. DEPRECATED, drivers should use the direction argument
292 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
293 * the dir field in the dma_interleaved_template structure.
294 * @src_addr: this is the physical address where DMA slave data
295 * should be read (RX), if the source is memory this argument is
297 * @dst_addr: this is the physical address where DMA slave data
298 * should be written (TX), if the source is memory this argument
300 * @src_addr_width: this is the width in bytes of the source (RX)
301 * register where DMA data shall be read. If the source
302 * is memory this may be ignored depending on architecture.
303 * Legal values: 1, 2, 4, 8.
304 * @dst_addr_width: same as src_addr_width but for destination
305 * target (TX) mutatis mutandis.
306 * @src_maxburst: the maximum number of words (note: words, as in
307 * units of the src_addr_width member, not bytes) that can be sent
308 * in one burst to the device. Typically something like half the
309 * FIFO depth on I/O peripherals so you don't overflow it. This
310 * may or may not be applicable on memory sources.
311 * @dst_maxburst: same as src_maxburst but for destination target
313 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
314 * with 'true' if peripheral should be flow controller. Direction will be
315 * selected at Runtime.
316 * @slave_id: Slave requester id. Only valid for slave channels. The dma
317 * slave peripheral will have unique id as dma requester which need to be
318 * pass as slave config.
320 * This struct is passed in as configuration data to a DMA engine
321 * in order to set up a certain channel for DMA transport at runtime.
322 * The DMA device/engine has to provide support for an additional
323 * callback in the dma_device structure, device_config and this struct
324 * will then be passed in as an argument to the function.
326 * The rationale for adding configuration information to this struct is as
327 * follows: if it is likely that more than one DMA slave controllers in
328 * the world will support the configuration option, then make it generic.
329 * If not: if it is fixed so that it be sent in static from the platform
330 * data, then prefer to do that.
332 struct dma_slave_config
{
333 enum dma_transfer_direction direction
;
336 enum dma_slave_buswidth src_addr_width
;
337 enum dma_slave_buswidth dst_addr_width
;
341 unsigned int slave_id
;
345 * enum dma_residue_granularity - Granularity of the reported transfer residue
346 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
347 * DMA channel is only able to tell whether a descriptor has been completed or
348 * not, which means residue reporting is not supported by this channel. The
349 * residue field of the dma_tx_state field will always be 0.
350 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
351 * completed segment of the transfer (For cyclic transfers this is after each
352 * period). This is typically implemented by having the hardware generate an
353 * interrupt after each transferred segment and then the drivers updates the
354 * outstanding residue by the size of the segment. Another possibility is if
355 * the hardware supports scatter-gather and the segment descriptor has a field
356 * which gets set after the segment has been completed. The driver then counts
357 * the number of segments without the flag set to compute the residue.
358 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
359 * burst. This is typically only supported if the hardware has a progress
360 * register of some sort (E.g. a register with the current read/write address
361 * or a register with the amount of bursts/beats/bytes that have been
362 * transferred or still need to be transferred).
364 enum dma_residue_granularity
{
365 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
366 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
367 DMA_RESIDUE_GRANULARITY_BURST
= 2,
370 /* struct dma_slave_caps - expose capabilities of a slave channel only
372 * @src_addr_widths: bit mask of src addr widths the channel supports
373 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
374 * @directions: bit mask of slave direction the channel supported
375 * since the enum dma_transfer_direction is not defined as bits for each
376 * type of direction, the dma controller should fill (1 << <TYPE>) and same
377 * should be checked by controller as well
378 * @cmd_pause: true, if pause and thereby resume is supported
379 * @cmd_terminate: true, if terminate cmd is supported
380 * @residue_granularity: granularity of the reported transfer residue
382 struct dma_slave_caps
{
388 enum dma_residue_granularity residue_granularity
;
391 static inline const char *dma_chan_name(struct dma_chan
*chan
)
393 return dev_name(&chan
->dev
->device
);
396 void dma_chan_cleanup(struct kref
*kref
);
399 * typedef dma_filter_fn - callback filter for dma_request_channel
400 * @chan: channel to be reviewed
401 * @filter_param: opaque parameter passed through dma_request_channel
403 * When this optional parameter is specified in a call to dma_request_channel a
404 * suitable channel is passed to this routine for further dispositioning before
405 * being returned. Where 'suitable' indicates a non-busy channel that
406 * satisfies the given capability mask. It returns 'true' to indicate that the
407 * channel is suitable.
409 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
411 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
413 struct dmaengine_unmap_data
{
425 * struct dma_async_tx_descriptor - async transaction descriptor
426 * ---dma generic offload fields---
427 * @cookie: tracking cookie for this transaction, set to -EBUSY if
428 * this tx is sitting on a dependency list
429 * @flags: flags to augment operation preparation, control completion, and
431 * @phys: physical address of the descriptor
432 * @chan: target channel for this operation
433 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
434 * descriptor pending. To be pushed on .issue_pending() call
435 * @callback: routine to call after this operation is complete
436 * @callback_param: general parameter to pass to the callback routine
437 * ---async_tx api specific fields---
438 * @next: at completion submit this descriptor
439 * @parent: pointer to the next level up in the dependency chain
440 * @lock: protect the parent and next pointers
442 struct dma_async_tx_descriptor
{
444 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
446 struct dma_chan
*chan
;
447 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
448 dma_async_tx_callback callback
;
449 void *callback_param
;
450 struct dmaengine_unmap_data
*unmap
;
451 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
452 struct dma_async_tx_descriptor
*next
;
453 struct dma_async_tx_descriptor
*parent
;
458 #ifdef CONFIG_DMA_ENGINE
459 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
460 struct dmaengine_unmap_data
*unmap
)
462 kref_get(&unmap
->kref
);
466 struct dmaengine_unmap_data
*
467 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
468 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
470 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
471 struct dmaengine_unmap_data
*unmap
)
474 static inline struct dmaengine_unmap_data
*
475 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
479 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
484 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
487 dmaengine_unmap_put(tx
->unmap
);
492 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
493 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
496 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
499 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
503 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
506 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
509 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
513 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
519 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
521 spin_lock_bh(&txd
->lock
);
523 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
525 spin_unlock_bh(&txd
->lock
);
527 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
532 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
536 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
540 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
544 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
551 * struct dma_tx_state - filled in to report the status of
553 * @last: last completed DMA cookie
554 * @used: last issued DMA cookie (i.e. the one in progress)
555 * @residue: the remaining number of bytes left to transmit
556 * on the selected transfer for states DMA_IN_PROGRESS and
557 * DMA_PAUSED if this is implemented in the driver, else 0
559 struct dma_tx_state
{
566 * struct dma_device - info on the entity supplying DMA services
567 * @chancnt: how many DMA channels are supported
568 * @privatecnt: how many DMA channels are requested by dma_request_channel
569 * @channels: the list of struct dma_chan
570 * @global_node: list_head for global dma_device_list
571 * @cap_mask: one or more dma_capability flags
572 * @max_xor: maximum number of xor sources, 0 if no capability
573 * @max_pq: maximum number of PQ sources and PQ-continue capability
574 * @copy_align: alignment shift for memcpy operations
575 * @xor_align: alignment shift for xor operations
576 * @pq_align: alignment shift for pq operations
577 * @fill_align: alignment shift for memset operations
578 * @dev_id: unique device ID
579 * @dev: struct device reference for dma mapping api
580 * @src_addr_widths: bit mask of src addr widths the device supports
581 * @dst_addr_widths: bit mask of dst addr widths the device supports
582 * @directions: bit mask of slave direction the device supports since
583 * the enum dma_transfer_direction is not defined as bits for
584 * each type of direction, the dma controller should fill (1 <<
585 * <TYPE>) and same should be checked by controller as well
586 * @residue_granularity: granularity of the transfer residue reported
588 * @device_alloc_chan_resources: allocate resources and return the
589 * number of allocated descriptors
590 * @device_free_chan_resources: release DMA channel's resources
591 * @device_prep_dma_memcpy: prepares a memcpy operation
592 * @device_prep_dma_xor: prepares a xor operation
593 * @device_prep_dma_xor_val: prepares a xor validation operation
594 * @device_prep_dma_pq: prepares a pq operation
595 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
596 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
597 * @device_prep_slave_sg: prepares a slave dma operation
598 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
599 * The function takes a buffer of size buf_len. The callback function will
600 * be called after period_len bytes have been transferred.
601 * @device_prep_interleaved_dma: Transfer expression in a generic way.
602 * @device_config: Pushes a new configuration to a channel, return 0 or an error
604 * @device_pause: Pauses any transfer happening on a channel. Returns
606 * @device_resume: Resumes any transfer on a channel previously
607 * paused. Returns 0 or an error code
608 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
610 * @device_tx_status: poll for transaction completion, the optional
611 * txstate parameter can be supplied with a pointer to get a
612 * struct with auxiliary transfer status information, otherwise the call
613 * will just return a simple status code
614 * @device_issue_pending: push pending transactions to hardware
618 unsigned int chancnt
;
619 unsigned int privatecnt
;
620 struct list_head channels
;
621 struct list_head global_node
;
622 dma_cap_mask_t cap_mask
;
623 unsigned short max_xor
;
624 unsigned short max_pq
;
629 #define DMA_HAS_PQ_CONTINUE (1 << 15)
637 enum dma_residue_granularity residue_granularity
;
639 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
640 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
642 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
643 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
644 size_t len
, unsigned long flags
);
645 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
646 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
647 unsigned int src_cnt
, size_t len
, unsigned long flags
);
648 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
649 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
650 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
651 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
652 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
653 unsigned int src_cnt
, const unsigned char *scf
,
654 size_t len
, unsigned long flags
);
655 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
656 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
657 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
658 enum sum_check_flags
*pqres
, unsigned long flags
);
659 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
660 struct dma_chan
*chan
, unsigned long flags
);
661 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
662 struct dma_chan
*chan
,
663 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
664 struct scatterlist
*src_sg
, unsigned int src_nents
,
665 unsigned long flags
);
667 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
668 struct dma_chan
*chan
, struct scatterlist
*sgl
,
669 unsigned int sg_len
, enum dma_transfer_direction direction
,
670 unsigned long flags
, void *context
);
671 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
672 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
673 size_t period_len
, enum dma_transfer_direction direction
,
674 unsigned long flags
);
675 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
676 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
677 unsigned long flags
);
679 int (*device_config
)(struct dma_chan
*chan
,
680 struct dma_slave_config
*config
);
681 int (*device_pause
)(struct dma_chan
*chan
);
682 int (*device_resume
)(struct dma_chan
*chan
);
683 int (*device_terminate_all
)(struct dma_chan
*chan
);
685 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
687 struct dma_tx_state
*txstate
);
688 void (*device_issue_pending
)(struct dma_chan
*chan
);
691 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
692 struct dma_slave_config
*config
)
694 if (chan
->device
->device_config
)
695 return chan
->device
->device_config(chan
, config
);
700 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
702 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
705 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
706 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
707 enum dma_transfer_direction dir
, unsigned long flags
)
709 struct scatterlist sg
;
710 sg_init_table(&sg
, 1);
711 sg_dma_address(&sg
) = buf
;
712 sg_dma_len(&sg
) = len
;
714 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
718 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
719 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
720 enum dma_transfer_direction dir
, unsigned long flags
)
722 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
726 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
728 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
729 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
730 enum dma_transfer_direction dir
, unsigned long flags
,
731 struct rio_dma_ext
*rio_ext
)
733 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
734 dir
, flags
, rio_ext
);
738 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
739 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
740 size_t period_len
, enum dma_transfer_direction dir
,
743 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
744 period_len
, dir
, flags
);
747 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
748 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
751 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
754 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_sg(
755 struct dma_chan
*chan
,
756 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
757 struct scatterlist
*src_sg
, unsigned int src_nents
,
760 return chan
->device
->device_prep_dma_sg(chan
, dst_sg
, dst_nents
,
761 src_sg
, src_nents
, flags
);
764 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
766 if (chan
->device
->device_terminate_all
)
767 return chan
->device
->device_terminate_all(chan
);
772 static inline int dmaengine_pause(struct dma_chan
*chan
)
774 if (chan
->device
->device_pause
)
775 return chan
->device
->device_pause(chan
);
780 static inline int dmaengine_resume(struct dma_chan
*chan
)
782 if (chan
->device
->device_resume
)
783 return chan
->device
->device_resume(chan
);
788 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
789 dma_cookie_t cookie
, struct dma_tx_state
*state
)
791 return chan
->device
->device_tx_status(chan
, cookie
, state
);
794 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
796 return desc
->tx_submit(desc
);
799 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
805 mask
= (1 << align
) - 1;
806 if (mask
& (off1
| off2
| len
))
811 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
812 size_t off2
, size_t len
)
814 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
817 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
818 size_t off2
, size_t len
)
820 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
823 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
824 size_t off2
, size_t len
)
826 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
829 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
830 size_t off2
, size_t len
)
832 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
836 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
840 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
843 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
845 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
848 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
850 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
852 return (flags
& mask
) == mask
;
855 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
857 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
860 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
862 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
865 /* dma_maxpq - reduce maxpq in the face of continued operations
866 * @dma - dma device with PQ capability
867 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
869 * When an engine does not support native continuation we need 3 extra
870 * source slots to reuse P and Q with the following coefficients:
871 * 1/ {00} * P : remove P from Q', but use it as a source for P'
872 * 2/ {01} * Q : use Q to continue Q' calculation
873 * 3/ {00} * Q : subtract Q from P' to cancel (2)
875 * In the case where P is disabled we only need 1 extra source:
876 * 1/ {01} * Q : use Q to continue Q' calculation
878 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
880 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
881 return dma_dev_to_maxpq(dma
);
882 else if (dmaf_p_disabled_continue(flags
))
883 return dma_dev_to_maxpq(dma
) - 1;
884 else if (dmaf_continue(flags
))
885 return dma_dev_to_maxpq(dma
) - 3;
889 /* --- public DMA engine API --- */
891 #ifdef CONFIG_DMA_ENGINE
892 void dmaengine_get(void);
893 void dmaengine_put(void);
895 static inline void dmaengine_get(void)
898 static inline void dmaengine_put(void)
903 #ifdef CONFIG_ASYNC_TX_DMA
904 #define async_dmaengine_get() dmaengine_get()
905 #define async_dmaengine_put() dmaengine_put()
906 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
907 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
909 #define async_dma_find_channel(type) dma_find_channel(type)
910 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
912 static inline void async_dmaengine_get(void)
915 static inline void async_dmaengine_put(void)
918 static inline struct dma_chan
*
919 async_dma_find_channel(enum dma_transaction_type type
)
923 #endif /* CONFIG_ASYNC_TX_DMA */
924 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
925 struct dma_chan
*chan
);
927 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
929 tx
->flags
|= DMA_CTRL_ACK
;
932 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
934 tx
->flags
&= ~DMA_CTRL_ACK
;
937 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
939 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
942 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
944 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
946 set_bit(tx_type
, dstp
->bits
);
949 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
951 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
953 clear_bit(tx_type
, dstp
->bits
);
956 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
957 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
959 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
962 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
964 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
966 return test_bit(tx_type
, srcp
->bits
);
969 #define for_each_dma_cap_mask(cap, mask) \
970 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
973 * dma_async_issue_pending - flush pending transactions to HW
974 * @chan: target DMA channel
976 * This allows drivers to push copies to HW in batches,
977 * reducing MMIO writes where possible.
979 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
981 chan
->device
->device_issue_pending(chan
);
985 * dma_async_is_tx_complete - poll for transaction completion
987 * @cookie: transaction identifier to check status of
988 * @last: returns last completed cookie, can be NULL
989 * @used: returns last issued cookie, can be NULL
991 * If @last and @used are passed in, upon return they reflect the driver
992 * internal state and can be used with dma_async_is_complete() to check
993 * the status of multiple cookies without re-checking hardware state.
995 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
996 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
998 struct dma_tx_state state
;
999 enum dma_status status
;
1001 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
1010 * dma_async_is_complete - test a cookie against chan state
1011 * @cookie: transaction identifier to test status of
1012 * @last_complete: last know completed transaction
1013 * @last_used: last cookie value handed out
1015 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1016 * the test logic is separated for lightweight testing of multiple cookies
1018 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1019 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1021 if (last_complete
<= last_used
) {
1022 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1023 return DMA_COMPLETE
;
1025 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1026 return DMA_COMPLETE
;
1028 return DMA_IN_PROGRESS
;
1032 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1037 st
->residue
= residue
;
1041 #ifdef CONFIG_DMA_ENGINE
1042 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1043 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1044 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1045 void dma_issue_pending_all(void);
1046 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1047 dma_filter_fn fn
, void *fn_param
);
1048 struct dma_chan
*dma_request_slave_channel_reason(struct device
*dev
,
1050 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1051 void dma_release_channel(struct dma_chan
*chan
);
1052 int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
1054 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1058 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1060 return DMA_COMPLETE
;
1062 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1064 return DMA_COMPLETE
;
1066 static inline void dma_issue_pending_all(void)
1069 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1070 dma_filter_fn fn
, void *fn_param
)
1074 static inline struct dma_chan
*dma_request_slave_channel_reason(
1075 struct device
*dev
, const char *name
)
1077 return ERR_PTR(-ENODEV
);
1079 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1084 static inline void dma_release_channel(struct dma_chan
*chan
)
1087 static inline int dma_get_slave_caps(struct dma_chan
*chan
,
1088 struct dma_slave_caps
*caps
)
1094 /* --- DMA device --- */
1096 int dma_async_device_register(struct dma_device
*device
);
1097 void dma_async_device_unregister(struct dma_device
*device
);
1098 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1099 struct dma_chan
*dma_get_slave_channel(struct dma_chan
*chan
);
1100 struct dma_chan
*dma_get_any_slave_channel(struct dma_device
*device
);
1101 struct dma_chan
*net_dma_find_channel(void);
1102 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1103 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1104 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1106 static inline struct dma_chan
1107 *__dma_request_slave_channel_compat(const dma_cap_mask_t
*mask
,
1108 dma_filter_fn fn
, void *fn_param
,
1109 struct device
*dev
, char *name
)
1111 struct dma_chan
*chan
;
1113 chan
= dma_request_slave_channel(dev
, name
);
1117 return __dma_request_channel(mask
, fn
, fn_param
);
1120 /* --- Helper iov-locking functions --- */
1122 struct dma_page_list
{
1123 char __user
*base_address
;
1125 struct page
**pages
;
1128 struct dma_pinned_list
{
1130 struct dma_page_list page_list
[0];
1133 struct dma_pinned_list
*dma_pin_iovec_pages(struct iovec
*iov
, size_t len
);
1134 void dma_unpin_iovec_pages(struct dma_pinned_list
* pinned_list
);
1136 dma_cookie_t
dma_memcpy_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
1137 struct dma_pinned_list
*pinned_list
, unsigned char *kdata
, size_t len
);
1138 dma_cookie_t
dma_memcpy_pg_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
1139 struct dma_pinned_list
*pinned_list
, struct page
*page
,
1140 unsigned int offset
, size_t len
);
1142 #endif /* DMAENGINE_H */