2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/scatterlist.h>
29 * typedef dma_cookie_t - an opaque DMA cookie
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
33 typedef s32 dma_cookie_t
;
34 #define DMA_MIN_COOKIE 1
35 #define DMA_MAX_COOKIE INT_MAX
37 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
40 * enum dma_status - DMA transaction status
41 * @DMA_SUCCESS: transaction completed successfully
42 * @DMA_IN_PROGRESS: transaction not yet processed
43 * @DMA_PAUSED: transaction is paused
44 * @DMA_ERROR: transaction failed
54 * enum dma_transaction_type - DMA transaction types/indexes
56 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
57 * automatically set as dma devices are registered.
59 enum dma_transaction_type
{
74 /* last transaction type for creation of the capabilities mask */
75 #define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
78 * enum dma_transfer_direction - dma transfer mode and direction indicator
79 * @DMA_MEM_TO_MEM: Async/Memcpy mode
80 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
81 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
82 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
84 enum dma_transfer_direction
{
92 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
93 * control completion, and communicate status.
94 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
96 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
97 * acknowledges receipt, i.e. has has a chance to establish any dependency
99 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
100 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
101 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
102 * (if not set, do the source dma-unmapping as page)
103 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
104 * (if not set, do the destination dma-unmapping as page)
105 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
106 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
107 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
108 * sources that were the result of a previous operation, in the case of a PQ
109 * operation it continues the calculation with new sources
110 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
111 * on the result of this operation
113 enum dma_ctrl_flags
{
114 DMA_PREP_INTERRUPT
= (1 << 0),
115 DMA_CTRL_ACK
= (1 << 1),
116 DMA_COMPL_SKIP_SRC_UNMAP
= (1 << 2),
117 DMA_COMPL_SKIP_DEST_UNMAP
= (1 << 3),
118 DMA_COMPL_SRC_UNMAP_SINGLE
= (1 << 4),
119 DMA_COMPL_DEST_UNMAP_SINGLE
= (1 << 5),
120 DMA_PREP_PQ_DISABLE_P
= (1 << 6),
121 DMA_PREP_PQ_DISABLE_Q
= (1 << 7),
122 DMA_PREP_CONTINUE
= (1 << 8),
123 DMA_PREP_FENCE
= (1 << 9),
127 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
128 * on a running channel.
129 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
130 * @DMA_PAUSE: pause ongoing transfers
131 * @DMA_RESUME: resume paused transfer
132 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
133 * that need to runtime reconfigure the slave channels (as opposed to passing
134 * configuration data in statically from the platform). An additional
135 * argument of struct dma_slave_config must be passed in with this
137 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
138 * into external start mode.
145 FSLDMA_EXTERNAL_START
,
149 * enum sum_check_bits - bit position of pq_check_flags
151 enum sum_check_bits
{
157 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
158 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
159 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
161 enum sum_check_flags
{
162 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
163 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
168 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
169 * See linux/cpumask.h
171 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
174 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
175 * @memcpy_count: transaction counter
176 * @bytes_transferred: byte counter
179 struct dma_chan_percpu
{
181 unsigned long memcpy_count
;
182 unsigned long bytes_transferred
;
186 * struct dma_chan - devices supply DMA channels, clients use them
187 * @device: ptr to the dma device who supplies this channel, always !%NULL
188 * @cookie: last cookie value returned to client
189 * @chan_id: channel ID for sysfs
190 * @dev: class device for sysfs
191 * @device_node: used to add this to the device chan list
192 * @local: per-cpu pointer to a struct dma_chan_percpu
193 * @client-count: how many clients are using this channel
194 * @table_count: number of appearances in the mem-to-mem allocation table
195 * @private: private data for certain client-channel associations
198 struct dma_device
*device
;
203 struct dma_chan_dev
*dev
;
205 struct list_head device_node
;
206 struct dma_chan_percpu __percpu
*local
;
213 * struct dma_chan_dev - relate sysfs device node to backing channel device
214 * @chan - driver channel device
215 * @device - sysfs device
216 * @dev_id - parent dma_device dev_id
217 * @idr_ref - reference count to gate release of dma_device dev_id
219 struct dma_chan_dev
{
220 struct dma_chan
*chan
;
221 struct device device
;
227 * enum dma_slave_buswidth - defines bus with of the DMA slave
228 * device, source or target buses
230 enum dma_slave_buswidth
{
231 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
232 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
233 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
234 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
235 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
239 * struct dma_slave_config - dma slave channel runtime config
240 * @direction: whether the data shall go in or out on this slave
241 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
242 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
243 * need to differentiate source and target addresses.
244 * @src_addr: this is the physical address where DMA slave data
245 * should be read (RX), if the source is memory this argument is
247 * @dst_addr: this is the physical address where DMA slave data
248 * should be written (TX), if the source is memory this argument
250 * @src_addr_width: this is the width in bytes of the source (RX)
251 * register where DMA data shall be read. If the source
252 * is memory this may be ignored depending on architecture.
253 * Legal values: 1, 2, 4, 8.
254 * @dst_addr_width: same as src_addr_width but for destination
255 * target (TX) mutatis mutandis.
256 * @src_maxburst: the maximum number of words (note: words, as in
257 * units of the src_addr_width member, not bytes) that can be sent
258 * in one burst to the device. Typically something like half the
259 * FIFO depth on I/O peripherals so you don't overflow it. This
260 * may or may not be applicable on memory sources.
261 * @dst_maxburst: same as src_maxburst but for destination target
264 * This struct is passed in as configuration data to a DMA engine
265 * in order to set up a certain channel for DMA transport at runtime.
266 * The DMA device/engine has to provide support for an additional
267 * command in the channel config interface, DMA_SLAVE_CONFIG
268 * and this struct will then be passed in as an argument to the
269 * DMA engine device_control() function.
271 * The rationale for adding configuration information to this struct
272 * is as follows: if it is likely that most DMA slave controllers in
273 * the world will support the configuration option, then make it
274 * generic. If not: if it is fixed so that it be sent in static from
275 * the platform data, then prefer to do that. Else, if it is neither
276 * fixed at runtime, nor generic enough (such as bus mastership on
277 * some CPU family and whatnot) then create a custom slave config
278 * struct and pass that, then make this config a member of that
279 * struct, if applicable.
281 struct dma_slave_config
{
282 enum dma_transfer_direction direction
;
285 enum dma_slave_buswidth src_addr_width
;
286 enum dma_slave_buswidth dst_addr_width
;
291 static inline const char *dma_chan_name(struct dma_chan
*chan
)
293 return dev_name(&chan
->dev
->device
);
296 void dma_chan_cleanup(struct kref
*kref
);
299 * typedef dma_filter_fn - callback filter for dma_request_channel
300 * @chan: channel to be reviewed
301 * @filter_param: opaque parameter passed through dma_request_channel
303 * When this optional parameter is specified in a call to dma_request_channel a
304 * suitable channel is passed to this routine for further dispositioning before
305 * being returned. Where 'suitable' indicates a non-busy channel that
306 * satisfies the given capability mask. It returns 'true' to indicate that the
307 * channel is suitable.
309 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
311 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
313 * struct dma_async_tx_descriptor - async transaction descriptor
314 * ---dma generic offload fields---
315 * @cookie: tracking cookie for this transaction, set to -EBUSY if
316 * this tx is sitting on a dependency list
317 * @flags: flags to augment operation preparation, control completion, and
319 * @phys: physical address of the descriptor
320 * @chan: target channel for this operation
321 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
322 * @callback: routine to call after this operation is complete
323 * @callback_param: general parameter to pass to the callback routine
324 * ---async_tx api specific fields---
325 * @next: at completion submit this descriptor
326 * @parent: pointer to the next level up in the dependency chain
327 * @lock: protect the parent and next pointers
329 struct dma_async_tx_descriptor
{
331 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
333 struct dma_chan
*chan
;
334 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
335 dma_async_tx_callback callback
;
336 void *callback_param
;
337 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
338 struct dma_async_tx_descriptor
*next
;
339 struct dma_async_tx_descriptor
*parent
;
344 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
345 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
348 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
351 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
355 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
358 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
361 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
365 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
371 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
373 spin_lock_bh(&txd
->lock
);
375 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
377 spin_unlock_bh(&txd
->lock
);
379 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
384 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
388 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
392 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
396 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
403 * struct dma_tx_state - filled in to report the status of
405 * @last: last completed DMA cookie
406 * @used: last issued DMA cookie (i.e. the one in progress)
407 * @residue: the remaining number of bytes left to transmit
408 * on the selected transfer for states DMA_IN_PROGRESS and
409 * DMA_PAUSED if this is implemented in the driver, else 0
411 struct dma_tx_state
{
418 * struct dma_device - info on the entity supplying DMA services
419 * @chancnt: how many DMA channels are supported
420 * @privatecnt: how many DMA channels are requested by dma_request_channel
421 * @channels: the list of struct dma_chan
422 * @global_node: list_head for global dma_device_list
423 * @cap_mask: one or more dma_capability flags
424 * @max_xor: maximum number of xor sources, 0 if no capability
425 * @max_pq: maximum number of PQ sources and PQ-continue capability
426 * @copy_align: alignment shift for memcpy operations
427 * @xor_align: alignment shift for xor operations
428 * @pq_align: alignment shift for pq operations
429 * @fill_align: alignment shift for memset operations
430 * @dev_id: unique device ID
431 * @dev: struct device reference for dma mapping api
432 * @device_alloc_chan_resources: allocate resources and return the
433 * number of allocated descriptors
434 * @device_free_chan_resources: release DMA channel's resources
435 * @device_prep_dma_memcpy: prepares a memcpy operation
436 * @device_prep_dma_xor: prepares a xor operation
437 * @device_prep_dma_xor_val: prepares a xor validation operation
438 * @device_prep_dma_pq: prepares a pq operation
439 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
440 * @device_prep_dma_memset: prepares a memset operation
441 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
442 * @device_prep_slave_sg: prepares a slave dma operation
443 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
444 * The function takes a buffer of size buf_len. The callback function will
445 * be called after period_len bytes have been transferred.
446 * @device_control: manipulate all pending operations on a channel, returns
448 * @device_tx_status: poll for transaction completion, the optional
449 * txstate parameter can be supplied with a pointer to get a
450 * struct with auxiliary transfer status information, otherwise the call
451 * will just return a simple status code
452 * @device_issue_pending: push pending transactions to hardware
456 unsigned int chancnt
;
457 unsigned int privatecnt
;
458 struct list_head channels
;
459 struct list_head global_node
;
460 dma_cap_mask_t cap_mask
;
461 unsigned short max_xor
;
462 unsigned short max_pq
;
467 #define DMA_HAS_PQ_CONTINUE (1 << 15)
472 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
473 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
475 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
476 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
477 size_t len
, unsigned long flags
);
478 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
479 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
480 unsigned int src_cnt
, size_t len
, unsigned long flags
);
481 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
482 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
483 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
484 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
485 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
486 unsigned int src_cnt
, const unsigned char *scf
,
487 size_t len
, unsigned long flags
);
488 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
489 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
490 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
491 enum sum_check_flags
*pqres
, unsigned long flags
);
492 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
493 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
494 unsigned long flags
);
495 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
496 struct dma_chan
*chan
, unsigned long flags
);
497 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
498 struct dma_chan
*chan
,
499 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
500 struct scatterlist
*src_sg
, unsigned int src_nents
,
501 unsigned long flags
);
503 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
504 struct dma_chan
*chan
, struct scatterlist
*sgl
,
505 unsigned int sg_len
, enum dma_transfer_direction direction
,
506 unsigned long flags
);
507 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
508 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
509 size_t period_len
, enum dma_transfer_direction direction
);
510 int (*device_control
)(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
513 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
515 struct dma_tx_state
*txstate
);
516 void (*device_issue_pending
)(struct dma_chan
*chan
);
519 static inline int dmaengine_device_control(struct dma_chan
*chan
,
520 enum dma_ctrl_cmd cmd
,
523 return chan
->device
->device_control(chan
, cmd
, arg
);
526 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
527 struct dma_slave_config
*config
)
529 return dmaengine_device_control(chan
, DMA_SLAVE_CONFIG
,
530 (unsigned long)config
);
533 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
534 struct dma_chan
*chan
, void *buf
, size_t len
,
535 enum dma_transfer_direction dir
, unsigned long flags
)
537 struct scatterlist sg
;
538 sg_init_one(&sg
, buf
, len
);
540 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1, dir
, flags
);
543 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
545 return dmaengine_device_control(chan
, DMA_TERMINATE_ALL
, 0);
548 static inline int dmaengine_pause(struct dma_chan
*chan
)
550 return dmaengine_device_control(chan
, DMA_PAUSE
, 0);
553 static inline int dmaengine_resume(struct dma_chan
*chan
)
555 return dmaengine_device_control(chan
, DMA_RESUME
, 0);
558 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
560 return desc
->tx_submit(desc
);
563 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
569 mask
= (1 << align
) - 1;
570 if (mask
& (off1
| off2
| len
))
575 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
576 size_t off2
, size_t len
)
578 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
581 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
582 size_t off2
, size_t len
)
584 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
587 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
588 size_t off2
, size_t len
)
590 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
593 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
594 size_t off2
, size_t len
)
596 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
600 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
604 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
607 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
609 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
612 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
614 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
616 return (flags
& mask
) == mask
;
619 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
621 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
624 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
626 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
629 /* dma_maxpq - reduce maxpq in the face of continued operations
630 * @dma - dma device with PQ capability
631 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
633 * When an engine does not support native continuation we need 3 extra
634 * source slots to reuse P and Q with the following coefficients:
635 * 1/ {00} * P : remove P from Q', but use it as a source for P'
636 * 2/ {01} * Q : use Q to continue Q' calculation
637 * 3/ {00} * Q : subtract Q from P' to cancel (2)
639 * In the case where P is disabled we only need 1 extra source:
640 * 1/ {01} * Q : use Q to continue Q' calculation
642 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
644 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
645 return dma_dev_to_maxpq(dma
);
646 else if (dmaf_p_disabled_continue(flags
))
647 return dma_dev_to_maxpq(dma
) - 1;
648 else if (dmaf_continue(flags
))
649 return dma_dev_to_maxpq(dma
) - 3;
653 /* --- public DMA engine API --- */
655 #ifdef CONFIG_DMA_ENGINE
656 void dmaengine_get(void);
657 void dmaengine_put(void);
659 static inline void dmaengine_get(void)
662 static inline void dmaengine_put(void)
667 #ifdef CONFIG_NET_DMA
668 #define net_dmaengine_get() dmaengine_get()
669 #define net_dmaengine_put() dmaengine_put()
671 static inline void net_dmaengine_get(void)
674 static inline void net_dmaengine_put(void)
679 #ifdef CONFIG_ASYNC_TX_DMA
680 #define async_dmaengine_get() dmaengine_get()
681 #define async_dmaengine_put() dmaengine_put()
682 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
683 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
685 #define async_dma_find_channel(type) dma_find_channel(type)
686 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
688 static inline void async_dmaengine_get(void)
691 static inline void async_dmaengine_put(void)
694 static inline struct dma_chan
*
695 async_dma_find_channel(enum dma_transaction_type type
)
699 #endif /* CONFIG_ASYNC_TX_DMA */
701 dma_cookie_t
dma_async_memcpy_buf_to_buf(struct dma_chan
*chan
,
702 void *dest
, void *src
, size_t len
);
703 dma_cookie_t
dma_async_memcpy_buf_to_pg(struct dma_chan
*chan
,
704 struct page
*page
, unsigned int offset
, void *kdata
, size_t len
);
705 dma_cookie_t
dma_async_memcpy_pg_to_pg(struct dma_chan
*chan
,
706 struct page
*dest_pg
, unsigned int dest_off
, struct page
*src_pg
,
707 unsigned int src_off
, size_t len
);
708 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
709 struct dma_chan
*chan
);
711 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
713 tx
->flags
|= DMA_CTRL_ACK
;
716 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
718 tx
->flags
&= ~DMA_CTRL_ACK
;
721 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
723 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
726 #define first_dma_cap(mask) __first_dma_cap(&(mask))
727 static inline int __first_dma_cap(const dma_cap_mask_t
*srcp
)
729 return min_t(int, DMA_TX_TYPE_END
,
730 find_first_bit(srcp
->bits
, DMA_TX_TYPE_END
));
733 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
734 static inline int __next_dma_cap(int n
, const dma_cap_mask_t
*srcp
)
736 return min_t(int, DMA_TX_TYPE_END
,
737 find_next_bit(srcp
->bits
, DMA_TX_TYPE_END
, n
+1));
740 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
742 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
744 set_bit(tx_type
, dstp
->bits
);
747 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
749 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
751 clear_bit(tx_type
, dstp
->bits
);
754 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
755 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
757 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
760 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
762 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
764 return test_bit(tx_type
, srcp
->bits
);
767 #define for_each_dma_cap_mask(cap, mask) \
768 for ((cap) = first_dma_cap(mask); \
769 (cap) < DMA_TX_TYPE_END; \
770 (cap) = next_dma_cap((cap), (mask)))
773 * dma_async_issue_pending - flush pending transactions to HW
774 * @chan: target DMA channel
776 * This allows drivers to push copies to HW in batches,
777 * reducing MMIO writes where possible.
779 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
781 chan
->device
->device_issue_pending(chan
);
784 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
787 * dma_async_is_tx_complete - poll for transaction completion
789 * @cookie: transaction identifier to check status of
790 * @last: returns last completed cookie, can be NULL
791 * @used: returns last issued cookie, can be NULL
793 * If @last and @used are passed in, upon return they reflect the driver
794 * internal state and can be used with dma_async_is_complete() to check
795 * the status of multiple cookies without re-checking hardware state.
797 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
798 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
800 struct dma_tx_state state
;
801 enum dma_status status
;
803 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
811 #define dma_async_memcpy_complete(chan, cookie, last, used)\
812 dma_async_is_tx_complete(chan, cookie, last, used)
815 * dma_async_is_complete - test a cookie against chan state
816 * @cookie: transaction identifier to test status of
817 * @last_complete: last know completed transaction
818 * @last_used: last cookie value handed out
820 * dma_async_is_complete() is used in dma_async_memcpy_complete()
821 * the test logic is separated for lightweight testing of multiple cookies
823 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
824 dma_cookie_t last_complete
, dma_cookie_t last_used
)
826 if (last_complete
<= last_used
) {
827 if ((cookie
<= last_complete
) || (cookie
> last_used
))
830 if ((cookie
<= last_complete
) && (cookie
> last_used
))
833 return DMA_IN_PROGRESS
;
837 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
842 st
->residue
= residue
;
846 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
847 #ifdef CONFIG_DMA_ENGINE
848 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
849 void dma_issue_pending_all(void);
850 struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
, dma_filter_fn fn
, void *fn_param
);
851 void dma_release_channel(struct dma_chan
*chan
);
853 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
857 static inline void dma_issue_pending_all(void)
860 static inline struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
,
861 dma_filter_fn fn
, void *fn_param
)
865 static inline void dma_release_channel(struct dma_chan
*chan
)
870 /* --- DMA device --- */
872 int dma_async_device_register(struct dma_device
*device
);
873 void dma_async_device_unregister(struct dma_device
*device
);
874 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
875 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
876 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
878 /* --- Helper iov-locking functions --- */
880 struct dma_page_list
{
881 char __user
*base_address
;
886 struct dma_pinned_list
{
888 struct dma_page_list page_list
[0];
891 struct dma_pinned_list
*dma_pin_iovec_pages(struct iovec
*iov
, size_t len
);
892 void dma_unpin_iovec_pages(struct dma_pinned_list
* pinned_list
);
894 dma_cookie_t
dma_memcpy_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
895 struct dma_pinned_list
*pinned_list
, unsigned char *kdata
, size_t len
);
896 dma_cookie_t
dma_memcpy_pg_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
897 struct dma_pinned_list
*pinned_list
, struct page
*page
,
898 unsigned int offset
, size_t len
);
900 #endif /* DMAENGINE_H */