2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
17 #ifndef LINUX_DMAENGINE_H
18 #define LINUX_DMAENGINE_H
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/uio.h>
23 #include <linux/bug.h>
24 #include <linux/scatterlist.h>
25 #include <linux/bitmap.h>
26 #include <linux/types.h>
30 * typedef dma_cookie_t - an opaque DMA cookie
32 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
34 typedef s32 dma_cookie_t
;
35 #define DMA_MIN_COOKIE 1
37 static inline int dma_submit_error(dma_cookie_t cookie
)
39 return cookie
< 0 ? cookie
: 0;
43 * enum dma_status - DMA transaction status
44 * @DMA_COMPLETE: transaction completed
45 * @DMA_IN_PROGRESS: transaction not yet processed
46 * @DMA_PAUSED: transaction is paused
47 * @DMA_ERROR: transaction failed
57 * enum dma_transaction_type - DMA transaction types/indexes
59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
60 * automatically set as dma devices are registered.
62 enum dma_transaction_type
{
77 /* last transaction type for creation of the capabilities mask */
82 * enum dma_transfer_direction - dma transfer mode and direction indicator
83 * @DMA_MEM_TO_MEM: Async/Memcpy mode
84 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
85 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
86 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
88 enum dma_transfer_direction
{
97 * Interleaved Transfer Request
98 * ----------------------------
99 * A chunk is collection of contiguous bytes to be transfered.
100 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
101 * ICGs may or maynot change between chunks.
102 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
103 * that when repeated an integral number of times, specifies the transfer.
104 * A transfer template is specification of a Frame, the number of times
105 * it is to be repeated and other per-transfer attributes.
107 * Practically, a client driver would have ready a template for each
108 * type of transfer it is going to need during its lifetime and
109 * set only 'src_start' and 'dst_start' before submitting the requests.
112 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
113 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
120 * struct data_chunk - Element of scatter-gather list that makes a frame.
121 * @size: Number of bytes to read from source.
122 * size_dst := fn(op, size_src), so doesn't mean much for destination.
123 * @icg: Number of bytes to jump after last src/dst address of this
124 * chunk and before first src/dst address for next chunk.
125 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
126 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
127 * @dst_icg: Number of bytes to jump after last dst address of this
128 * chunk and before the first dst address for next chunk.
129 * Ignored if dst_inc is true and dst_sgl is false.
130 * @src_icg: Number of bytes to jump after last src address of this
131 * chunk and before the first src address for next chunk.
132 * Ignored if src_inc is true and src_sgl is false.
142 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
144 * @src_start: Bus address of source for the first chunk.
145 * @dst_start: Bus address of destination for the first chunk.
146 * @dir: Specifies the type of Source and Destination.
147 * @src_inc: If the source address increments after reading from it.
148 * @dst_inc: If the destination address increments after writing to it.
149 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
150 * Otherwise, source is read contiguously (icg ignored).
151 * Ignored if src_inc is false.
152 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
153 * Otherwise, destination is filled contiguously (icg ignored).
154 * Ignored if dst_inc is false.
155 * @numf: Number of frames in this template.
156 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
157 * @sgl: Array of {chunk,icg} pairs that make up a frame.
159 struct dma_interleaved_template
{
160 dma_addr_t src_start
;
161 dma_addr_t dst_start
;
162 enum dma_transfer_direction dir
;
169 struct data_chunk sgl
[0];
173 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
174 * control completion, and communicate status.
175 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
177 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
178 * acknowledges receipt, i.e. has has a chance to establish any dependency
180 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
181 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
182 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
183 * sources that were the result of a previous operation, in the case of a PQ
184 * operation it continues the calculation with new sources
185 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
186 * on the result of this operation
187 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
190 enum dma_ctrl_flags
{
191 DMA_PREP_INTERRUPT
= (1 << 0),
192 DMA_CTRL_ACK
= (1 << 1),
193 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
194 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
195 DMA_PREP_CONTINUE
= (1 << 4),
196 DMA_PREP_FENCE
= (1 << 5),
197 DMA_CTRL_REUSE
= (1 << 6),
201 * enum sum_check_bits - bit position of pq_check_flags
203 enum sum_check_bits
{
209 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
210 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
211 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
213 enum sum_check_flags
{
214 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
215 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
220 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
221 * See linux/cpumask.h
223 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
226 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
227 * @memcpy_count: transaction counter
228 * @bytes_transferred: byte counter
231 struct dma_chan_percpu
{
233 unsigned long memcpy_count
;
234 unsigned long bytes_transferred
;
238 * struct dma_router - DMA router structure
239 * @dev: pointer to the DMA router device
240 * @route_free: function to be called when the route can be disconnected
244 void (*route_free
)(struct device
*dev
, void *route_data
);
248 * struct dma_chan - devices supply DMA channels, clients use them
249 * @device: ptr to the dma device who supplies this channel, always !%NULL
250 * @cookie: last cookie value returned to client
251 * @completed_cookie: last completed cookie for this channel
252 * @chan_id: channel ID for sysfs
253 * @dev: class device for sysfs
254 * @device_node: used to add this to the device chan list
255 * @local: per-cpu pointer to a struct dma_chan_percpu
256 * @client_count: how many clients are using this channel
257 * @table_count: number of appearances in the mem-to-mem allocation table
258 * @router: pointer to the DMA router structure
259 * @route_data: channel specific data for the router
260 * @private: private data for certain client-channel associations
263 struct dma_device
*device
;
265 dma_cookie_t completed_cookie
;
269 struct dma_chan_dev
*dev
;
271 struct list_head device_node
;
272 struct dma_chan_percpu __percpu
*local
;
277 struct dma_router
*router
;
284 * struct dma_chan_dev - relate sysfs device node to backing channel device
285 * @chan: driver channel device
286 * @device: sysfs device
287 * @dev_id: parent dma_device dev_id
288 * @idr_ref: reference count to gate release of dma_device dev_id
290 struct dma_chan_dev
{
291 struct dma_chan
*chan
;
292 struct device device
;
298 * enum dma_slave_buswidth - defines bus width of the DMA slave
299 * device, source or target buses
301 enum dma_slave_buswidth
{
302 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
303 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
304 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
305 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
306 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
307 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
308 DMA_SLAVE_BUSWIDTH_16_BYTES
= 16,
309 DMA_SLAVE_BUSWIDTH_32_BYTES
= 32,
310 DMA_SLAVE_BUSWIDTH_64_BYTES
= 64,
314 * struct dma_slave_config - dma slave channel runtime config
315 * @direction: whether the data shall go in or out on this slave
316 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
317 * legal values. DEPRECATED, drivers should use the direction argument
318 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
319 * the dir field in the dma_interleaved_template structure.
320 * @src_addr: this is the physical address where DMA slave data
321 * should be read (RX), if the source is memory this argument is
323 * @dst_addr: this is the physical address where DMA slave data
324 * should be written (TX), if the source is memory this argument
326 * @src_addr_width: this is the width in bytes of the source (RX)
327 * register where DMA data shall be read. If the source
328 * is memory this may be ignored depending on architecture.
329 * Legal values: 1, 2, 4, 8.
330 * @dst_addr_width: same as src_addr_width but for destination
331 * target (TX) mutatis mutandis.
332 * @src_maxburst: the maximum number of words (note: words, as in
333 * units of the src_addr_width member, not bytes) that can be sent
334 * in one burst to the device. Typically something like half the
335 * FIFO depth on I/O peripherals so you don't overflow it. This
336 * may or may not be applicable on memory sources.
337 * @dst_maxburst: same as src_maxburst but for destination target
339 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
340 * with 'true' if peripheral should be flow controller. Direction will be
341 * selected at Runtime.
342 * @slave_id: Slave requester id. Only valid for slave channels. The dma
343 * slave peripheral will have unique id as dma requester which need to be
344 * pass as slave config.
346 * This struct is passed in as configuration data to a DMA engine
347 * in order to set up a certain channel for DMA transport at runtime.
348 * The DMA device/engine has to provide support for an additional
349 * callback in the dma_device structure, device_config and this struct
350 * will then be passed in as an argument to the function.
352 * The rationale for adding configuration information to this struct is as
353 * follows: if it is likely that more than one DMA slave controllers in
354 * the world will support the configuration option, then make it generic.
355 * If not: if it is fixed so that it be sent in static from the platform
356 * data, then prefer to do that.
358 struct dma_slave_config
{
359 enum dma_transfer_direction direction
;
360 phys_addr_t src_addr
;
361 phys_addr_t dst_addr
;
362 enum dma_slave_buswidth src_addr_width
;
363 enum dma_slave_buswidth dst_addr_width
;
367 unsigned int slave_id
;
371 * enum dma_residue_granularity - Granularity of the reported transfer residue
372 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
373 * DMA channel is only able to tell whether a descriptor has been completed or
374 * not, which means residue reporting is not supported by this channel. The
375 * residue field of the dma_tx_state field will always be 0.
376 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
377 * completed segment of the transfer (For cyclic transfers this is after each
378 * period). This is typically implemented by having the hardware generate an
379 * interrupt after each transferred segment and then the drivers updates the
380 * outstanding residue by the size of the segment. Another possibility is if
381 * the hardware supports scatter-gather and the segment descriptor has a field
382 * which gets set after the segment has been completed. The driver then counts
383 * the number of segments without the flag set to compute the residue.
384 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
385 * burst. This is typically only supported if the hardware has a progress
386 * register of some sort (E.g. a register with the current read/write address
387 * or a register with the amount of bursts/beats/bytes that have been
388 * transferred or still need to be transferred).
390 enum dma_residue_granularity
{
391 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
392 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
393 DMA_RESIDUE_GRANULARITY_BURST
= 2,
396 /* struct dma_slave_caps - expose capabilities of a slave channel only
398 * @src_addr_widths: bit mask of src addr widths the channel supports
399 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
400 * @directions: bit mask of slave direction the channel supported
401 * since the enum dma_transfer_direction is not defined as bits for each
402 * type of direction, the dma controller should fill (1 << <TYPE>) and same
403 * should be checked by controller as well
404 * @max_burst: max burst capability per-transfer
405 * @cmd_pause: true, if pause and thereby resume is supported
406 * @cmd_terminate: true, if terminate cmd is supported
407 * @residue_granularity: granularity of the reported transfer residue
408 * @descriptor_reuse: if a descriptor can be reused by client and
409 * resubmitted multiple times
411 struct dma_slave_caps
{
418 enum dma_residue_granularity residue_granularity
;
419 bool descriptor_reuse
;
422 static inline const char *dma_chan_name(struct dma_chan
*chan
)
424 return dev_name(&chan
->dev
->device
);
427 void dma_chan_cleanup(struct kref
*kref
);
430 * typedef dma_filter_fn - callback filter for dma_request_channel
431 * @chan: channel to be reviewed
432 * @filter_param: opaque parameter passed through dma_request_channel
434 * When this optional parameter is specified in a call to dma_request_channel a
435 * suitable channel is passed to this routine for further dispositioning before
436 * being returned. Where 'suitable' indicates a non-busy channel that
437 * satisfies the given capability mask. It returns 'true' to indicate that the
438 * channel is suitable.
440 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
442 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
444 struct dmaengine_unmap_data
{
456 * struct dma_async_tx_descriptor - async transaction descriptor
457 * ---dma generic offload fields---
458 * @cookie: tracking cookie for this transaction, set to -EBUSY if
459 * this tx is sitting on a dependency list
460 * @flags: flags to augment operation preparation, control completion, and
462 * @phys: physical address of the descriptor
463 * @chan: target channel for this operation
464 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
465 * descriptor pending. To be pushed on .issue_pending() call
466 * @callback: routine to call after this operation is complete
467 * @callback_param: general parameter to pass to the callback routine
468 * ---async_tx api specific fields---
469 * @next: at completion submit this descriptor
470 * @parent: pointer to the next level up in the dependency chain
471 * @lock: protect the parent and next pointers
473 struct dma_async_tx_descriptor
{
475 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
477 struct dma_chan
*chan
;
478 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
479 int (*desc_free
)(struct dma_async_tx_descriptor
*tx
);
480 dma_async_tx_callback callback
;
481 void *callback_param
;
482 struct dmaengine_unmap_data
*unmap
;
483 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
484 struct dma_async_tx_descriptor
*next
;
485 struct dma_async_tx_descriptor
*parent
;
490 #ifdef CONFIG_DMA_ENGINE
491 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
492 struct dmaengine_unmap_data
*unmap
)
494 kref_get(&unmap
->kref
);
498 struct dmaengine_unmap_data
*
499 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
500 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
502 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
503 struct dmaengine_unmap_data
*unmap
)
506 static inline struct dmaengine_unmap_data
*
507 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
511 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
516 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
519 dmaengine_unmap_put(tx
->unmap
);
524 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
525 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
528 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
531 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
535 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
538 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
541 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
545 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
551 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
553 spin_lock_bh(&txd
->lock
);
555 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
557 spin_unlock_bh(&txd
->lock
);
559 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
564 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
568 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
572 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
576 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
583 * struct dma_tx_state - filled in to report the status of
585 * @last: last completed DMA cookie
586 * @used: last issued DMA cookie (i.e. the one in progress)
587 * @residue: the remaining number of bytes left to transmit
588 * on the selected transfer for states DMA_IN_PROGRESS and
589 * DMA_PAUSED if this is implemented in the driver, else 0
591 struct dma_tx_state
{
598 * enum dmaengine_alignment - defines alignment of the DMA async tx
601 enum dmaengine_alignment
{
602 DMAENGINE_ALIGN_1_BYTE
= 0,
603 DMAENGINE_ALIGN_2_BYTES
= 1,
604 DMAENGINE_ALIGN_4_BYTES
= 2,
605 DMAENGINE_ALIGN_8_BYTES
= 3,
606 DMAENGINE_ALIGN_16_BYTES
= 4,
607 DMAENGINE_ALIGN_32_BYTES
= 5,
608 DMAENGINE_ALIGN_64_BYTES
= 6,
612 * struct dma_slave_map - associates slave device and it's slave channel with
613 * parameter to be used by a filter function
614 * @devname: name of the device
615 * @slave: slave channel name
616 * @param: opaque parameter to pass to struct dma_filter.fn
618 struct dma_slave_map
{
625 * struct dma_filter - information for slave device/channel to filter_fn/param
627 * @fn: filter function callback
628 * @mapcnt: number of slave device/channel in the map
629 * @map: array of channel to filter mapping data
634 const struct dma_slave_map
*map
;
638 * struct dma_device - info on the entity supplying DMA services
639 * @chancnt: how many DMA channels are supported
640 * @privatecnt: how many DMA channels are requested by dma_request_channel
641 * @channels: the list of struct dma_chan
642 * @global_node: list_head for global dma_device_list
643 * @filter: information for device/slave to filter function/param mapping
644 * @cap_mask: one or more dma_capability flags
645 * @max_xor: maximum number of xor sources, 0 if no capability
646 * @max_pq: maximum number of PQ sources and PQ-continue capability
647 * @copy_align: alignment shift for memcpy operations
648 * @xor_align: alignment shift for xor operations
649 * @pq_align: alignment shift for pq operations
650 * @fill_align: alignment shift for memset operations
651 * @dev_id: unique device ID
652 * @dev: struct device reference for dma mapping api
653 * @src_addr_widths: bit mask of src addr widths the device supports
654 * @dst_addr_widths: bit mask of dst addr widths the device supports
655 * @directions: bit mask of slave direction the device supports since
656 * the enum dma_transfer_direction is not defined as bits for
657 * each type of direction, the dma controller should fill (1 <<
658 * <TYPE>) and same should be checked by controller as well
659 * @max_burst: max burst capability per-transfer
660 * @residue_granularity: granularity of the transfer residue reported
662 * @device_alloc_chan_resources: allocate resources and return the
663 * number of allocated descriptors
664 * @device_free_chan_resources: release DMA channel's resources
665 * @device_prep_dma_memcpy: prepares a memcpy operation
666 * @device_prep_dma_xor: prepares a xor operation
667 * @device_prep_dma_xor_val: prepares a xor validation operation
668 * @device_prep_dma_pq: prepares a pq operation
669 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
670 * @device_prep_dma_memset: prepares a memset operation
671 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
672 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
673 * @device_prep_slave_sg: prepares a slave dma operation
674 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
675 * The function takes a buffer of size buf_len. The callback function will
676 * be called after period_len bytes have been transferred.
677 * @device_prep_interleaved_dma: Transfer expression in a generic way.
678 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
679 * @device_config: Pushes a new configuration to a channel, return 0 or an error
681 * @device_pause: Pauses any transfer happening on a channel. Returns
683 * @device_resume: Resumes any transfer on a channel previously
684 * paused. Returns 0 or an error code
685 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
687 * @device_synchronize: Synchronizes the termination of a transfers to the
689 * @device_tx_status: poll for transaction completion, the optional
690 * txstate parameter can be supplied with a pointer to get a
691 * struct with auxiliary transfer status information, otherwise the call
692 * will just return a simple status code
693 * @device_issue_pending: push pending transactions to hardware
694 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
698 unsigned int chancnt
;
699 unsigned int privatecnt
;
700 struct list_head channels
;
701 struct list_head global_node
;
702 struct dma_filter filter
;
703 dma_cap_mask_t cap_mask
;
704 unsigned short max_xor
;
705 unsigned short max_pq
;
706 enum dmaengine_alignment copy_align
;
707 enum dmaengine_alignment xor_align
;
708 enum dmaengine_alignment pq_align
;
709 enum dmaengine_alignment fill_align
;
710 #define DMA_HAS_PQ_CONTINUE (1 << 15)
719 bool descriptor_reuse
;
720 enum dma_residue_granularity residue_granularity
;
722 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
723 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
725 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
726 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
727 size_t len
, unsigned long flags
);
728 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
729 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
730 unsigned int src_cnt
, size_t len
, unsigned long flags
);
731 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
732 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
733 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
734 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
735 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
736 unsigned int src_cnt
, const unsigned char *scf
,
737 size_t len
, unsigned long flags
);
738 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
739 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
740 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
741 enum sum_check_flags
*pqres
, unsigned long flags
);
742 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
743 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
744 unsigned long flags
);
745 struct dma_async_tx_descriptor
*(*device_prep_dma_memset_sg
)(
746 struct dma_chan
*chan
, struct scatterlist
*sg
,
747 unsigned int nents
, int value
, unsigned long flags
);
748 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
749 struct dma_chan
*chan
, unsigned long flags
);
750 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
751 struct dma_chan
*chan
,
752 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
753 struct scatterlist
*src_sg
, unsigned int src_nents
,
754 unsigned long flags
);
756 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
757 struct dma_chan
*chan
, struct scatterlist
*sgl
,
758 unsigned int sg_len
, enum dma_transfer_direction direction
,
759 unsigned long flags
, void *context
);
760 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
761 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
762 size_t period_len
, enum dma_transfer_direction direction
,
763 unsigned long flags
);
764 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
765 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
766 unsigned long flags
);
767 struct dma_async_tx_descriptor
*(*device_prep_dma_imm_data
)(
768 struct dma_chan
*chan
, dma_addr_t dst
, u64 data
,
769 unsigned long flags
);
771 int (*device_config
)(struct dma_chan
*chan
,
772 struct dma_slave_config
*config
);
773 int (*device_pause
)(struct dma_chan
*chan
);
774 int (*device_resume
)(struct dma_chan
*chan
);
775 int (*device_terminate_all
)(struct dma_chan
*chan
);
776 void (*device_synchronize
)(struct dma_chan
*chan
);
778 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
780 struct dma_tx_state
*txstate
);
781 void (*device_issue_pending
)(struct dma_chan
*chan
);
784 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
785 struct dma_slave_config
*config
)
787 if (chan
->device
->device_config
)
788 return chan
->device
->device_config(chan
, config
);
793 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
795 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
798 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
799 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
800 enum dma_transfer_direction dir
, unsigned long flags
)
802 struct scatterlist sg
;
803 sg_init_table(&sg
, 1);
804 sg_dma_address(&sg
) = buf
;
805 sg_dma_len(&sg
) = len
;
807 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
811 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
812 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
813 enum dma_transfer_direction dir
, unsigned long flags
)
815 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
819 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
821 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
822 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
823 enum dma_transfer_direction dir
, unsigned long flags
,
824 struct rio_dma_ext
*rio_ext
)
826 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
827 dir
, flags
, rio_ext
);
831 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
832 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
833 size_t period_len
, enum dma_transfer_direction dir
,
836 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
837 period_len
, dir
, flags
);
840 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
841 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
844 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
847 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memset(
848 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
851 if (!chan
|| !chan
->device
)
854 return chan
->device
->device_prep_dma_memset(chan
, dest
, value
,
858 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_sg(
859 struct dma_chan
*chan
,
860 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
861 struct scatterlist
*src_sg
, unsigned int src_nents
,
864 return chan
->device
->device_prep_dma_sg(chan
, dst_sg
, dst_nents
,
865 src_sg
, src_nents
, flags
);
869 * dmaengine_terminate_all() - Terminate all active DMA transfers
870 * @chan: The channel for which to terminate the transfers
872 * This function is DEPRECATED use either dmaengine_terminate_sync() or
873 * dmaengine_terminate_async() instead.
875 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
877 if (chan
->device
->device_terminate_all
)
878 return chan
->device
->device_terminate_all(chan
);
884 * dmaengine_terminate_async() - Terminate all active DMA transfers
885 * @chan: The channel for which to terminate the transfers
887 * Calling this function will terminate all active and pending descriptors
888 * that have previously been submitted to the channel. It is not guaranteed
889 * though that the transfer for the active descriptor has stopped when the
890 * function returns. Furthermore it is possible the complete callback of a
891 * submitted transfer is still running when this function returns.
893 * dmaengine_synchronize() needs to be called before it is safe to free
894 * any memory that is accessed by previously submitted descriptors or before
895 * freeing any resources accessed from within the completion callback of any
896 * perviously submitted descriptors.
898 * This function can be called from atomic context as well as from within a
899 * complete callback of a descriptor submitted on the same channel.
901 * If none of the two conditions above apply consider using
902 * dmaengine_terminate_sync() instead.
904 static inline int dmaengine_terminate_async(struct dma_chan
*chan
)
906 if (chan
->device
->device_terminate_all
)
907 return chan
->device
->device_terminate_all(chan
);
913 * dmaengine_synchronize() - Synchronize DMA channel termination
914 * @chan: The channel to synchronize
916 * Synchronizes to the DMA channel termination to the current context. When this
917 * function returns it is guaranteed that all transfers for previously issued
918 * descriptors have stopped and and it is safe to free the memory assoicated
919 * with them. Furthermore it is guaranteed that all complete callback functions
920 * for a previously submitted descriptor have finished running and it is safe to
921 * free resources accessed from within the complete callbacks.
923 * The behavior of this function is undefined if dma_async_issue_pending() has
924 * been called between dmaengine_terminate_async() and this function.
926 * This function must only be called from non-atomic context and must not be
927 * called from within a complete callback of a descriptor submitted on the same
930 static inline void dmaengine_synchronize(struct dma_chan
*chan
)
934 if (chan
->device
->device_synchronize
)
935 chan
->device
->device_synchronize(chan
);
939 * dmaengine_terminate_sync() - Terminate all active DMA transfers
940 * @chan: The channel for which to terminate the transfers
942 * Calling this function will terminate all active and pending transfers
943 * that have previously been submitted to the channel. It is similar to
944 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
945 * stopped and that all complete callbacks have finished running when the
948 * This function must only be called from non-atomic context and must not be
949 * called from within a complete callback of a descriptor submitted on the same
952 static inline int dmaengine_terminate_sync(struct dma_chan
*chan
)
956 ret
= dmaengine_terminate_async(chan
);
960 dmaengine_synchronize(chan
);
965 static inline int dmaengine_pause(struct dma_chan
*chan
)
967 if (chan
->device
->device_pause
)
968 return chan
->device
->device_pause(chan
);
973 static inline int dmaengine_resume(struct dma_chan
*chan
)
975 if (chan
->device
->device_resume
)
976 return chan
->device
->device_resume(chan
);
981 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
982 dma_cookie_t cookie
, struct dma_tx_state
*state
)
984 return chan
->device
->device_tx_status(chan
, cookie
, state
);
987 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
989 return desc
->tx_submit(desc
);
992 static inline bool dmaengine_check_align(enum dmaengine_alignment align
,
993 size_t off1
, size_t off2
, size_t len
)
999 mask
= (1 << align
) - 1;
1000 if (mask
& (off1
| off2
| len
))
1005 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
1006 size_t off2
, size_t len
)
1008 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
1011 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
1012 size_t off2
, size_t len
)
1014 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
1017 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
1018 size_t off2
, size_t len
)
1020 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
1023 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
1024 size_t off2
, size_t len
)
1026 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
1030 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
1032 dma
->max_pq
= maxpq
;
1033 if (has_pq_continue
)
1034 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
1037 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
1039 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
1042 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
1044 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
1046 return (flags
& mask
) == mask
;
1049 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
1051 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
1054 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
1056 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
1059 /* dma_maxpq - reduce maxpq in the face of continued operations
1060 * @dma - dma device with PQ capability
1061 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1063 * When an engine does not support native continuation we need 3 extra
1064 * source slots to reuse P and Q with the following coefficients:
1065 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1066 * 2/ {01} * Q : use Q to continue Q' calculation
1067 * 3/ {00} * Q : subtract Q from P' to cancel (2)
1069 * In the case where P is disabled we only need 1 extra source:
1070 * 1/ {01} * Q : use Q to continue Q' calculation
1072 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
1074 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
1075 return dma_dev_to_maxpq(dma
);
1076 else if (dmaf_p_disabled_continue(flags
))
1077 return dma_dev_to_maxpq(dma
) - 1;
1078 else if (dmaf_continue(flags
))
1079 return dma_dev_to_maxpq(dma
) - 3;
1083 static inline size_t dmaengine_get_icg(bool inc
, bool sgl
, size_t icg
,
1096 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template
*xt
,
1097 struct data_chunk
*chunk
)
1099 return dmaengine_get_icg(xt
->dst_inc
, xt
->dst_sgl
,
1100 chunk
->icg
, chunk
->dst_icg
);
1103 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template
*xt
,
1104 struct data_chunk
*chunk
)
1106 return dmaengine_get_icg(xt
->src_inc
, xt
->src_sgl
,
1107 chunk
->icg
, chunk
->src_icg
);
1110 /* --- public DMA engine API --- */
1112 #ifdef CONFIG_DMA_ENGINE
1113 void dmaengine_get(void);
1114 void dmaengine_put(void);
1116 static inline void dmaengine_get(void)
1119 static inline void dmaengine_put(void)
1124 #ifdef CONFIG_ASYNC_TX_DMA
1125 #define async_dmaengine_get() dmaengine_get()
1126 #define async_dmaengine_put() dmaengine_put()
1127 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1128 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1130 #define async_dma_find_channel(type) dma_find_channel(type)
1131 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1133 static inline void async_dmaengine_get(void)
1136 static inline void async_dmaengine_put(void)
1139 static inline struct dma_chan
*
1140 async_dma_find_channel(enum dma_transaction_type type
)
1144 #endif /* CONFIG_ASYNC_TX_DMA */
1145 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
1146 struct dma_chan
*chan
);
1148 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
1150 tx
->flags
|= DMA_CTRL_ACK
;
1153 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
1155 tx
->flags
&= ~DMA_CTRL_ACK
;
1158 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
1160 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
1163 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1165 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1167 set_bit(tx_type
, dstp
->bits
);
1170 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1172 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1174 clear_bit(tx_type
, dstp
->bits
);
1177 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1178 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
1180 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
1183 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1185 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
1187 return test_bit(tx_type
, srcp
->bits
);
1190 #define for_each_dma_cap_mask(cap, mask) \
1191 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1194 * dma_async_issue_pending - flush pending transactions to HW
1195 * @chan: target DMA channel
1197 * This allows drivers to push copies to HW in batches,
1198 * reducing MMIO writes where possible.
1200 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
1202 chan
->device
->device_issue_pending(chan
);
1206 * dma_async_is_tx_complete - poll for transaction completion
1207 * @chan: DMA channel
1208 * @cookie: transaction identifier to check status of
1209 * @last: returns last completed cookie, can be NULL
1210 * @used: returns last issued cookie, can be NULL
1212 * If @last and @used are passed in, upon return they reflect the driver
1213 * internal state and can be used with dma_async_is_complete() to check
1214 * the status of multiple cookies without re-checking hardware state.
1216 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
1217 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
1219 struct dma_tx_state state
;
1220 enum dma_status status
;
1222 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
1231 * dma_async_is_complete - test a cookie against chan state
1232 * @cookie: transaction identifier to test status of
1233 * @last_complete: last know completed transaction
1234 * @last_used: last cookie value handed out
1236 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1237 * the test logic is separated for lightweight testing of multiple cookies
1239 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1240 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1242 if (last_complete
<= last_used
) {
1243 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1244 return DMA_COMPLETE
;
1246 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1247 return DMA_COMPLETE
;
1249 return DMA_IN_PROGRESS
;
1253 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1258 st
->residue
= residue
;
1262 #ifdef CONFIG_DMA_ENGINE
1263 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1264 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1265 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1266 void dma_issue_pending_all(void);
1267 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1268 dma_filter_fn fn
, void *fn_param
);
1269 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1271 struct dma_chan
*dma_request_chan(struct device
*dev
, const char *name
);
1272 struct dma_chan
*dma_request_chan_by_mask(const dma_cap_mask_t
*mask
);
1274 void dma_release_channel(struct dma_chan
*chan
);
1275 int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
1277 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1281 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1283 return DMA_COMPLETE
;
1285 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1287 return DMA_COMPLETE
;
1289 static inline void dma_issue_pending_all(void)
1292 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1293 dma_filter_fn fn
, void *fn_param
)
1297 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1302 static inline struct dma_chan
*dma_request_chan(struct device
*dev
,
1305 return ERR_PTR(-ENODEV
);
1307 static inline struct dma_chan
*dma_request_chan_by_mask(
1308 const dma_cap_mask_t
*mask
)
1310 return ERR_PTR(-ENODEV
);
1312 static inline void dma_release_channel(struct dma_chan
*chan
)
1315 static inline int dma_get_slave_caps(struct dma_chan
*chan
,
1316 struct dma_slave_caps
*caps
)
1322 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1324 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor
*tx
)
1326 struct dma_slave_caps caps
;
1328 dma_get_slave_caps(tx
->chan
, &caps
);
1330 if (caps
.descriptor_reuse
) {
1331 tx
->flags
|= DMA_CTRL_REUSE
;
1338 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor
*tx
)
1340 tx
->flags
&= ~DMA_CTRL_REUSE
;
1343 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor
*tx
)
1345 return (tx
->flags
& DMA_CTRL_REUSE
) == DMA_CTRL_REUSE
;
1348 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor
*desc
)
1350 /* this is supported for reusable desc, so check that */
1351 if (dmaengine_desc_test_reuse(desc
))
1352 return desc
->desc_free(desc
);
1357 /* --- DMA device --- */
1359 int dma_async_device_register(struct dma_device
*device
);
1360 void dma_async_device_unregister(struct dma_device
*device
);
1361 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1362 struct dma_chan
*dma_get_slave_channel(struct dma_chan
*chan
);
1363 struct dma_chan
*dma_get_any_slave_channel(struct dma_device
*device
);
1364 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1365 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1366 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1368 static inline struct dma_chan
1369 *__dma_request_slave_channel_compat(const dma_cap_mask_t
*mask
,
1370 dma_filter_fn fn
, void *fn_param
,
1371 struct device
*dev
, const char *name
)
1373 struct dma_chan
*chan
;
1375 chan
= dma_request_slave_channel(dev
, name
);
1379 if (!fn
|| !fn_param
)
1382 return __dma_request_channel(mask
, fn
, fn_param
);
1384 #endif /* DMAENGINE_H */