include/linux/dw_dmac.h

   1 /*
   2  * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
   3  * AVR32 systems.)
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  * Copyright (C) 2010-2011 ST Microelectronics
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #ifndef DW_DMAC_H
  13 #define DW_DMAC_H
  14
  15 #include <linux/dmaengine.h>
  16
  17 /**
  18  * struct dw_dma_platform_data - Controller configuration parameters
  19  * @nr_channels: Number of channels supported by hardware (max 8)
  20  * @is_private: The device channels should be marked as private and not for
  21  *      by the general purpose DMA channel allocator.
  22  * @block_size: Maximum block size supported by the controller
  23  * @nr_masters: Number of AHB masters supported by the controller
  24  * @data_width: Maximum data width supported by hardware per AHB master
  25  *              (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
  26  */
  27 struct dw_dma_platform_data {
  28         unsigned int    nr_channels;
  29         bool            is_private;
  30 #define CHAN_ALLOCATION_ASCENDING       0       /* zero to seven */
  31 #define CHAN_ALLOCATION_DESCENDING      1       /* seven to zero */
  32         unsigned char   chan_allocation_order;
  33 #define CHAN_PRIORITY_ASCENDING         0       /* chan0 highest */
  34 #define CHAN_PRIORITY_DESCENDING        1       /* chan7 highest */
  35         unsigned char   chan_priority;
  36         unsigned short  block_size;
  37         unsigned char   nr_masters;
  38         unsigned char   data_width[4];
  39 };
  40
  41 /* bursts size */
  42 enum dw_dma_msize {
  43         DW_DMA_MSIZE_1,
  44         DW_DMA_MSIZE_4,
  45         DW_DMA_MSIZE_8,
  46         DW_DMA_MSIZE_16,
  47         DW_DMA_MSIZE_32,
  48         DW_DMA_MSIZE_64,
  49         DW_DMA_MSIZE_128,
  50         DW_DMA_MSIZE_256,
  51 };
  52
  53 /**
  54  * struct dw_dma_slave - Controller-specific information about a slave
  55  *
  56  * @dma_dev: required DMA master device
  57  * @cfg_hi: Platform-specific initializer for the CFG_HI register
  58  * @cfg_lo: Platform-specific initializer for the CFG_LO register
  59  * @src_master: src master for transfers on allocated channel.
  60  * @dst_master: dest master for transfers on allocated channel.
  61  */
  62 struct dw_dma_slave {
  63         struct device           *dma_dev;
  64         u32                     cfg_hi;
  65         u32                     cfg_lo;
  66         u8                      src_master;
  67         u8                      dst_master;
  68 };
  69
  70 /* Platform-configurable bits in CFG_HI */
  71 #define DWC_CFGH_FCMODE         (1 << 0)
  72 #define DWC_CFGH_FIFO_MODE      (1 << 1)
  73 #define DWC_CFGH_PROTCTL(x)     ((x) << 2)
  74 #define DWC_CFGH_SRC_PER(x)     ((x) << 7)
  75 #define DWC_CFGH_DST_PER(x)     ((x) << 11)
  76
  77 /* Platform-configurable bits in CFG_LO */
  78 #define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
  79 #define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
  80 #define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
  81 #define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
  82 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
  83 #define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
  84 #define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
  85 #define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
  86 #define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
  87 #define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
  88
  89 /* DMA API extensions */
  90 struct dw_cyclic_desc {
  91         struct dw_desc  **desc;
  92         unsigned long   periods;
  93         void            (*period_callback)(void *param);
  94         void            *period_callback_param;
  95 };
  96
  97 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
  98                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
  99                 enum dma_transfer_direction direction);
 100 void dw_dma_cyclic_free(struct dma_chan *chan);
 101 int dw_dma_cyclic_start(struct dma_chan *chan);
 102 void dw_dma_cyclic_stop(struct dma_chan *chan);
 103
 104 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
 105
 106 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
 107
 108 #endif /* DW_DMAC_H */