include/linux/edac.h

   1 /*
   2  * Generic EDAC defs
   3  *
   4  * Author: Dave Jiang <djiang@mvista.com>
   5  *
   6  * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  *
  11  */
  12 #ifndef _LINUX_EDAC_H_
  13 #define _LINUX_EDAC_H_
  14
  15 #include <linux/atomic.h>
  16 #include <linux/kobject.h>
  17 #include <linux/completion.h>
  18 #include <linux/workqueue.h>
  19
  20 struct device;
  21
  22 #define EDAC_OPSTATE_INVAL      -1
  23 #define EDAC_OPSTATE_POLL       0
  24 #define EDAC_OPSTATE_NMI        1
  25 #define EDAC_OPSTATE_INT        2
  26
  27 extern int edac_op_state;
  28 extern int edac_err_assert;
  29 extern atomic_t edac_handlers;
  30 extern struct bus_type edac_subsys;
  31
  32 extern int edac_handler_set(void);
  33 extern void edac_atomic_assert_error(void);
  34 extern struct bus_type *edac_get_sysfs_subsys(void);
  35 extern void edac_put_sysfs_subsys(void);
  36
  37 static inline void opstate_init(void)
  38 {
  39         switch (edac_op_state) {
  40         case EDAC_OPSTATE_POLL:
  41         case EDAC_OPSTATE_NMI:
  42                 break;
  43         default:
  44                 edac_op_state = EDAC_OPSTATE_POLL;
  45         }
  46         return;
  47 }
  48
  49 #define EDAC_MC_LABEL_LEN       31
  50 #define MC_PROC_NAME_MAX_LEN    7
  51
  52 /* memory devices */
  53 enum dev_type {
  54         DEV_UNKNOWN = 0,
  55         DEV_X1,
  56         DEV_X2,
  57         DEV_X4,
  58         DEV_X8,
  59         DEV_X16,
  60         DEV_X32,                /* Do these parts exist? */
  61         DEV_X64                 /* Do these parts exist? */
  62 };
  63
  64 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
  65 #define DEV_FLAG_X1             BIT(DEV_X1)
  66 #define DEV_FLAG_X2             BIT(DEV_X2)
  67 #define DEV_FLAG_X4             BIT(DEV_X4)
  68 #define DEV_FLAG_X8             BIT(DEV_X8)
  69 #define DEV_FLAG_X16            BIT(DEV_X16)
  70 #define DEV_FLAG_X32            BIT(DEV_X32)
  71 #define DEV_FLAG_X64            BIT(DEV_X64)
  72
  73 /**
  74  * enum mem_type - memory types. For a more detailed reference, please see
  75  *                      http://en.wikipedia.org/wiki/DRAM
  76  *
  77  * @MEM_EMPTY           Empty csrow
  78  * @MEM_RESERVED:       Reserved csrow type
  79  * @MEM_UNKNOWN:        Unknown csrow type
  80  * @MEM_FPM:            FPM - Fast Page Mode, used on systems up to 1995.
  81  * @MEM_EDO:            EDO - Extended data out, used on systems up to 1998.
  82  * @MEM_BEDO:           BEDO - Burst Extended data out, an EDO variant.
  83  * @MEM_SDR:            SDR - Single data rate SDRAM
  84  *                      http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
  85  *                      They use 3 pins for chip select: Pins 0 and 2 are
  86  *                      for rank 0; pins 1 and 3 are for rank 1, if the memory
  87  *                      is dual-rank.
  88  * @MEM_RDR:            Registered SDR SDRAM
  89  * @MEM_DDR:            Double data rate SDRAM
  90  *                      http://en.wikipedia.org/wiki/DDR_SDRAM
  91  * @MEM_RDDR:           Registered Double data rate SDRAM
  92  *                      This is a variant of the DDR memories.
  93  *                      A registered memory has a buffer inside it, hiding
  94  *                      part of the memory details to the memory controller.
  95  * @MEM_RMBS:           Rambus DRAM, used on a few Pentium III/IV controllers.
  96  * @MEM_DDR2:           DDR2 RAM, as described at JEDEC JESD79-2F.
  97  *                      Those memories are labed as "PC2-" instead of "PC" to
  98  *                      differenciate from DDR.
  99  * @MEM_FB_DDR2:        Fully-Buffered DDR2, as described at JEDEC Std No. 205
 100  *                      and JESD206.
 101  *                      Those memories are accessed per DIMM slot, and not by
 102  *                      a chip select signal.
 103  * @MEM_RDDR2:          Registered DDR2 RAM
 104  *                      This is a variant of the DDR2 memories.
 105  * @MEM_XDR:            Rambus XDR
 106  *                      It is an evolution of the original RAMBUS memories,
 107  *                      created to compete with DDR2. Weren't used on any
 108  *                      x86 arch, but cell_edac PPC memory controller uses it.
 109  * @MEM_DDR3:           DDR3 RAM
 110  * @MEM_RDDR3:          Registered DDR3 RAM
 111  *                      This is a variant of the DDR3 memories.
 112  */
 113 enum mem_type {
 114         MEM_EMPTY = 0,
 115         MEM_RESERVED,
 116         MEM_UNKNOWN,
 117         MEM_FPM,
 118         MEM_EDO,
 119         MEM_BEDO,
 120         MEM_SDR,
 121         MEM_RDR,
 122         MEM_DDR,
 123         MEM_RDDR,
 124         MEM_RMBS,
 125         MEM_DDR2,
 126         MEM_FB_DDR2,
 127         MEM_RDDR2,
 128         MEM_XDR,
 129         MEM_DDR3,
 130         MEM_RDDR3,
 131 };
 132
 133 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 134 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 135 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 136 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 137 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 138 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 139 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 140 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 141 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 142 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 143 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 144 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 145 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 146 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 147 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 148 #define MEM_FLAG_DDR3            BIT(MEM_DDR3)
 149 #define MEM_FLAG_RDDR3           BIT(MEM_RDDR3)
 150
 151 /* chipset Error Detection and Correction capabilities and mode */
 152 enum edac_type {
 153         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 154         EDAC_NONE,              /* Doesn't support ECC */
 155         EDAC_RESERVED,          /* Reserved ECC type */
 156         EDAC_PARITY,            /* Detects parity errors */
 157         EDAC_EC,                /* Error Checking - no correction */
 158         EDAC_SECDED,            /* Single bit error correction, Double detection */
 159         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 160         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 161         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 162         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 163 };
 164
 165 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 166 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 167 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 168 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 169 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 170 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 171 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 172 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 173 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 174
 175 /* scrubbing capabilities */
 176 enum scrub_type {
 177         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 178         SCRUB_NONE,             /* No scrubber */
 179         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 180         SCRUB_SW_SRC,           /* Software scrub only errors */
 181         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 182         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 183         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 184         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 185         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 186         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 187 };
 188
 189 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 190 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 191 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 192 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 193 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 194 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 195 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 196 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 197
 198 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 199
 200 /* EDAC internal operation states */
 201 #define OP_ALLOC                0x100
 202 #define OP_RUNNING_POLL         0x201
 203 #define OP_RUNNING_INTERRUPT    0x202
 204 #define OP_RUNNING_POLL_INTR    0x203
 205 #define OP_OFFLINE              0x300
 206
 207 /*
 208  * Concepts used at the EDAC subsystem
 209  *
 210  * There are several things to be aware of that aren't at all obvious:
 211  *
 212  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 213  *
 214  * These are some of the many terms that are thrown about that don't always
 215  * mean what people think they mean (Inconceivable!).  In the interest of
 216  * creating a common ground for discussion, terms and their definitions
 217  * will be established.
 218  *
 219  * Memory devices:      The individual DRAM chips on a memory stick.  These
 220  *                      devices commonly output 4 and 8 bits each (x4, x8).
 221  *                      Grouping several of these in parallel provides the
 222  *                      number of bits that the memory controller expects:
 223  *                      typically 72 bits, in order to provide 64 bits +
 224  *                      8 bits of ECC data.
 225  *
 226  * Memory Stick:        A printed circuit board that aggregates multiple
 227  *                      memory devices in parallel.  In general, this is the
 228  *                      Field Replaceable Unit (FRU) which gets replaced, in
 229  *                      the case of excessive errors. Most often it is also
 230  *                      called DIMM (Dual Inline Memory Module).
 231  *
 232  * Memory Socket:       A physical connector on the motherboard that accepts
 233  *                      a single memory stick. Also called as "slot" on several
 234  *                      datasheets.
 235  *
 236  * Channel:             A memory controller channel, responsible to communicate
 237  *                      with a group of DIMMs. Each channel has its own
 238  *                      independent control (command) and data bus, and can
 239  *                      be used independently or grouped with other channels.
 240  *
 241  * Branch:              It is typically the highest hierarchy on a
 242  *                      Fully-Buffered DIMM memory controller.
 243  *                      Typically, it contains two channels.
 244  *                      Two channels at the same branch can be used in single
 245  *                      mode or in lockstep mode.
 246  *                      When lockstep is enabled, the cacheline is doubled,
 247  *                      but it generally brings some performance penalty.
 248  *                      Also, it is generally not possible to point to just one
 249  *                      memory stick when an error occurs, as the error
 250  *                      correction code is calculated using two DIMMs instead
 251  *                      of one. Due to that, it is capable of correcting more
 252  *                      errors than on single mode.
 253  *
 254  * Single-channel:      The data accessed by the memory controller is contained
 255  *                      into one dimm only. E. g. if the data is 64 bits-wide,
 256  *                      the data flows to the CPU using one 64 bits parallel
 257  *                      access.
 258  *                      Typically used with SDR, DDR, DDR2 and DDR3 memories.
 259  *                      FB-DIMM and RAMBUS use a different concept for channel,
 260  *                      so this concept doesn't apply there.
 261  *
 262  * Double-channel:      The data size accessed by the memory controller is
 263  *                      interlaced into two dimms, accessed at the same time.
 264  *                      E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
 265  *                      the data flows to the CPU using a 128 bits parallel
 266  *                      access.
 267  *
 268  * Chip-select row:     This is the name of the DRAM signal used to select the
 269  *                      DRAM ranks to be accessed. Common chip-select rows for
 270  *                      single channel are 64 bits, for dual channel 128 bits.
 271  *                      It may not be visible by the memory controller, as some
 272  *                      DIMM types have a memory buffer that can hide direct
 273  *                      access to it from the Memory Controller.
 274  *
 275  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
 276  *                      Motherboards commonly drive two chip-select pins to
 277  *                      a memory stick. A single-ranked stick, will occupy
 278  *                      only one of those rows. The other will be unused.
 279  *
 280  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 281  *                      access different sets of memory devices.  The two
 282  *                      rows cannot be accessed concurrently.
 283  *
 284  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 285  *                      A double-sided stick has two chip-select rows which
 286  *                      access different sets of memory devices. The two
 287  *                      rows cannot be accessed concurrently. "Double-sided"
 288  *                      is irrespective of the memory devices being mounted
 289  *                      on both sides of the memory stick.
 290  *
 291  * Socket set:          All of the memory sticks that are required for
 292  *                      a single memory access or all of the memory sticks
 293  *                      spanned by a chip-select row.  A single socket set
 294  *                      has two chip-select rows and if double-sided sticks
 295  *                      are used these will occupy those chip-select rows.
 296  *
 297  * Bank:                This term is avoided because it is unclear when
 298  *                      needing to distinguish between chip-select rows and
 299  *                      socket sets.
 300  *
 301  * Controller pages:
 302  *
 303  * Physical pages:
 304  *
 305  * Virtual pages:
 306  *
 307  *
 308  * STRUCTURE ORGANIZATION AND CHOICES
 309  *
 310  *
 311  *
 312  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 313  */
 314
 315 /* FIXME: add a per-dimm ce error count */
 316 struct dimm_info {
 317         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 318         unsigned memory_controller;
 319         unsigned csrow;
 320         unsigned csrow_channel;
 321
 322         u32 grain;              /* granularity of reported error in bytes */
 323         enum dev_type dtype;    /* memory device type */
 324         enum mem_type mtype;    /* memory dimm type */
 325         enum edac_type edac_mode;       /* EDAC mode for this dimm */
 326
 327         u32 ce_count;           /* Correctable Errors for this dimm */
 328 };
 329
 330 /**
 331  * struct rank_info - contains the information for one DIMM rank
 332  *
 333  * @chan_idx:   channel number where the rank is (typically, 0 or 1)
 334  * @ce_count:   number of correctable errors for this rank
 335  * @csrow:      A pointer to the chip select row structure (the parent
 336  *              structure). The location of the rank is given by
 337  *              the (csrow->csrow_idx, chan_idx) vector.
 338  * @dimm:       A pointer to the DIMM structure, where the DIMM label
 339  *              information is stored.
 340  *
 341  * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
 342  *        This is a bad assumption, but it makes this patch easier. Later
 343  *        patches in this series will fix this issue.
 344  */
 345 struct rank_info {
 346         int chan_idx;
 347         u32 ce_count;
 348         struct csrow_info *csrow;
 349         struct dimm_info *dimm;
 350 };
 351
 352 struct csrow_info {
 353         unsigned long first_page;       /* first page number in csrow */
 354         unsigned long last_page;        /* last page number in csrow */
 355         u32 nr_pages;                   /* number of pages in csrow */
 356         unsigned long page_mask;        /* used for interleaving -
 357                                          * 0UL for non intlv
 358                                          */
 359         int csrow_idx;                  /* the chip-select row */
 360
 361         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 362         u32 ce_count;           /* Correctable Errors for this csrow */
 363
 364         struct mem_ctl_info *mci;       /* the parent */
 365
 366         struct kobject kobj;    /* sysfs kobject for this csrow */
 367
 368         /* channel information for this csrow */
 369         u32 nr_channels;
 370         struct rank_info *channels;
 371 };
 372
 373 struct mcidev_sysfs_group {
 374         const char *name;                               /* group name */
 375         const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
 376 };
 377
 378 struct mcidev_sysfs_group_kobj {
 379         struct list_head list;          /* list for all instances within a mc */
 380
 381         struct kobject kobj;            /* kobj for the group */
 382
 383         const struct mcidev_sysfs_group *grp;   /* group description table */
 384         struct mem_ctl_info *mci;       /* the parent */
 385 };
 386
 387 /* mcidev_sysfs_attribute structure
 388  *      used for driver sysfs attributes and in mem_ctl_info
 389  *      sysfs top level entries
 390  */
 391 struct mcidev_sysfs_attribute {
 392         /* It should use either attr or grp */
 393         struct attribute attr;
 394         const struct mcidev_sysfs_group *grp;   /* Points to a group of attributes */
 395
 396         /* Ops for show/store values at the attribute - not used on group */
 397         ssize_t (*show)(struct mem_ctl_info *,char *);
 398         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 399 };
 400
 401 /* MEMORY controller information structure
 402  */
 403 struct mem_ctl_info {
 404         struct list_head link;  /* for global list of mem_ctl_info structs */
 405
 406         struct module *owner;   /* Module owner of this control struct */
 407
 408         unsigned long mtype_cap;        /* memory types supported by mc */
 409         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 410         unsigned long edac_cap; /* configuration capabilities - this is
 411                                  * closely related to edac_ctl_cap.  The
 412                                  * difference is that the controller may be
 413                                  * capable of s4ecd4ed which would be listed
 414                                  * in edac_ctl_cap, but if channels aren't
 415                                  * capable of s4ecd4ed then the edac_cap would
 416                                  * not have that capability.
 417                                  */
 418         unsigned long scrub_cap;        /* chipset scrub capabilities */
 419         enum scrub_type scrub_mode;     /* current scrub mode */
 420
 421         /* Translates sdram memory scrub rate given in bytes/sec to the
 422            internal representation and configures whatever else needs
 423            to be configured.
 424          */
 425         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
 426
 427         /* Get the current sdram memory scrub rate from the internal
 428            representation and converts it to the closest matching
 429            bandwidth in bytes/sec.
 430          */
 431         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
 432
 433
 434         /* pointer to edac checking routine */
 435         void (*edac_check) (struct mem_ctl_info * mci);
 436
 437         /*
 438          * Remaps memory pages: controller pages to physical pages.
 439          * For most MC's, this will be NULL.
 440          */
 441         /* FIXME - why not send the phys page to begin with? */
 442         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 443                                            unsigned long page);
 444         int mc_idx;
 445         int nr_csrows;
 446         struct csrow_info *csrows;
 447
 448         /*
 449          * DIMM info. Will eventually remove the entire csrows_info some day
 450          */
 451         unsigned nr_dimms;
 452         struct dimm_info *dimms;
 453
 454         /*
 455          * FIXME - what about controllers on other busses? - IDs must be
 456          * unique.  dev pointer should be sufficiently unique, but
 457          * BUS:SLOT.FUNC numbers may not be unique.
 458          */
 459         struct device *dev;
 460         const char *mod_name;
 461         const char *mod_ver;
 462         const char *ctl_name;
 463         const char *dev_name;
 464         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 465         void *pvt_info;
 466         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 467         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 468         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 469         u32 ce_count;           /* Total Correctable Errors for this MC */
 470         unsigned long start_time;       /* mci load start time (in jiffies) */
 471
 472         struct completion complete;
 473
 474         /* edac sysfs device control */
 475         struct kobject edac_mci_kobj;
 476
 477         /* list for all grp instances within a mc */
 478         struct list_head grp_kobj_list;
 479
 480         /* Additional top controller level attributes, but specified
 481          * by the low level driver.
 482          *
 483          * Set by the low level driver to provide attributes at the
 484          * controller level, same level as 'ue_count' and 'ce_count' above.
 485          * An array of structures, NULL terminated
 486          *
 487          * If attributes are desired, then set to array of attributes
 488          * If no attributes are desired, leave NULL
 489          */
 490         const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 491
 492         /* work struct for this MC */
 493         struct delayed_work work;
 494
 495         /* the internal state of this controller instance */
 496         int op_state;
 497 };
 498
 499 #endif