include/linux/gpio/driver.h

   1 #ifndef __LINUX_GPIO_DRIVER_H
   2 #define __LINUX_GPIO_DRIVER_H
   3
   4 #include <linux/device.h>
   5 #include <linux/types.h>
   6 #include <linux/module.h>
   7 #include <linux/irq.h>
   8 #include <linux/irqchip/chained_irq.h>
   9 #include <linux/irqdomain.h>
  10 #include <linux/lockdep.h>
  11 #include <linux/pinctrl/pinctrl.h>
  12 #include <linux/kconfig.h>
  13
  14 struct gpio_desc;
  15 struct of_phandle_args;
  16 struct device_node;
  17 struct seq_file;
  18 struct gpio_device;
  19
  20 #ifdef CONFIG_GPIOLIB
  21
  22 /**
  23  * struct gpio_chip - abstract a GPIO controller
  24  * @label: for diagnostics
  25  * @gpiodev: the internal state holder, opaque struct
  26  * @parent: optional parent device providing the GPIOs
  27  * @owner: helps prevent removal of modules exporting active GPIOs
  28  * @request: optional hook for chip-specific activation, such as
  29  *      enabling module power and clock; may sleep
  30  * @free: optional hook for chip-specific deactivation, such as
  31  *      disabling module power and clock; may sleep
  32  * @get_direction: returns direction for signal "offset", 0=out, 1=in,
  33  *      (same as GPIOF_DIR_XXX), or negative error
  34  * @direction_input: configures signal "offset" as input, or returns error
  35  * @direction_output: configures signal "offset" as output, or returns error
  36  * @get: returns value for signal "offset", 0=low, 1=high, or negative error
  37  * @set: assigns output value for signal "offset"
  38  * @set_multiple: assigns output values for multiple signals defined by "mask"
  39  * @set_debounce: optional hook for setting debounce time for specified gpio in
  40  *      interrupt triggered gpio chips
  41  * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
  42  *      implementation may not sleep
  43  * @dbg_show: optional routine to show contents in debugfs; default code
  44  *      will be used when this is omitted, but custom code can show extra
  45  *      state (such as pullup/pulldown configuration).
  46  * @base: identifies the first GPIO number handled by this chip;
  47  *      or, if negative during registration, requests dynamic ID allocation.
  48  *      DEPRECATION: providing anything non-negative and nailing the base
  49  *      offset of GPIO chips is deprecated. Please pass -1 as base to
  50  *      let gpiolib select the chip base in all possible cases. We want to
  51  *      get rid of the static GPIO number space in the long run.
  52  * @ngpio: the number of GPIOs handled by this controller; the last GPIO
  53  *      handled is (base + ngpio - 1).
  54  * @names: if set, must be an array of strings to use as alternative
  55  *      names for the GPIOs in this chip. Any entry in the array
  56  *      may be NULL if there is no alias for the GPIO, however the
  57  *      array must be @ngpio entries long.  A name can include a single printk
  58  *      format specifier for an unsigned int.  It is substituted by the actual
  59  *      number of the gpio.
  60  * @can_sleep: flag must be set iff get()/set() methods sleep, as they
  61  *      must while accessing GPIO expander chips over I2C or SPI. This
  62  *      implies that if the chip supports IRQs, these IRQs need to be threaded
  63  *      as the chip access may sleep when e.g. reading out the IRQ status
  64  *      registers.
  65  * @irq_not_threaded: flag must be set if @can_sleep is set but the
  66  *      IRQs don't need to be threaded
  67  * @read_reg: reader function for generic GPIO
  68  * @write_reg: writer function for generic GPIO
  69  * @pin2mask: some generic GPIO controllers work with the big-endian bits
  70  *      notation, e.g. in a 8-bits register, GPIO7 is the least significant
  71  *      bit. This callback assigns the right bit mask.
  72  * @reg_dat: data (in) register for generic GPIO
  73  * @reg_set: output set register (out=high) for generic GPIO
  74  * @reg_clk: output clear register (out=low) for generic GPIO
  75  * @reg_dir: direction setting register for generic GPIO
  76  * @bgpio_bits: number of register bits used for a generic GPIO i.e.
  77  *      <register width> * 8
  78  * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
  79  *      shadowed and real data registers writes together.
  80  * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
  81  *      safely.
  82  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
  83  *      direction safely.
  84  * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
  85  * @irqdomain: Interrupt translation domain; responsible for mapping
  86  *      between GPIO hwirq number and linux irq number
  87  * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
  88  * @irq_handler: the irq handler to use (often a predefined irq core function)
  89  *      for GPIO IRQs, provided by GPIO driver
  90  * @irq_default_type: default IRQ triggering type applied during GPIO driver
  91  *      initialization, provided by GPIO driver
  92  * @irq_parent: GPIO IRQ chip parent/bank linux irq number,
  93  *      provided by GPIO driver
  94  * @lock_key: per GPIO IRQ chip lockdep class
  95  *
  96  * A gpio_chip can help platforms abstract various sources of GPIOs so
  97  * they can all be accessed through a common programing interface.
  98  * Example sources would be SOC controllers, FPGAs, multifunction
  99  * chips, dedicated GPIO expanders, and so on.
 100  *
 101  * Each chip controls a number of signals, identified in method calls
 102  * by "offset" values in the range 0..(@ngpio - 1).  When those signals
 103  * are referenced through calls like gpio_get_value(gpio), the offset
 104  * is calculated by subtracting @base from the gpio number.
 105  */
 106 struct gpio_chip {
 107         const char              *label;
 108         struct gpio_device      *gpiodev;
 109         struct device           *parent;
 110         struct module           *owner;
 111
 112         int                     (*request)(struct gpio_chip *chip,
 113                                                 unsigned offset);
 114         void                    (*free)(struct gpio_chip *chip,
 115                                                 unsigned offset);
 116         int                     (*get_direction)(struct gpio_chip *chip,
 117                                                 unsigned offset);
 118         int                     (*direction_input)(struct gpio_chip *chip,
 119                                                 unsigned offset);
 120         int                     (*direction_output)(struct gpio_chip *chip,
 121                                                 unsigned offset, int value);
 122         int                     (*get)(struct gpio_chip *chip,
 123                                                 unsigned offset);
 124         void                    (*set)(struct gpio_chip *chip,
 125                                                 unsigned offset, int value);
 126         void                    (*set_multiple)(struct gpio_chip *chip,
 127                                                 unsigned long *mask,
 128                                                 unsigned long *bits);
 129         int                     (*set_debounce)(struct gpio_chip *chip,
 130                                                 unsigned offset,
 131                                                 unsigned debounce);
 132
 133         int                     (*to_irq)(struct gpio_chip *chip,
 134                                                 unsigned offset);
 135
 136         void                    (*dbg_show)(struct seq_file *s,
 137                                                 struct gpio_chip *chip);
 138         int                     base;
 139         u16                     ngpio;
 140         const char              *const *names;
 141         bool                    can_sleep;
 142         bool                    irq_not_threaded;
 143
 144 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
 145         unsigned long (*read_reg)(void __iomem *reg);
 146         void (*write_reg)(void __iomem *reg, unsigned long data);
 147         unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
 148         void __iomem *reg_dat;
 149         void __iomem *reg_set;
 150         void __iomem *reg_clr;
 151         void __iomem *reg_dir;
 152         int bgpio_bits;
 153         spinlock_t bgpio_lock;
 154         unsigned long bgpio_data;
 155         unsigned long bgpio_dir;
 156 #endif
 157
 158 #ifdef CONFIG_GPIOLIB_IRQCHIP
 159         /*
 160          * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
 161          * to handle IRQs for most practical cases.
 162          */
 163         struct irq_chip         *irqchip;
 164         struct irq_domain       *irqdomain;
 165         unsigned int            irq_base;
 166         irq_flow_handler_t      irq_handler;
 167         unsigned int            irq_default_type;
 168         int                     irq_parent;
 169         struct lock_class_key   *lock_key;
 170 #endif
 171
 172 #if defined(CONFIG_OF_GPIO)
 173         /*
 174          * If CONFIG_OF is enabled, then all GPIO controllers described in the
 175          * device tree automatically may have an OF translation
 176          */
 177         struct device_node *of_node;
 178         int of_gpio_n_cells;
 179         int (*of_xlate)(struct gpio_chip *gc,
 180                         const struct of_phandle_args *gpiospec, u32 *flags);
 181 #endif
 182 };
 183
 184 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
 185                         unsigned offset);
 186
 187 /* add/remove chips */
 188 extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
 189 static inline int gpiochip_add(struct gpio_chip *chip)
 190 {
 191         return gpiochip_add_data(chip, NULL);
 192 }
 193 extern void gpiochip_remove(struct gpio_chip *chip);
 194 extern struct gpio_chip *gpiochip_find(void *data,
 195                               int (*match)(struct gpio_chip *chip, void *data));
 196
 197 /* lock/unlock as IRQ */
 198 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
 199 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
 200 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
 201
 202 /* Line status inquiry for drivers */
 203 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
 204 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
 205
 206 /* get driver data */
 207 void *gpiochip_get_data(struct gpio_chip *chip);
 208
 209 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
 210
 211 struct bgpio_pdata {
 212         const char *label;
 213         int base;
 214         int ngpio;
 215 };
 216
 217 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
 218
 219 int bgpio_init(struct gpio_chip *gc, struct device *dev,
 220                unsigned long sz, void __iomem *dat, void __iomem *set,
 221                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
 222                unsigned long flags);
 223
 224 #define BGPIOF_BIG_ENDIAN               BIT(0)
 225 #define BGPIOF_UNREADABLE_REG_SET       BIT(1) /* reg_set is unreadable */
 226 #define BGPIOF_UNREADABLE_REG_DIR       BIT(2) /* reg_dir is unreadable */
 227 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER    BIT(3)
 228 #define BGPIOF_READ_OUTPUT_REG_SET      BIT(4) /* reg_set stores output value */
 229 #define BGPIOF_NO_OUTPUT                BIT(5) /* only input */
 230
 231 #endif
 232
 233 #ifdef CONFIG_GPIOLIB_IRQCHIP
 234
 235 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
 236                 struct irq_chip *irqchip,
 237                 int parent_irq,
 238                 irq_flow_handler_t parent_handler);
 239
 240 int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
 241                           struct irq_chip *irqchip,
 242                           unsigned int first_irq,
 243                           irq_flow_handler_t handler,
 244                           unsigned int type,
 245                           struct lock_class_key *lock_key);
 246
 247 #ifdef CONFIG_LOCKDEP
 248 #define gpiochip_irqchip_add(...)                               \
 249 (                                                               \
 250         ({                                                      \
 251                 static struct lock_class_key _key;              \
 252                 _gpiochip_irqchip_add(__VA_ARGS__, &_key);      \
 253         })                                                      \
 254 )
 255 #else
 256 #define gpiochip_irqchip_add(...)                               \
 257         _gpiochip_irqchip_add(__VA_ARGS__, NULL)
 258 #endif
 259
 260 #endif /* CONFIG_GPIOLIB_IRQCHIP */
 261
 262 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
 263 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
 264
 265 #ifdef CONFIG_PINCTRL
 266
 267 /**
 268  * struct gpio_pin_range - pin range controlled by a gpio chip
 269  * @head: list for maintaining set of pin ranges, used internally
 270  * @pctldev: pinctrl device which handles corresponding pins
 271  * @range: actual range of pins controlled by a gpio controller
 272  */
 273
 274 struct gpio_pin_range {
 275         struct list_head node;
 276         struct pinctrl_dev *pctldev;
 277         struct pinctrl_gpio_range range;
 278 };
 279
 280 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
 281                            unsigned int gpio_offset, unsigned int pin_offset,
 282                            unsigned int npins);
 283 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
 284                         struct pinctrl_dev *pctldev,
 285                         unsigned int gpio_offset, const char *pin_group);
 286 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
 287
 288 #else
 289
 290 static inline int
 291 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
 292                        unsigned int gpio_offset, unsigned int pin_offset,
 293                        unsigned int npins)
 294 {
 295         return 0;
 296 }
 297 static inline int
 298 gpiochip_add_pingroup_range(struct gpio_chip *chip,
 299                         struct pinctrl_dev *pctldev,
 300                         unsigned int gpio_offset, const char *pin_group)
 301 {
 302         return 0;
 303 }
 304
 305 static inline void
 306 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
 307 {
 308 }
 309
 310 #endif /* CONFIG_PINCTRL */
 311
 312 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
 313                                             const char *label);
 314 void gpiochip_free_own_desc(struct gpio_desc *desc);
 315
 316 #else /* CONFIG_GPIOLIB */
 317
 318 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
 319 {
 320         /* GPIO can never have been requested */
 321         WARN_ON(1);
 322         return ERR_PTR(-ENODEV);
 323 }
 324
 325 #endif /* CONFIG_GPIOLIB */
 326
 327 #endif