5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
33 enum irqchip_irq_state
;
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_THREAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
75 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
78 IRQ_TYPE_NONE
= 0x00000000,
79 IRQ_TYPE_EDGE_RISING
= 0x00000001,
80 IRQ_TYPE_EDGE_FALLING
= 0x00000002,
81 IRQ_TYPE_EDGE_BOTH
= (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
),
82 IRQ_TYPE_LEVEL_HIGH
= 0x00000004,
83 IRQ_TYPE_LEVEL_LOW
= 0x00000008,
84 IRQ_TYPE_LEVEL_MASK
= (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
),
85 IRQ_TYPE_SENSE_MASK
= 0x0000000f,
86 IRQ_TYPE_DEFAULT
= IRQ_TYPE_SENSE_MASK
,
88 IRQ_TYPE_PROBE
= 0x00000010,
91 IRQ_PER_CPU
= (1 << 9),
92 IRQ_NOPROBE
= (1 << 10),
93 IRQ_NOREQUEST
= (1 << 11),
94 IRQ_NOAUTOEN
= (1 << 12),
95 IRQ_NO_BALANCING
= (1 << 13),
96 IRQ_MOVE_PCNTXT
= (1 << 14),
97 IRQ_NESTED_THREAD
= (1 << 15),
98 IRQ_NOTHREAD
= (1 << 16),
99 IRQ_PER_CPU_DEVID
= (1 << 17),
100 IRQ_IS_POLLED
= (1 << 18),
101 IRQ_DISABLE_UNLAZY
= (1 << 19),
104 #define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
113 * Return value for chip->irq_set_affinity()
115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
118 * support stacked irqchips, which indicates skipping
119 * all descendent irqchips.
123 IRQ_SET_MASK_OK_NOCOPY
,
124 IRQ_SET_MASK_OK_DONE
,
131 * struct irq_common_data - per irq data shared by all irqchips
132 * @state_use_accessors: status information for irq chip functions.
133 * Use accessor functions to deal with it
134 * @node: node index useful for balancing
135 * @handler_data: per-IRQ data for the irq_chip methods
136 * @affinity: IRQ affinity on SMP
137 * @msi_desc: MSI descriptor
139 struct irq_common_data
{
140 unsigned int state_use_accessors
;
145 struct msi_desc
*msi_desc
;
146 cpumask_var_t affinity
;
150 * struct irq_data - per irq chip data passed down to chip functions
151 * @mask: precomputed bitmask for accessing the chip registers
152 * @irq: interrupt number
153 * @hwirq: hardware interrupt number, local to the interrupt domain
154 * @common: point to data shared by all irqchips
155 * @chip: low level interrupt hardware access
156 * @domain: Interrupt translation domain; responsible for mapping
157 * between hwirq number and linux irq number.
158 * @parent_data: pointer to parent struct irq_data to support hierarchy
160 * @chip_data: platform-specific per-chip private data for the chip
161 * methods, to allow shared chip implementations
167 struct irq_common_data
*common
;
168 struct irq_chip
*chip
;
169 struct irq_domain
*domain
;
170 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
171 struct irq_data
*parent_data
;
177 * Bit masks for irq_common_data.state_use_accessors
179 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
180 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
181 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
182 * IRQD_PER_CPU - Interrupt is per cpu
183 * IRQD_AFFINITY_SET - Interrupt affinity was set
184 * IRQD_LEVEL - Interrupt is level triggered
185 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
187 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
189 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
190 * IRQD_IRQ_MASKED - Masked state of the interrupt
191 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
192 * IRQD_WAKEUP_ARMED - Wakeup mode armed
193 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
196 IRQD_TRIGGER_MASK
= 0xf,
197 IRQD_SETAFFINITY_PENDING
= (1 << 8),
198 IRQD_NO_BALANCING
= (1 << 10),
199 IRQD_PER_CPU
= (1 << 11),
200 IRQD_AFFINITY_SET
= (1 << 12),
201 IRQD_LEVEL
= (1 << 13),
202 IRQD_WAKEUP_STATE
= (1 << 14),
203 IRQD_MOVE_PCNTXT
= (1 << 15),
204 IRQD_IRQ_DISABLED
= (1 << 16),
205 IRQD_IRQ_MASKED
= (1 << 17),
206 IRQD_IRQ_INPROGRESS
= (1 << 18),
207 IRQD_WAKEUP_ARMED
= (1 << 19),
208 IRQD_FORWARDED_TO_VCPU
= (1 << 20),
211 #define __irqd_to_state(d) ((d)->common->state_use_accessors)
213 static inline bool irqd_is_setaffinity_pending(struct irq_data
*d
)
215 return __irqd_to_state(d
) & IRQD_SETAFFINITY_PENDING
;
218 static inline bool irqd_is_per_cpu(struct irq_data
*d
)
220 return __irqd_to_state(d
) & IRQD_PER_CPU
;
223 static inline bool irqd_can_balance(struct irq_data
*d
)
225 return !(__irqd_to_state(d
) & (IRQD_PER_CPU
| IRQD_NO_BALANCING
));
228 static inline bool irqd_affinity_was_set(struct irq_data
*d
)
230 return __irqd_to_state(d
) & IRQD_AFFINITY_SET
;
233 static inline void irqd_mark_affinity_was_set(struct irq_data
*d
)
235 __irqd_to_state(d
) |= IRQD_AFFINITY_SET
;
238 static inline u32
irqd_get_trigger_type(struct irq_data
*d
)
240 return __irqd_to_state(d
) & IRQD_TRIGGER_MASK
;
244 * Must only be called inside irq_chip.irq_set_type() functions.
246 static inline void irqd_set_trigger_type(struct irq_data
*d
, u32 type
)
248 __irqd_to_state(d
) &= ~IRQD_TRIGGER_MASK
;
249 __irqd_to_state(d
) |= type
& IRQD_TRIGGER_MASK
;
252 static inline bool irqd_is_level_type(struct irq_data
*d
)
254 return __irqd_to_state(d
) & IRQD_LEVEL
;
257 static inline bool irqd_is_wakeup_set(struct irq_data
*d
)
259 return __irqd_to_state(d
) & IRQD_WAKEUP_STATE
;
262 static inline bool irqd_can_move_in_process_context(struct irq_data
*d
)
264 return __irqd_to_state(d
) & IRQD_MOVE_PCNTXT
;
267 static inline bool irqd_irq_disabled(struct irq_data
*d
)
269 return __irqd_to_state(d
) & IRQD_IRQ_DISABLED
;
272 static inline bool irqd_irq_masked(struct irq_data
*d
)
274 return __irqd_to_state(d
) & IRQD_IRQ_MASKED
;
277 static inline bool irqd_irq_inprogress(struct irq_data
*d
)
279 return __irqd_to_state(d
) & IRQD_IRQ_INPROGRESS
;
282 static inline bool irqd_is_wakeup_armed(struct irq_data
*d
)
284 return __irqd_to_state(d
) & IRQD_WAKEUP_ARMED
;
287 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data
*d
)
289 return __irqd_to_state(d
) & IRQD_FORWARDED_TO_VCPU
;
292 static inline void irqd_set_forwarded_to_vcpu(struct irq_data
*d
)
294 __irqd_to_state(d
) |= IRQD_FORWARDED_TO_VCPU
;
297 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data
*d
)
299 __irqd_to_state(d
) &= ~IRQD_FORWARDED_TO_VCPU
;
302 static inline irq_hw_number_t
irqd_to_hwirq(struct irq_data
*d
)
308 * struct irq_chip - hardware interrupt chip descriptor
310 * @name: name for /proc/interrupts
311 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
312 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
313 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
314 * @irq_disable: disable the interrupt
315 * @irq_ack: start of a new interrupt
316 * @irq_mask: mask an interrupt source
317 * @irq_mask_ack: ack and mask an interrupt source
318 * @irq_unmask: unmask an interrupt source
319 * @irq_eoi: end of interrupt
320 * @irq_set_affinity: set the CPU affinity on SMP machines
321 * @irq_retrigger: resend an IRQ to the CPU
322 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
323 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
324 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
325 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
326 * @irq_cpu_online: configure an interrupt source for a secondary CPU
327 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
328 * @irq_suspend: function called from core code on suspend once per
329 * chip, when one or more interrupts are installed
330 * @irq_resume: function called from core code on resume once per chip,
331 * when one ore more interrupts are installed
332 * @irq_pm_shutdown: function called from core code on shutdown once per chip
333 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
334 * @irq_print_chip: optional to print special chip info in show_interrupts
335 * @irq_request_resources: optional to request resources before calling
336 * any other callback related to this irq
337 * @irq_release_resources: optional to release resources acquired with
338 * irq_request_resources
339 * @irq_compose_msi_msg: optional to compose message content for MSI
340 * @irq_write_msi_msg: optional to write message content for MSI
341 * @irq_get_irqchip_state: return the internal state of an interrupt
342 * @irq_set_irqchip_state: set the internal state of a interrupt
343 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
344 * @flags: chip specific flags
348 unsigned int (*irq_startup
)(struct irq_data
*data
);
349 void (*irq_shutdown
)(struct irq_data
*data
);
350 void (*irq_enable
)(struct irq_data
*data
);
351 void (*irq_disable
)(struct irq_data
*data
);
353 void (*irq_ack
)(struct irq_data
*data
);
354 void (*irq_mask
)(struct irq_data
*data
);
355 void (*irq_mask_ack
)(struct irq_data
*data
);
356 void (*irq_unmask
)(struct irq_data
*data
);
357 void (*irq_eoi
)(struct irq_data
*data
);
359 int (*irq_set_affinity
)(struct irq_data
*data
, const struct cpumask
*dest
, bool force
);
360 int (*irq_retrigger
)(struct irq_data
*data
);
361 int (*irq_set_type
)(struct irq_data
*data
, unsigned int flow_type
);
362 int (*irq_set_wake
)(struct irq_data
*data
, unsigned int on
);
364 void (*irq_bus_lock
)(struct irq_data
*data
);
365 void (*irq_bus_sync_unlock
)(struct irq_data
*data
);
367 void (*irq_cpu_online
)(struct irq_data
*data
);
368 void (*irq_cpu_offline
)(struct irq_data
*data
);
370 void (*irq_suspend
)(struct irq_data
*data
);
371 void (*irq_resume
)(struct irq_data
*data
);
372 void (*irq_pm_shutdown
)(struct irq_data
*data
);
374 void (*irq_calc_mask
)(struct irq_data
*data
);
376 void (*irq_print_chip
)(struct irq_data
*data
, struct seq_file
*p
);
377 int (*irq_request_resources
)(struct irq_data
*data
);
378 void (*irq_release_resources
)(struct irq_data
*data
);
380 void (*irq_compose_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
381 void (*irq_write_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
383 int (*irq_get_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool *state
);
384 int (*irq_set_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool state
);
386 int (*irq_set_vcpu_affinity
)(struct irq_data
*data
, void *vcpu_info
);
392 * irq_chip specific flags
394 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
395 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
396 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
397 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
399 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
400 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
401 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
404 IRQCHIP_SET_TYPE_MASKED
= (1 << 0),
405 IRQCHIP_EOI_IF_HANDLED
= (1 << 1),
406 IRQCHIP_MASK_ON_SUSPEND
= (1 << 2),
407 IRQCHIP_ONOFFLINE_ENABLED
= (1 << 3),
408 IRQCHIP_SKIP_SET_WAKE
= (1 << 4),
409 IRQCHIP_ONESHOT_SAFE
= (1 << 5),
410 IRQCHIP_EOI_THREADED
= (1 << 6),
413 #include <linux/irqdesc.h>
416 * Pick up the arch-dependent methods:
418 #include <asm/hw_irq.h>
420 #ifndef NR_IRQS_LEGACY
421 # define NR_IRQS_LEGACY 0
424 #ifndef ARCH_IRQ_INIT_FLAGS
425 # define ARCH_IRQ_INIT_FLAGS 0
428 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
431 extern int setup_irq(unsigned int irq
, struct irqaction
*new);
432 extern void remove_irq(unsigned int irq
, struct irqaction
*act
);
433 extern int setup_percpu_irq(unsigned int irq
, struct irqaction
*new);
434 extern void remove_percpu_irq(unsigned int irq
, struct irqaction
*act
);
436 extern void irq_cpu_online(void);
437 extern void irq_cpu_offline(void);
438 extern int irq_set_affinity_locked(struct irq_data
*data
,
439 const struct cpumask
*cpumask
, bool force
);
440 extern int irq_set_vcpu_affinity(unsigned int irq
, void *vcpu_info
);
442 extern void irq_migrate_all_off_this_cpu(void);
444 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
445 void irq_move_irq(struct irq_data
*data
);
446 void irq_move_masked_irq(struct irq_data
*data
);
448 static inline void irq_move_irq(struct irq_data
*data
) { }
449 static inline void irq_move_masked_irq(struct irq_data
*data
) { }
452 extern int no_irq_affinity
;
454 #ifdef CONFIG_HARDIRQS_SW_RESEND
455 int irq_set_parent(int irq
, int parent_irq
);
457 static inline int irq_set_parent(int irq
, int parent_irq
)
464 * Built-in IRQ handlers for various IRQ types,
465 * callable via desc->handle_irq()
467 extern void handle_level_irq(struct irq_desc
*desc
);
468 extern void handle_fasteoi_irq(struct irq_desc
*desc
);
469 extern void handle_edge_irq(struct irq_desc
*desc
);
470 extern void handle_edge_eoi_irq(struct irq_desc
*desc
);
471 extern void handle_simple_irq(struct irq_desc
*desc
);
472 extern void handle_percpu_irq(struct irq_desc
*desc
);
473 extern void handle_percpu_devid_irq(struct irq_desc
*desc
);
474 extern void handle_bad_irq(struct irq_desc
*desc
);
475 extern void handle_nested_irq(unsigned int irq
);
477 extern int irq_chip_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
);
478 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
479 extern void irq_chip_enable_parent(struct irq_data
*data
);
480 extern void irq_chip_disable_parent(struct irq_data
*data
);
481 extern void irq_chip_ack_parent(struct irq_data
*data
);
482 extern int irq_chip_retrigger_hierarchy(struct irq_data
*data
);
483 extern void irq_chip_mask_parent(struct irq_data
*data
);
484 extern void irq_chip_unmask_parent(struct irq_data
*data
);
485 extern void irq_chip_eoi_parent(struct irq_data
*data
);
486 extern int irq_chip_set_affinity_parent(struct irq_data
*data
,
487 const struct cpumask
*dest
,
489 extern int irq_chip_set_wake_parent(struct irq_data
*data
, unsigned int on
);
490 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data
*data
,
492 extern int irq_chip_set_type_parent(struct irq_data
*data
, unsigned int type
);
495 /* Handling of unhandled and spurious interrupts: */
496 extern void note_interrupt(struct irq_desc
*desc
, irqreturn_t action_ret
);
499 /* Enable/disable irq debugging output: */
500 extern int noirqdebug_setup(char *str
);
502 /* Checks whether the interrupt can be requested by request_irq(): */
503 extern int can_request_irq(unsigned int irq
, unsigned long irqflags
);
505 /* Dummy irq-chip implementations: */
506 extern struct irq_chip no_irq_chip
;
507 extern struct irq_chip dummy_irq_chip
;
510 irq_set_chip_and_handler_name(unsigned int irq
, struct irq_chip
*chip
,
511 irq_flow_handler_t handle
, const char *name
);
513 static inline void irq_set_chip_and_handler(unsigned int irq
, struct irq_chip
*chip
,
514 irq_flow_handler_t handle
)
516 irq_set_chip_and_handler_name(irq
, chip
, handle
, NULL
);
519 extern int irq_set_percpu_devid(unsigned int irq
);
522 __irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
, int is_chained
,
526 irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
)
528 __irq_set_handler(irq
, handle
, 0, NULL
);
532 * Set a highlevel chained flow handler for a given IRQ.
533 * (a chained handler is automatically enabled and set to
534 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
537 irq_set_chained_handler(unsigned int irq
, irq_flow_handler_t handle
)
539 __irq_set_handler(irq
, handle
, 1, NULL
);
543 * Set a highlevel chained flow handler and its data for a given IRQ.
544 * (a chained handler is automatically enabled and set to
545 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
548 irq_set_chained_handler_and_data(unsigned int irq
, irq_flow_handler_t handle
,
551 void irq_modify_status(unsigned int irq
, unsigned long clr
, unsigned long set
);
553 static inline void irq_set_status_flags(unsigned int irq
, unsigned long set
)
555 irq_modify_status(irq
, 0, set
);
558 static inline void irq_clear_status_flags(unsigned int irq
, unsigned long clr
)
560 irq_modify_status(irq
, clr
, 0);
563 static inline void irq_set_noprobe(unsigned int irq
)
565 irq_modify_status(irq
, 0, IRQ_NOPROBE
);
568 static inline void irq_set_probe(unsigned int irq
)
570 irq_modify_status(irq
, IRQ_NOPROBE
, 0);
573 static inline void irq_set_nothread(unsigned int irq
)
575 irq_modify_status(irq
, 0, IRQ_NOTHREAD
);
578 static inline void irq_set_thread(unsigned int irq
)
580 irq_modify_status(irq
, IRQ_NOTHREAD
, 0);
583 static inline void irq_set_nested_thread(unsigned int irq
, bool nest
)
586 irq_set_status_flags(irq
, IRQ_NESTED_THREAD
);
588 irq_clear_status_flags(irq
, IRQ_NESTED_THREAD
);
591 static inline void irq_set_percpu_devid_flags(unsigned int irq
)
593 irq_set_status_flags(irq
,
594 IRQ_NOAUTOEN
| IRQ_PER_CPU
| IRQ_NOTHREAD
|
595 IRQ_NOPROBE
| IRQ_PER_CPU_DEVID
);
598 /* Set/get chip/data for an IRQ: */
599 extern int irq_set_chip(unsigned int irq
, struct irq_chip
*chip
);
600 extern int irq_set_handler_data(unsigned int irq
, void *data
);
601 extern int irq_set_chip_data(unsigned int irq
, void *data
);
602 extern int irq_set_irq_type(unsigned int irq
, unsigned int type
);
603 extern int irq_set_msi_desc(unsigned int irq
, struct msi_desc
*entry
);
604 extern int irq_set_msi_desc_off(unsigned int irq_base
, unsigned int irq_offset
,
605 struct msi_desc
*entry
);
606 extern struct irq_data
*irq_get_irq_data(unsigned int irq
);
608 static inline struct irq_chip
*irq_get_chip(unsigned int irq
)
610 struct irq_data
*d
= irq_get_irq_data(irq
);
611 return d
? d
->chip
: NULL
;
614 static inline struct irq_chip
*irq_data_get_irq_chip(struct irq_data
*d
)
619 static inline void *irq_get_chip_data(unsigned int irq
)
621 struct irq_data
*d
= irq_get_irq_data(irq
);
622 return d
? d
->chip_data
: NULL
;
625 static inline void *irq_data_get_irq_chip_data(struct irq_data
*d
)
630 static inline void *irq_get_handler_data(unsigned int irq
)
632 struct irq_data
*d
= irq_get_irq_data(irq
);
633 return d
? d
->common
->handler_data
: NULL
;
636 static inline void *irq_data_get_irq_handler_data(struct irq_data
*d
)
638 return d
->common
->handler_data
;
641 static inline struct msi_desc
*irq_get_msi_desc(unsigned int irq
)
643 struct irq_data
*d
= irq_get_irq_data(irq
);
644 return d
? d
->common
->msi_desc
: NULL
;
647 static inline struct msi_desc
*irq_data_get_msi_desc(struct irq_data
*d
)
649 return d
->common
->msi_desc
;
652 static inline u32
irq_get_trigger_type(unsigned int irq
)
654 struct irq_data
*d
= irq_get_irq_data(irq
);
655 return d
? irqd_get_trigger_type(d
) : 0;
658 static inline int irq_common_data_get_node(struct irq_common_data
*d
)
667 static inline int irq_data_get_node(struct irq_data
*d
)
669 return irq_common_data_get_node(d
->common
);
672 static inline struct cpumask
*irq_get_affinity_mask(int irq
)
674 struct irq_data
*d
= irq_get_irq_data(irq
);
676 return d
? d
->common
->affinity
: NULL
;
679 static inline struct cpumask
*irq_data_get_affinity_mask(struct irq_data
*d
)
681 return d
->common
->affinity
;
684 unsigned int arch_dynirq_lower_bound(unsigned int from
);
686 int __irq_alloc_descs(int irq
, unsigned int from
, unsigned int cnt
, int node
,
687 struct module
*owner
);
689 /* use macros to avoid needing export.h for THIS_MODULE */
690 #define irq_alloc_descs(irq, from, cnt, node) \
691 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
693 #define irq_alloc_desc(node) \
694 irq_alloc_descs(-1, 0, 1, node)
696 #define irq_alloc_desc_at(at, node) \
697 irq_alloc_descs(at, at, 1, node)
699 #define irq_alloc_desc_from(from, node) \
700 irq_alloc_descs(-1, from, 1, node)
702 #define irq_alloc_descs_from(from, cnt, node) \
703 irq_alloc_descs(-1, from, cnt, node)
705 void irq_free_descs(unsigned int irq
, unsigned int cnt
);
706 static inline void irq_free_desc(unsigned int irq
)
708 irq_free_descs(irq
, 1);
711 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
712 unsigned int irq_alloc_hwirqs(int cnt
, int node
);
713 static inline unsigned int irq_alloc_hwirq(int node
)
715 return irq_alloc_hwirqs(1, node
);
717 void irq_free_hwirqs(unsigned int from
, int cnt
);
718 static inline void irq_free_hwirq(unsigned int irq
)
720 return irq_free_hwirqs(irq
, 1);
722 int arch_setup_hwirq(unsigned int irq
, int node
);
723 void arch_teardown_hwirq(unsigned int irq
);
726 #ifdef CONFIG_GENERIC_IRQ_LEGACY
727 void irq_init_desc(unsigned int irq
);
731 * struct irq_chip_regs - register offsets for struct irq_gci
732 * @enable: Enable register offset to reg_base
733 * @disable: Disable register offset to reg_base
734 * @mask: Mask register offset to reg_base
735 * @ack: Ack register offset to reg_base
736 * @eoi: Eoi register offset to reg_base
737 * @type: Type configuration register offset to reg_base
738 * @polarity: Polarity configuration register offset to reg_base
740 struct irq_chip_regs
{
741 unsigned long enable
;
742 unsigned long disable
;
747 unsigned long polarity
;
751 * struct irq_chip_type - Generic interrupt chip instance for a flow type
752 * @chip: The real interrupt chip which provides the callbacks
753 * @regs: Register offsets for this chip
754 * @handler: Flow handler associated with this chip
755 * @type: Chip can handle these flow types
756 * @mask_cache_priv: Cached mask register private to the chip type
757 * @mask_cache: Pointer to cached mask register
759 * A irq_generic_chip can have several instances of irq_chip_type when
760 * it requires different functions and register offsets for different
763 struct irq_chip_type
{
764 struct irq_chip chip
;
765 struct irq_chip_regs regs
;
766 irq_flow_handler_t handler
;
773 * struct irq_chip_generic - Generic irq chip data structure
774 * @lock: Lock to protect register and cache data access
775 * @reg_base: Register base address (virtual)
776 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
777 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
778 * @suspend: Function called from core code on suspend once per
779 * chip; can be useful instead of irq_chip::suspend to
780 * handle chip details even when no interrupts are in use
781 * @resume: Function called from core code on resume once per chip;
782 * can be useful instead of irq_chip::suspend to handle
783 * chip details even when no interrupts are in use
784 * @irq_base: Interrupt base nr for this chip
785 * @irq_cnt: Number of interrupts handled by this chip
786 * @mask_cache: Cached mask register shared between all chip types
787 * @type_cache: Cached type register
788 * @polarity_cache: Cached polarity register
789 * @wake_enabled: Interrupt can wakeup from suspend
790 * @wake_active: Interrupt is marked as an wakeup from suspend source
791 * @num_ct: Number of available irq_chip_type instances (usually 1)
792 * @private: Private data for non generic chip callbacks
793 * @installed: bitfield to denote installed interrupts
794 * @unused: bitfield to denote unused interrupts
795 * @domain: irq domain pointer
796 * @list: List head for keeping track of instances
797 * @chip_types: Array of interrupt irq_chip_types
799 * Note, that irq_chip_generic can have multiple irq_chip_type
800 * implementations which can be associated to a particular irq line of
801 * an irq_chip_generic instance. That allows to share and protect
802 * state in an irq_chip_generic instance when we need to implement
803 * different flow mechanisms (level/edge) for it.
805 struct irq_chip_generic
{
807 void __iomem
*reg_base
;
808 u32 (*reg_readl
)(void __iomem
*addr
);
809 void (*reg_writel
)(u32 val
, void __iomem
*addr
);
810 void (*suspend
)(struct irq_chip_generic
*gc
);
811 void (*resume
)(struct irq_chip_generic
*gc
);
812 unsigned int irq_base
;
813 unsigned int irq_cnt
;
821 unsigned long installed
;
822 unsigned long unused
;
823 struct irq_domain
*domain
;
824 struct list_head list
;
825 struct irq_chip_type chip_types
[0];
829 * enum irq_gc_flags - Initialization flags for generic irq chips
830 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
831 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
832 * irq chips which need to call irq_set_wake() on
833 * the parent irq. Usually GPIO implementations
834 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
835 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
836 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
839 IRQ_GC_INIT_MASK_CACHE
= 1 << 0,
840 IRQ_GC_INIT_NESTED_LOCK
= 1 << 1,
841 IRQ_GC_MASK_CACHE_PER_TYPE
= 1 << 2,
842 IRQ_GC_NO_MASK
= 1 << 3,
843 IRQ_GC_BE_IO
= 1 << 4,
847 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
848 * @irqs_per_chip: Number of interrupts per chip
849 * @num_chips: Number of chips
850 * @irq_flags_to_set: IRQ* flags to set on irq setup
851 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
852 * @gc_flags: Generic chip specific setup flags
853 * @gc: Array of pointers to generic interrupt chips
855 struct irq_domain_chip_generic
{
856 unsigned int irqs_per_chip
;
857 unsigned int num_chips
;
858 unsigned int irq_flags_to_clear
;
859 unsigned int irq_flags_to_set
;
860 enum irq_gc_flags gc_flags
;
861 struct irq_chip_generic
*gc
[0];
864 /* Generic chip callback functions */
865 void irq_gc_noop(struct irq_data
*d
);
866 void irq_gc_mask_disable_reg(struct irq_data
*d
);
867 void irq_gc_mask_set_bit(struct irq_data
*d
);
868 void irq_gc_mask_clr_bit(struct irq_data
*d
);
869 void irq_gc_unmask_enable_reg(struct irq_data
*d
);
870 void irq_gc_ack_set_bit(struct irq_data
*d
);
871 void irq_gc_ack_clr_bit(struct irq_data
*d
);
872 void irq_gc_mask_disable_reg_and_ack(struct irq_data
*d
);
873 void irq_gc_eoi(struct irq_data
*d
);
874 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
);
876 /* Setup functions for irq_chip_generic */
877 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
878 irq_hw_number_t hw_irq
);
879 struct irq_chip_generic
*
880 irq_alloc_generic_chip(const char *name
, int nr_ct
, unsigned int irq_base
,
881 void __iomem
*reg_base
, irq_flow_handler_t handler
);
882 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
883 enum irq_gc_flags flags
, unsigned int clr
,
885 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
);
886 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
887 unsigned int clr
, unsigned int set
);
889 struct irq_chip_generic
*irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
);
890 int irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
891 int num_ct
, const char *name
,
892 irq_flow_handler_t handler
,
893 unsigned int clr
, unsigned int set
,
894 enum irq_gc_flags flags
);
897 static inline struct irq_chip_type
*irq_data_get_chip_type(struct irq_data
*d
)
899 return container_of(d
->chip
, struct irq_chip_type
, chip
);
902 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
905 static inline void irq_gc_lock(struct irq_chip_generic
*gc
)
907 raw_spin_lock(&gc
->lock
);
910 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
)
912 raw_spin_unlock(&gc
->lock
);
915 static inline void irq_gc_lock(struct irq_chip_generic
*gc
) { }
916 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
) { }
919 static inline void irq_reg_writel(struct irq_chip_generic
*gc
,
920 u32 val
, int reg_offset
)
923 gc
->reg_writel(val
, gc
->reg_base
+ reg_offset
);
925 writel(val
, gc
->reg_base
+ reg_offset
);
928 static inline u32
irq_reg_readl(struct irq_chip_generic
*gc
,
932 return gc
->reg_readl(gc
->reg_base
+ reg_offset
);
934 return readl(gc
->reg_base
+ reg_offset
);
937 #endif /* _LINUX_IRQ_H */