5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
33 enum irqchip_irq_state
;
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_THREAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
75 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
78 IRQ_TYPE_NONE
= 0x00000000,
79 IRQ_TYPE_EDGE_RISING
= 0x00000001,
80 IRQ_TYPE_EDGE_FALLING
= 0x00000002,
81 IRQ_TYPE_EDGE_BOTH
= (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
),
82 IRQ_TYPE_LEVEL_HIGH
= 0x00000004,
83 IRQ_TYPE_LEVEL_LOW
= 0x00000008,
84 IRQ_TYPE_LEVEL_MASK
= (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
),
85 IRQ_TYPE_SENSE_MASK
= 0x0000000f,
86 IRQ_TYPE_DEFAULT
= IRQ_TYPE_SENSE_MASK
,
88 IRQ_TYPE_PROBE
= 0x00000010,
91 IRQ_PER_CPU
= (1 << 9),
92 IRQ_NOPROBE
= (1 << 10),
93 IRQ_NOREQUEST
= (1 << 11),
94 IRQ_NOAUTOEN
= (1 << 12),
95 IRQ_NO_BALANCING
= (1 << 13),
96 IRQ_MOVE_PCNTXT
= (1 << 14),
97 IRQ_NESTED_THREAD
= (1 << 15),
98 IRQ_NOTHREAD
= (1 << 16),
99 IRQ_PER_CPU_DEVID
= (1 << 17),
100 IRQ_IS_POLLED
= (1 << 18),
101 IRQ_DISABLE_UNLAZY
= (1 << 19),
104 #define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
113 * Return value for chip->irq_set_affinity()
115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
118 * support stacked irqchips, which indicates skipping
119 * all descendent irqchips.
123 IRQ_SET_MASK_OK_NOCOPY
,
124 IRQ_SET_MASK_OK_DONE
,
131 * struct irq_common_data - per irq data shared by all irqchips
132 * @state_use_accessors: status information for irq chip functions.
133 * Use accessor functions to deal with it
134 * @node: node index useful for balancing
135 * @handler_data: per-IRQ data for the irq_chip methods
136 * @affinity: IRQ affinity on SMP. If this is an IPI
137 * related irq, then this is the mask of the
138 * CPUs to which an IPI can be sent.
139 * @msi_desc: MSI descriptor
140 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
142 struct irq_common_data
{
143 unsigned int __private state_use_accessors
;
148 struct msi_desc
*msi_desc
;
149 cpumask_var_t affinity
;
150 #ifdef CONFIG_GENERIC_IRQ_IPI
151 unsigned int ipi_offset
;
156 * struct irq_data - per irq chip data passed down to chip functions
157 * @mask: precomputed bitmask for accessing the chip registers
158 * @irq: interrupt number
159 * @hwirq: hardware interrupt number, local to the interrupt domain
160 * @common: point to data shared by all irqchips
161 * @chip: low level interrupt hardware access
162 * @domain: Interrupt translation domain; responsible for mapping
163 * between hwirq number and linux irq number.
164 * @parent_data: pointer to parent struct irq_data to support hierarchy
166 * @chip_data: platform-specific per-chip private data for the chip
167 * methods, to allow shared chip implementations
173 struct irq_common_data
*common
;
174 struct irq_chip
*chip
;
175 struct irq_domain
*domain
;
176 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
177 struct irq_data
*parent_data
;
183 * Bit masks for irq_common_data.state_use_accessors
185 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
186 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
187 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
188 * IRQD_PER_CPU - Interrupt is per cpu
189 * IRQD_AFFINITY_SET - Interrupt affinity was set
190 * IRQD_LEVEL - Interrupt is level triggered
191 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
193 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
195 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
196 * IRQD_IRQ_MASKED - Masked state of the interrupt
197 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
198 * IRQD_WAKEUP_ARMED - Wakeup mode armed
199 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
202 IRQD_TRIGGER_MASK
= 0xf,
203 IRQD_SETAFFINITY_PENDING
= (1 << 8),
204 IRQD_NO_BALANCING
= (1 << 10),
205 IRQD_PER_CPU
= (1 << 11),
206 IRQD_AFFINITY_SET
= (1 << 12),
207 IRQD_LEVEL
= (1 << 13),
208 IRQD_WAKEUP_STATE
= (1 << 14),
209 IRQD_MOVE_PCNTXT
= (1 << 15),
210 IRQD_IRQ_DISABLED
= (1 << 16),
211 IRQD_IRQ_MASKED
= (1 << 17),
212 IRQD_IRQ_INPROGRESS
= (1 << 18),
213 IRQD_WAKEUP_ARMED
= (1 << 19),
214 IRQD_FORWARDED_TO_VCPU
= (1 << 20),
217 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
219 static inline bool irqd_is_setaffinity_pending(struct irq_data
*d
)
221 return __irqd_to_state(d
) & IRQD_SETAFFINITY_PENDING
;
224 static inline bool irqd_is_per_cpu(struct irq_data
*d
)
226 return __irqd_to_state(d
) & IRQD_PER_CPU
;
229 static inline bool irqd_can_balance(struct irq_data
*d
)
231 return !(__irqd_to_state(d
) & (IRQD_PER_CPU
| IRQD_NO_BALANCING
));
234 static inline bool irqd_affinity_was_set(struct irq_data
*d
)
236 return __irqd_to_state(d
) & IRQD_AFFINITY_SET
;
239 static inline void irqd_mark_affinity_was_set(struct irq_data
*d
)
241 __irqd_to_state(d
) |= IRQD_AFFINITY_SET
;
244 static inline u32
irqd_get_trigger_type(struct irq_data
*d
)
246 return __irqd_to_state(d
) & IRQD_TRIGGER_MASK
;
250 * Must only be called inside irq_chip.irq_set_type() functions.
252 static inline void irqd_set_trigger_type(struct irq_data
*d
, u32 type
)
254 __irqd_to_state(d
) &= ~IRQD_TRIGGER_MASK
;
255 __irqd_to_state(d
) |= type
& IRQD_TRIGGER_MASK
;
258 static inline bool irqd_is_level_type(struct irq_data
*d
)
260 return __irqd_to_state(d
) & IRQD_LEVEL
;
263 static inline bool irqd_is_wakeup_set(struct irq_data
*d
)
265 return __irqd_to_state(d
) & IRQD_WAKEUP_STATE
;
268 static inline bool irqd_can_move_in_process_context(struct irq_data
*d
)
270 return __irqd_to_state(d
) & IRQD_MOVE_PCNTXT
;
273 static inline bool irqd_irq_disabled(struct irq_data
*d
)
275 return __irqd_to_state(d
) & IRQD_IRQ_DISABLED
;
278 static inline bool irqd_irq_masked(struct irq_data
*d
)
280 return __irqd_to_state(d
) & IRQD_IRQ_MASKED
;
283 static inline bool irqd_irq_inprogress(struct irq_data
*d
)
285 return __irqd_to_state(d
) & IRQD_IRQ_INPROGRESS
;
288 static inline bool irqd_is_wakeup_armed(struct irq_data
*d
)
290 return __irqd_to_state(d
) & IRQD_WAKEUP_ARMED
;
293 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data
*d
)
295 return __irqd_to_state(d
) & IRQD_FORWARDED_TO_VCPU
;
298 static inline void irqd_set_forwarded_to_vcpu(struct irq_data
*d
)
300 __irqd_to_state(d
) |= IRQD_FORWARDED_TO_VCPU
;
303 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data
*d
)
305 __irqd_to_state(d
) &= ~IRQD_FORWARDED_TO_VCPU
;
308 #undef __irqd_to_state
310 static inline irq_hw_number_t
irqd_to_hwirq(struct irq_data
*d
)
316 * struct irq_chip - hardware interrupt chip descriptor
318 * @name: name for /proc/interrupts
319 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
320 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
321 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
322 * @irq_disable: disable the interrupt
323 * @irq_ack: start of a new interrupt
324 * @irq_mask: mask an interrupt source
325 * @irq_mask_ack: ack and mask an interrupt source
326 * @irq_unmask: unmask an interrupt source
327 * @irq_eoi: end of interrupt
328 * @irq_set_affinity: set the CPU affinity on SMP machines
329 * @irq_retrigger: resend an IRQ to the CPU
330 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
331 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
332 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
333 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
334 * @irq_cpu_online: configure an interrupt source for a secondary CPU
335 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
336 * @irq_suspend: function called from core code on suspend once per
337 * chip, when one or more interrupts are installed
338 * @irq_resume: function called from core code on resume once per chip,
339 * when one ore more interrupts are installed
340 * @irq_pm_shutdown: function called from core code on shutdown once per chip
341 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
342 * @irq_print_chip: optional to print special chip info in show_interrupts
343 * @irq_request_resources: optional to request resources before calling
344 * any other callback related to this irq
345 * @irq_release_resources: optional to release resources acquired with
346 * irq_request_resources
347 * @irq_compose_msi_msg: optional to compose message content for MSI
348 * @irq_write_msi_msg: optional to write message content for MSI
349 * @irq_get_irqchip_state: return the internal state of an interrupt
350 * @irq_set_irqchip_state: set the internal state of a interrupt
351 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
352 * @ipi_send_single: send a single IPI to destination cpus
353 * @ipi_send_mask: send an IPI to destination cpus in cpumask
354 * @flags: chip specific flags
358 unsigned int (*irq_startup
)(struct irq_data
*data
);
359 void (*irq_shutdown
)(struct irq_data
*data
);
360 void (*irq_enable
)(struct irq_data
*data
);
361 void (*irq_disable
)(struct irq_data
*data
);
363 void (*irq_ack
)(struct irq_data
*data
);
364 void (*irq_mask
)(struct irq_data
*data
);
365 void (*irq_mask_ack
)(struct irq_data
*data
);
366 void (*irq_unmask
)(struct irq_data
*data
);
367 void (*irq_eoi
)(struct irq_data
*data
);
369 int (*irq_set_affinity
)(struct irq_data
*data
, const struct cpumask
*dest
, bool force
);
370 int (*irq_retrigger
)(struct irq_data
*data
);
371 int (*irq_set_type
)(struct irq_data
*data
, unsigned int flow_type
);
372 int (*irq_set_wake
)(struct irq_data
*data
, unsigned int on
);
374 void (*irq_bus_lock
)(struct irq_data
*data
);
375 void (*irq_bus_sync_unlock
)(struct irq_data
*data
);
377 void (*irq_cpu_online
)(struct irq_data
*data
);
378 void (*irq_cpu_offline
)(struct irq_data
*data
);
380 void (*irq_suspend
)(struct irq_data
*data
);
381 void (*irq_resume
)(struct irq_data
*data
);
382 void (*irq_pm_shutdown
)(struct irq_data
*data
);
384 void (*irq_calc_mask
)(struct irq_data
*data
);
386 void (*irq_print_chip
)(struct irq_data
*data
, struct seq_file
*p
);
387 int (*irq_request_resources
)(struct irq_data
*data
);
388 void (*irq_release_resources
)(struct irq_data
*data
);
390 void (*irq_compose_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
391 void (*irq_write_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
393 int (*irq_get_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool *state
);
394 int (*irq_set_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool state
);
396 int (*irq_set_vcpu_affinity
)(struct irq_data
*data
, void *vcpu_info
);
398 void (*ipi_send_single
)(struct irq_data
*data
, unsigned int cpu
);
399 void (*ipi_send_mask
)(struct irq_data
*data
, const struct cpumask
*dest
);
405 * irq_chip specific flags
407 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
408 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
409 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
410 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
412 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
413 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
414 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
417 IRQCHIP_SET_TYPE_MASKED
= (1 << 0),
418 IRQCHIP_EOI_IF_HANDLED
= (1 << 1),
419 IRQCHIP_MASK_ON_SUSPEND
= (1 << 2),
420 IRQCHIP_ONOFFLINE_ENABLED
= (1 << 3),
421 IRQCHIP_SKIP_SET_WAKE
= (1 << 4),
422 IRQCHIP_ONESHOT_SAFE
= (1 << 5),
423 IRQCHIP_EOI_THREADED
= (1 << 6),
426 #include <linux/irqdesc.h>
429 * Pick up the arch-dependent methods:
431 #include <asm/hw_irq.h>
433 #ifndef NR_IRQS_LEGACY
434 # define NR_IRQS_LEGACY 0
437 #ifndef ARCH_IRQ_INIT_FLAGS
438 # define ARCH_IRQ_INIT_FLAGS 0
441 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
444 extern int setup_irq(unsigned int irq
, struct irqaction
*new);
445 extern void remove_irq(unsigned int irq
, struct irqaction
*act
);
446 extern int setup_percpu_irq(unsigned int irq
, struct irqaction
*new);
447 extern void remove_percpu_irq(unsigned int irq
, struct irqaction
*act
);
449 extern void irq_cpu_online(void);
450 extern void irq_cpu_offline(void);
451 extern int irq_set_affinity_locked(struct irq_data
*data
,
452 const struct cpumask
*cpumask
, bool force
);
453 extern int irq_set_vcpu_affinity(unsigned int irq
, void *vcpu_info
);
455 extern void irq_migrate_all_off_this_cpu(void);
457 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
458 void irq_move_irq(struct irq_data
*data
);
459 void irq_move_masked_irq(struct irq_data
*data
);
461 static inline void irq_move_irq(struct irq_data
*data
) { }
462 static inline void irq_move_masked_irq(struct irq_data
*data
) { }
465 extern int no_irq_affinity
;
467 #ifdef CONFIG_HARDIRQS_SW_RESEND
468 int irq_set_parent(int irq
, int parent_irq
);
470 static inline int irq_set_parent(int irq
, int parent_irq
)
477 * Built-in IRQ handlers for various IRQ types,
478 * callable via desc->handle_irq()
480 extern void handle_level_irq(struct irq_desc
*desc
);
481 extern void handle_fasteoi_irq(struct irq_desc
*desc
);
482 extern void handle_edge_irq(struct irq_desc
*desc
);
483 extern void handle_edge_eoi_irq(struct irq_desc
*desc
);
484 extern void handle_simple_irq(struct irq_desc
*desc
);
485 extern void handle_percpu_irq(struct irq_desc
*desc
);
486 extern void handle_percpu_devid_irq(struct irq_desc
*desc
);
487 extern void handle_bad_irq(struct irq_desc
*desc
);
488 extern void handle_nested_irq(unsigned int irq
);
490 extern int irq_chip_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
);
491 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
492 extern void irq_chip_enable_parent(struct irq_data
*data
);
493 extern void irq_chip_disable_parent(struct irq_data
*data
);
494 extern void irq_chip_ack_parent(struct irq_data
*data
);
495 extern int irq_chip_retrigger_hierarchy(struct irq_data
*data
);
496 extern void irq_chip_mask_parent(struct irq_data
*data
);
497 extern void irq_chip_unmask_parent(struct irq_data
*data
);
498 extern void irq_chip_eoi_parent(struct irq_data
*data
);
499 extern int irq_chip_set_affinity_parent(struct irq_data
*data
,
500 const struct cpumask
*dest
,
502 extern int irq_chip_set_wake_parent(struct irq_data
*data
, unsigned int on
);
503 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data
*data
,
505 extern int irq_chip_set_type_parent(struct irq_data
*data
, unsigned int type
);
508 /* Handling of unhandled and spurious interrupts: */
509 extern void note_interrupt(struct irq_desc
*desc
, irqreturn_t action_ret
);
512 /* Enable/disable irq debugging output: */
513 extern int noirqdebug_setup(char *str
);
515 /* Checks whether the interrupt can be requested by request_irq(): */
516 extern int can_request_irq(unsigned int irq
, unsigned long irqflags
);
518 /* Dummy irq-chip implementations: */
519 extern struct irq_chip no_irq_chip
;
520 extern struct irq_chip dummy_irq_chip
;
523 irq_set_chip_and_handler_name(unsigned int irq
, struct irq_chip
*chip
,
524 irq_flow_handler_t handle
, const char *name
);
526 static inline void irq_set_chip_and_handler(unsigned int irq
, struct irq_chip
*chip
,
527 irq_flow_handler_t handle
)
529 irq_set_chip_and_handler_name(irq
, chip
, handle
, NULL
);
532 extern int irq_set_percpu_devid(unsigned int irq
);
533 extern int irq_set_percpu_devid_partition(unsigned int irq
,
534 const struct cpumask
*affinity
);
535 extern int irq_get_percpu_devid_partition(unsigned int irq
,
536 struct cpumask
*affinity
);
539 __irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
, int is_chained
,
543 irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
)
545 __irq_set_handler(irq
, handle
, 0, NULL
);
549 * Set a highlevel chained flow handler for a given IRQ.
550 * (a chained handler is automatically enabled and set to
551 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
554 irq_set_chained_handler(unsigned int irq
, irq_flow_handler_t handle
)
556 __irq_set_handler(irq
, handle
, 1, NULL
);
560 * Set a highlevel chained flow handler and its data for a given IRQ.
561 * (a chained handler is automatically enabled and set to
562 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
565 irq_set_chained_handler_and_data(unsigned int irq
, irq_flow_handler_t handle
,
568 void irq_modify_status(unsigned int irq
, unsigned long clr
, unsigned long set
);
570 static inline void irq_set_status_flags(unsigned int irq
, unsigned long set
)
572 irq_modify_status(irq
, 0, set
);
575 static inline void irq_clear_status_flags(unsigned int irq
, unsigned long clr
)
577 irq_modify_status(irq
, clr
, 0);
580 static inline void irq_set_noprobe(unsigned int irq
)
582 irq_modify_status(irq
, 0, IRQ_NOPROBE
);
585 static inline void irq_set_probe(unsigned int irq
)
587 irq_modify_status(irq
, IRQ_NOPROBE
, 0);
590 static inline void irq_set_nothread(unsigned int irq
)
592 irq_modify_status(irq
, 0, IRQ_NOTHREAD
);
595 static inline void irq_set_thread(unsigned int irq
)
597 irq_modify_status(irq
, IRQ_NOTHREAD
, 0);
600 static inline void irq_set_nested_thread(unsigned int irq
, bool nest
)
603 irq_set_status_flags(irq
, IRQ_NESTED_THREAD
);
605 irq_clear_status_flags(irq
, IRQ_NESTED_THREAD
);
608 static inline void irq_set_percpu_devid_flags(unsigned int irq
)
610 irq_set_status_flags(irq
,
611 IRQ_NOAUTOEN
| IRQ_PER_CPU
| IRQ_NOTHREAD
|
612 IRQ_NOPROBE
| IRQ_PER_CPU_DEVID
);
615 /* Set/get chip/data for an IRQ: */
616 extern int irq_set_chip(unsigned int irq
, struct irq_chip
*chip
);
617 extern int irq_set_handler_data(unsigned int irq
, void *data
);
618 extern int irq_set_chip_data(unsigned int irq
, void *data
);
619 extern int irq_set_irq_type(unsigned int irq
, unsigned int type
);
620 extern int irq_set_msi_desc(unsigned int irq
, struct msi_desc
*entry
);
621 extern int irq_set_msi_desc_off(unsigned int irq_base
, unsigned int irq_offset
,
622 struct msi_desc
*entry
);
623 extern struct irq_data
*irq_get_irq_data(unsigned int irq
);
625 static inline struct irq_chip
*irq_get_chip(unsigned int irq
)
627 struct irq_data
*d
= irq_get_irq_data(irq
);
628 return d
? d
->chip
: NULL
;
631 static inline struct irq_chip
*irq_data_get_irq_chip(struct irq_data
*d
)
636 static inline void *irq_get_chip_data(unsigned int irq
)
638 struct irq_data
*d
= irq_get_irq_data(irq
);
639 return d
? d
->chip_data
: NULL
;
642 static inline void *irq_data_get_irq_chip_data(struct irq_data
*d
)
647 static inline void *irq_get_handler_data(unsigned int irq
)
649 struct irq_data
*d
= irq_get_irq_data(irq
);
650 return d
? d
->common
->handler_data
: NULL
;
653 static inline void *irq_data_get_irq_handler_data(struct irq_data
*d
)
655 return d
->common
->handler_data
;
658 static inline struct msi_desc
*irq_get_msi_desc(unsigned int irq
)
660 struct irq_data
*d
= irq_get_irq_data(irq
);
661 return d
? d
->common
->msi_desc
: NULL
;
664 static inline struct msi_desc
*irq_data_get_msi_desc(struct irq_data
*d
)
666 return d
->common
->msi_desc
;
669 static inline u32
irq_get_trigger_type(unsigned int irq
)
671 struct irq_data
*d
= irq_get_irq_data(irq
);
672 return d
? irqd_get_trigger_type(d
) : 0;
675 static inline int irq_common_data_get_node(struct irq_common_data
*d
)
684 static inline int irq_data_get_node(struct irq_data
*d
)
686 return irq_common_data_get_node(d
->common
);
689 static inline struct cpumask
*irq_get_affinity_mask(int irq
)
691 struct irq_data
*d
= irq_get_irq_data(irq
);
693 return d
? d
->common
->affinity
: NULL
;
696 static inline struct cpumask
*irq_data_get_affinity_mask(struct irq_data
*d
)
698 return d
->common
->affinity
;
701 unsigned int arch_dynirq_lower_bound(unsigned int from
);
703 int __irq_alloc_descs(int irq
, unsigned int from
, unsigned int cnt
, int node
,
704 struct module
*owner
);
706 /* use macros to avoid needing export.h for THIS_MODULE */
707 #define irq_alloc_descs(irq, from, cnt, node) \
708 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
710 #define irq_alloc_desc(node) \
711 irq_alloc_descs(-1, 0, 1, node)
713 #define irq_alloc_desc_at(at, node) \
714 irq_alloc_descs(at, at, 1, node)
716 #define irq_alloc_desc_from(from, node) \
717 irq_alloc_descs(-1, from, 1, node)
719 #define irq_alloc_descs_from(from, cnt, node) \
720 irq_alloc_descs(-1, from, cnt, node)
722 void irq_free_descs(unsigned int irq
, unsigned int cnt
);
723 static inline void irq_free_desc(unsigned int irq
)
725 irq_free_descs(irq
, 1);
728 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
729 unsigned int irq_alloc_hwirqs(int cnt
, int node
);
730 static inline unsigned int irq_alloc_hwirq(int node
)
732 return irq_alloc_hwirqs(1, node
);
734 void irq_free_hwirqs(unsigned int from
, int cnt
);
735 static inline void irq_free_hwirq(unsigned int irq
)
737 return irq_free_hwirqs(irq
, 1);
739 int arch_setup_hwirq(unsigned int irq
, int node
);
740 void arch_teardown_hwirq(unsigned int irq
);
743 #ifdef CONFIG_GENERIC_IRQ_LEGACY
744 void irq_init_desc(unsigned int irq
);
748 * struct irq_chip_regs - register offsets for struct irq_gci
749 * @enable: Enable register offset to reg_base
750 * @disable: Disable register offset to reg_base
751 * @mask: Mask register offset to reg_base
752 * @ack: Ack register offset to reg_base
753 * @eoi: Eoi register offset to reg_base
754 * @type: Type configuration register offset to reg_base
755 * @polarity: Polarity configuration register offset to reg_base
757 struct irq_chip_regs
{
758 unsigned long enable
;
759 unsigned long disable
;
764 unsigned long polarity
;
768 * struct irq_chip_type - Generic interrupt chip instance for a flow type
769 * @chip: The real interrupt chip which provides the callbacks
770 * @regs: Register offsets for this chip
771 * @handler: Flow handler associated with this chip
772 * @type: Chip can handle these flow types
773 * @mask_cache_priv: Cached mask register private to the chip type
774 * @mask_cache: Pointer to cached mask register
776 * A irq_generic_chip can have several instances of irq_chip_type when
777 * it requires different functions and register offsets for different
780 struct irq_chip_type
{
781 struct irq_chip chip
;
782 struct irq_chip_regs regs
;
783 irq_flow_handler_t handler
;
790 * struct irq_chip_generic - Generic irq chip data structure
791 * @lock: Lock to protect register and cache data access
792 * @reg_base: Register base address (virtual)
793 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
794 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
795 * @suspend: Function called from core code on suspend once per
796 * chip; can be useful instead of irq_chip::suspend to
797 * handle chip details even when no interrupts are in use
798 * @resume: Function called from core code on resume once per chip;
799 * can be useful instead of irq_chip::suspend to handle
800 * chip details even when no interrupts are in use
801 * @irq_base: Interrupt base nr for this chip
802 * @irq_cnt: Number of interrupts handled by this chip
803 * @mask_cache: Cached mask register shared between all chip types
804 * @type_cache: Cached type register
805 * @polarity_cache: Cached polarity register
806 * @wake_enabled: Interrupt can wakeup from suspend
807 * @wake_active: Interrupt is marked as an wakeup from suspend source
808 * @num_ct: Number of available irq_chip_type instances (usually 1)
809 * @private: Private data for non generic chip callbacks
810 * @installed: bitfield to denote installed interrupts
811 * @unused: bitfield to denote unused interrupts
812 * @domain: irq domain pointer
813 * @list: List head for keeping track of instances
814 * @chip_types: Array of interrupt irq_chip_types
816 * Note, that irq_chip_generic can have multiple irq_chip_type
817 * implementations which can be associated to a particular irq line of
818 * an irq_chip_generic instance. That allows to share and protect
819 * state in an irq_chip_generic instance when we need to implement
820 * different flow mechanisms (level/edge) for it.
822 struct irq_chip_generic
{
824 void __iomem
*reg_base
;
825 u32 (*reg_readl
)(void __iomem
*addr
);
826 void (*reg_writel
)(u32 val
, void __iomem
*addr
);
827 void (*suspend
)(struct irq_chip_generic
*gc
);
828 void (*resume
)(struct irq_chip_generic
*gc
);
829 unsigned int irq_base
;
830 unsigned int irq_cnt
;
838 unsigned long installed
;
839 unsigned long unused
;
840 struct irq_domain
*domain
;
841 struct list_head list
;
842 struct irq_chip_type chip_types
[0];
846 * enum irq_gc_flags - Initialization flags for generic irq chips
847 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
848 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
849 * irq chips which need to call irq_set_wake() on
850 * the parent irq. Usually GPIO implementations
851 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
852 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
853 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
856 IRQ_GC_INIT_MASK_CACHE
= 1 << 0,
857 IRQ_GC_INIT_NESTED_LOCK
= 1 << 1,
858 IRQ_GC_MASK_CACHE_PER_TYPE
= 1 << 2,
859 IRQ_GC_NO_MASK
= 1 << 3,
860 IRQ_GC_BE_IO
= 1 << 4,
864 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
865 * @irqs_per_chip: Number of interrupts per chip
866 * @num_chips: Number of chips
867 * @irq_flags_to_set: IRQ* flags to set on irq setup
868 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
869 * @gc_flags: Generic chip specific setup flags
870 * @gc: Array of pointers to generic interrupt chips
872 struct irq_domain_chip_generic
{
873 unsigned int irqs_per_chip
;
874 unsigned int num_chips
;
875 unsigned int irq_flags_to_clear
;
876 unsigned int irq_flags_to_set
;
877 enum irq_gc_flags gc_flags
;
878 struct irq_chip_generic
*gc
[0];
881 /* Generic chip callback functions */
882 void irq_gc_noop(struct irq_data
*d
);
883 void irq_gc_mask_disable_reg(struct irq_data
*d
);
884 void irq_gc_mask_set_bit(struct irq_data
*d
);
885 void irq_gc_mask_clr_bit(struct irq_data
*d
);
886 void irq_gc_unmask_enable_reg(struct irq_data
*d
);
887 void irq_gc_ack_set_bit(struct irq_data
*d
);
888 void irq_gc_ack_clr_bit(struct irq_data
*d
);
889 void irq_gc_mask_disable_reg_and_ack(struct irq_data
*d
);
890 void irq_gc_eoi(struct irq_data
*d
);
891 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
);
893 /* Setup functions for irq_chip_generic */
894 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
895 irq_hw_number_t hw_irq
);
896 struct irq_chip_generic
*
897 irq_alloc_generic_chip(const char *name
, int nr_ct
, unsigned int irq_base
,
898 void __iomem
*reg_base
, irq_flow_handler_t handler
);
899 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
900 enum irq_gc_flags flags
, unsigned int clr
,
902 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
);
903 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
904 unsigned int clr
, unsigned int set
);
906 struct irq_chip_generic
*irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
);
907 int irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
908 int num_ct
, const char *name
,
909 irq_flow_handler_t handler
,
910 unsigned int clr
, unsigned int set
,
911 enum irq_gc_flags flags
);
914 static inline struct irq_chip_type
*irq_data_get_chip_type(struct irq_data
*d
)
916 return container_of(d
->chip
, struct irq_chip_type
, chip
);
919 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
922 static inline void irq_gc_lock(struct irq_chip_generic
*gc
)
924 raw_spin_lock(&gc
->lock
);
927 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
)
929 raw_spin_unlock(&gc
->lock
);
932 static inline void irq_gc_lock(struct irq_chip_generic
*gc
) { }
933 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
) { }
936 static inline void irq_reg_writel(struct irq_chip_generic
*gc
,
937 u32 val
, int reg_offset
)
940 gc
->reg_writel(val
, gc
->reg_base
+ reg_offset
);
942 writel(val
, gc
->reg_base
+ reg_offset
);
945 static inline u32
irq_reg_readl(struct irq_chip_generic
*gc
,
949 return gc
->reg_readl(gc
->reg_base
+ reg_offset
);
951 return readl(gc
->reg_base
+ reg_offset
);
954 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
955 #define INVALID_HWIRQ (~0UL)
956 irq_hw_number_t
ipi_get_hwirq(unsigned int irq
, unsigned int cpu
);
957 int __ipi_send_single(struct irq_desc
*desc
, unsigned int cpu
);
958 int __ipi_send_mask(struct irq_desc
*desc
, const struct cpumask
*dest
);
959 int ipi_send_single(unsigned int virq
, unsigned int cpu
);
960 int ipi_send_mask(unsigned int virq
, const struct cpumask
*dest
);
962 #endif /* _LINUX_IRQ_H */