include/linux/irqchip/arm-gic.h

   1 /*
   2  *  include/linux/irqchip/arm-gic.h
   3  *
   4  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef __LINUX_IRQCHIP_ARM_GIC_H
  11 #define __LINUX_IRQCHIP_ARM_GIC_H
  12
  13 #define GIC_CPU_CTRL                    0x00
  14 #define GIC_CPU_PRIMASK                 0x04
  15 #define GIC_CPU_BINPOINT                0x08
  16 #define GIC_CPU_INTACK                  0x0c
  17 #define GIC_CPU_EOI                     0x10
  18 #define GIC_CPU_RUNNINGPRI              0x14
  19 #define GIC_CPU_HIGHPRI                 0x18
  20 #define GIC_CPU_ALIAS_BINPOINT          0x1c
  21 #define GIC_CPU_ACTIVEPRIO              0xd0
  22 #define GIC_CPU_IDENT                   0xfc
  23 #define GIC_CPU_DEACTIVATE              0x1000
  24
  25 #define GICC_ENABLE                     0x1
  26 #define GICC_INT_PRI_THRESHOLD          0xf0
  27
  28 #define GIC_CPU_CTRL_EOImodeNS          (1 << 9)
  29
  30 #define GICC_IAR_INT_ID_MASK            0x3ff
  31 #define GICC_INT_SPURIOUS               1023
  32 #define GICC_DIS_BYPASS_MASK            0x1e0
  33
  34 #define GIC_DIST_CTRL                   0x000
  35 #define GIC_DIST_CTR                    0x004
  36 #define GIC_DIST_IIDR                   0x008
  37 #define GIC_DIST_IGROUP                 0x080
  38 #define GIC_DIST_ENABLE_SET             0x100
  39 #define GIC_DIST_ENABLE_CLEAR           0x180
  40 #define GIC_DIST_PENDING_SET            0x200
  41 #define GIC_DIST_PENDING_CLEAR          0x280
  42 #define GIC_DIST_ACTIVE_SET             0x300
  43 #define GIC_DIST_ACTIVE_CLEAR           0x380
  44 #define GIC_DIST_PRI                    0x400
  45 #define GIC_DIST_TARGET                 0x800
  46 #define GIC_DIST_CONFIG                 0xc00
  47 #define GIC_DIST_SOFTINT                0xf00
  48 #define GIC_DIST_SGI_PENDING_CLEAR      0xf10
  49 #define GIC_DIST_SGI_PENDING_SET        0xf20
  50
  51 #define GICD_ENABLE                     0x1
  52 #define GICD_DISABLE                    0x0
  53 #define GICD_INT_ACTLOW_LVLTRIG         0x0
  54 #define GICD_INT_EN_CLR_X32             0xffffffff
  55 #define GICD_INT_EN_SET_SGI             0x0000ffff
  56 #define GICD_INT_EN_CLR_PPI             0xffff0000
  57 #define GICD_INT_DEF_PRI                0xa0
  58 #define GICD_INT_DEF_PRI_X4             ((GICD_INT_DEF_PRI << 24) |\
  59                                         (GICD_INT_DEF_PRI << 16) |\
  60                                         (GICD_INT_DEF_PRI << 8) |\
  61                                         GICD_INT_DEF_PRI)
  62
  63 #define GICH_HCR                        0x0
  64 #define GICH_VTR                        0x4
  65 #define GICH_VMCR                       0x8
  66 #define GICH_MISR                       0x10
  67 #define GICH_EISR0                      0x20
  68 #define GICH_EISR1                      0x24
  69 #define GICH_ELRSR0                     0x30
  70 #define GICH_ELRSR1                     0x34
  71 #define GICH_APR                        0xf0
  72 #define GICH_LR0                        0x100
  73
  74 #define GICH_HCR_EN                     (1 << 0)
  75 #define GICH_HCR_UIE                    (1 << 1)
  76
  77 #define GICH_LR_VIRTUALID               (0x3ff << 0)
  78 #define GICH_LR_PHYSID_CPUID_SHIFT      (10)
  79 #define GICH_LR_PHYSID_CPUID            (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)
  80 #define GICH_LR_PRIORITY_SHIFT          23
  81 #define GICH_LR_STATE                   (3 << 28)
  82 #define GICH_LR_PENDING_BIT             (1 << 28)
  83 #define GICH_LR_ACTIVE_BIT              (1 << 29)
  84 #define GICH_LR_EOI                     (1 << 19)
  85 #define GICH_LR_HW                      (1 << 31)
  86
  87 #define GICH_VMCR_CTRL_SHIFT            0
  88 #define GICH_VMCR_CTRL_MASK             (0x21f << GICH_VMCR_CTRL_SHIFT)
  89 #define GICH_VMCR_PRIMASK_SHIFT         27
  90 #define GICH_VMCR_PRIMASK_MASK          (0x1f << GICH_VMCR_PRIMASK_SHIFT)
  91 #define GICH_VMCR_BINPOINT_SHIFT        21
  92 #define GICH_VMCR_BINPOINT_MASK         (0x7 << GICH_VMCR_BINPOINT_SHIFT)
  93 #define GICH_VMCR_ALIAS_BINPOINT_SHIFT  18
  94 #define GICH_VMCR_ALIAS_BINPOINT_MASK   (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
  95
  96 #define GICH_MISR_EOI                   (1 << 0)
  97 #define GICH_MISR_U                     (1 << 1)
  98
  99 #ifndef __ASSEMBLY__
 100
 101 #include <linux/irqdomain.h>
 102
 103 struct device_node;
 104
 105 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 106 int gic_cpu_if_down(unsigned int gic_nr);
 107
 108 /*
 109  * Subdrivers that need some preparatory work can initialize their
 110  * chips and call this to register their GICs.
 111  */
 112 int gic_of_init(struct device_node *node, struct device_node *parent);
 113
 114 /*
 115  * Legacy platforms not converted to DT yet must use this to init
 116  * their GIC
 117  */
 118 void gic_init(unsigned int nr, int start,
 119               void __iomem *dist , void __iomem *cpu);
 120
 121 int gicv2m_init(struct fwnode_handle *parent_handle,
 122                 struct irq_domain *parent);
 123
 124 void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
 125 int gic_get_cpu_id(unsigned int cpu);
 126 void gic_migrate_target(unsigned int new_cpu_id);
 127 unsigned long gic_get_sgir_physaddr(void);
 128
 129 #endif /* __ASSEMBLY */
 130 #endif