include/linux/mfd/samsung/irq.h

   1 /* irq.h
   2  *
   3  * Copyright (c) 2012 Samsung Electronics Co., Ltd
   4  *              http://www.samsung.com
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  */
  12
  13 #ifndef __LINUX_MFD_SEC_IRQ_H
  14 #define __LINUX_MFD_SEC_IRQ_H
  15
  16 enum s2mpa01_irq {
  17         S2MPA01_IRQ_PWRONF,
  18         S2MPA01_IRQ_PWRONR,
  19         S2MPA01_IRQ_JIGONBF,
  20         S2MPA01_IRQ_JIGONBR,
  21         S2MPA01_IRQ_ACOKBF,
  22         S2MPA01_IRQ_ACOKBR,
  23         S2MPA01_IRQ_PWRON1S,
  24         S2MPA01_IRQ_MRB,
  25
  26         S2MPA01_IRQ_RTC60S,
  27         S2MPA01_IRQ_RTCA1,
  28         S2MPA01_IRQ_RTCA0,
  29         S2MPA01_IRQ_SMPL,
  30         S2MPA01_IRQ_RTC1S,
  31         S2MPA01_IRQ_WTSR,
  32
  33         S2MPA01_IRQ_INT120C,
  34         S2MPA01_IRQ_INT140C,
  35         S2MPA01_IRQ_LDO3_TSD,
  36         S2MPA01_IRQ_B16_TSD,
  37         S2MPA01_IRQ_B24_TSD,
  38         S2MPA01_IRQ_B35_TSD,
  39
  40         S2MPA01_IRQ_NR,
  41 };
  42
  43 #define S2MPA01_IRQ_PWRONF_MASK         (1 << 0)
  44 #define S2MPA01_IRQ_PWRONR_MASK         (1 << 1)
  45 #define S2MPA01_IRQ_JIGONBF_MASK        (1 << 2)
  46 #define S2MPA01_IRQ_JIGONBR_MASK        (1 << 3)
  47 #define S2MPA01_IRQ_ACOKBF_MASK         (1 << 4)
  48 #define S2MPA01_IRQ_ACOKBR_MASK         (1 << 5)
  49 #define S2MPA01_IRQ_PWRON1S_MASK        (1 << 6)
  50 #define S2MPA01_IRQ_MRB_MASK            (1 << 7)
  51
  52 #define S2MPA01_IRQ_RTC60S_MASK         (1 << 0)
  53 #define S2MPA01_IRQ_RTCA1_MASK          (1 << 1)
  54 #define S2MPA01_IRQ_RTCA0_MASK          (1 << 2)
  55 #define S2MPA01_IRQ_SMPL_MASK           (1 << 3)
  56 #define S2MPA01_IRQ_RTC1S_MASK          (1 << 4)
  57 #define S2MPA01_IRQ_WTSR_MASK           (1 << 5)
  58
  59 #define S2MPA01_IRQ_INT120C_MASK        (1 << 0)
  60 #define S2MPA01_IRQ_INT140C_MASK        (1 << 1)
  61 #define S2MPA01_IRQ_LDO3_TSD_MASK       (1 << 2)
  62 #define S2MPA01_IRQ_B16_TSD_MASK        (1 << 3)
  63 #define S2MPA01_IRQ_B24_TSD_MASK        (1 << 4)
  64 #define S2MPA01_IRQ_B35_TSD_MASK        (1 << 5)
  65
  66 enum s2mps11_irq {
  67         S2MPS11_IRQ_PWRONF,
  68         S2MPS11_IRQ_PWRONR,
  69         S2MPS11_IRQ_JIGONBF,
  70         S2MPS11_IRQ_JIGONBR,
  71         S2MPS11_IRQ_ACOKBF,
  72         S2MPS11_IRQ_ACOKBR,
  73         S2MPS11_IRQ_PWRON1S,
  74         S2MPS11_IRQ_MRB,
  75
  76         S2MPS11_IRQ_RTC60S,
  77         S2MPS11_IRQ_RTCA0,
  78         S2MPS11_IRQ_RTCA1,
  79         S2MPS11_IRQ_SMPL,
  80         S2MPS11_IRQ_RTC1S,
  81         S2MPS11_IRQ_WTSR,
  82
  83         S2MPS11_IRQ_INT120C,
  84         S2MPS11_IRQ_INT140C,
  85
  86         S2MPS11_IRQ_NR,
  87 };
  88
  89 #define S2MPS11_IRQ_PWRONF_MASK         (1 << 0)
  90 #define S2MPS11_IRQ_PWRONR_MASK         (1 << 1)
  91 #define S2MPS11_IRQ_JIGONBF_MASK        (1 << 2)
  92 #define S2MPS11_IRQ_JIGONBR_MASK        (1 << 3)
  93 #define S2MPS11_IRQ_ACOKBF_MASK         (1 << 4)
  94 #define S2MPS11_IRQ_ACOKBR_MASK         (1 << 5)
  95 #define S2MPS11_IRQ_PWRON1S_MASK        (1 << 6)
  96 #define S2MPS11_IRQ_MRB_MASK            (1 << 7)
  97
  98 #define S2MPS11_IRQ_RTC60S_MASK         (1 << 0)
  99 #define S2MPS11_IRQ_RTCA1_MASK          (1 << 1)
 100 #define S2MPS11_IRQ_RTCA0_MASK          (1 << 2)
 101 #define S2MPS11_IRQ_SMPL_MASK           (1 << 3)
 102 #define S2MPS11_IRQ_RTC1S_MASK          (1 << 4)
 103 #define S2MPS11_IRQ_WTSR_MASK           (1 << 5)
 104
 105 #define S2MPS11_IRQ_INT120C_MASK        (1 << 0)
 106 #define S2MPS11_IRQ_INT140C_MASK        (1 << 1)
 107
 108 enum s2mps14_irq {
 109         S2MPS14_IRQ_PWRONF,
 110         S2MPS14_IRQ_PWRONR,
 111         S2MPS14_IRQ_JIGONBF,
 112         S2MPS14_IRQ_JIGONBR,
 113         S2MPS14_IRQ_ACOKBF,
 114         S2MPS14_IRQ_ACOKBR,
 115         S2MPS14_IRQ_PWRON1S,
 116         S2MPS14_IRQ_MRB,
 117
 118         S2MPS14_IRQ_RTC60S,
 119         S2MPS14_IRQ_RTCA1,
 120         S2MPS14_IRQ_RTCA0,
 121         S2MPS14_IRQ_SMPL,
 122         S2MPS14_IRQ_RTC1S,
 123         S2MPS14_IRQ_WTSR,
 124
 125         S2MPS14_IRQ_INT120C,
 126         S2MPS14_IRQ_INT140C,
 127         S2MPS14_IRQ_TSD,
 128
 129         S2MPS14_IRQ_NR,
 130 };
 131
 132 /* Masks for interrupts are the same as in s2mps11 */
 133 #define S2MPS14_IRQ_TSD_MASK            (1 << 2)
 134
 135 enum s5m8767_irq {
 136         S5M8767_IRQ_PWRR,
 137         S5M8767_IRQ_PWRF,
 138         S5M8767_IRQ_PWR1S,
 139         S5M8767_IRQ_JIGR,
 140         S5M8767_IRQ_JIGF,
 141         S5M8767_IRQ_LOWBAT2,
 142         S5M8767_IRQ_LOWBAT1,
 143
 144         S5M8767_IRQ_MRB,
 145         S5M8767_IRQ_DVSOK2,
 146         S5M8767_IRQ_DVSOK3,
 147         S5M8767_IRQ_DVSOK4,
 148
 149         S5M8767_IRQ_RTC60S,
 150         S5M8767_IRQ_RTCA1,
 151         S5M8767_IRQ_RTCA2,
 152         S5M8767_IRQ_SMPL,
 153         S5M8767_IRQ_RTC1S,
 154         S5M8767_IRQ_WTSR,
 155
 156         S5M8767_IRQ_NR,
 157 };
 158
 159 #define S5M8767_IRQ_PWRR_MASK           (1 << 0)
 160 #define S5M8767_IRQ_PWRF_MASK           (1 << 1)
 161 #define S5M8767_IRQ_PWR1S_MASK          (1 << 3)
 162 #define S5M8767_IRQ_JIGR_MASK           (1 << 4)
 163 #define S5M8767_IRQ_JIGF_MASK           (1 << 5)
 164 #define S5M8767_IRQ_LOWBAT2_MASK        (1 << 6)
 165 #define S5M8767_IRQ_LOWBAT1_MASK        (1 << 7)
 166
 167 #define S5M8767_IRQ_MRB_MASK            (1 << 2)
 168 #define S5M8767_IRQ_DVSOK2_MASK         (1 << 3)
 169 #define S5M8767_IRQ_DVSOK3_MASK         (1 << 4)
 170 #define S5M8767_IRQ_DVSOK4_MASK         (1 << 5)
 171
 172 #define S5M8767_IRQ_RTC60S_MASK         (1 << 0)
 173 #define S5M8767_IRQ_RTCA1_MASK          (1 << 1)
 174 #define S5M8767_IRQ_RTCA2_MASK          (1 << 2)
 175 #define S5M8767_IRQ_SMPL_MASK           (1 << 3)
 176 #define S5M8767_IRQ_RTC1S_MASK          (1 << 4)
 177 #define S5M8767_IRQ_WTSR_MASK           (1 << 5)
 178
 179 enum s5m8763_irq {
 180         S5M8763_IRQ_DCINF,
 181         S5M8763_IRQ_DCINR,
 182         S5M8763_IRQ_JIGF,
 183         S5M8763_IRQ_JIGR,
 184         S5M8763_IRQ_PWRONF,
 185         S5M8763_IRQ_PWRONR,
 186
 187         S5M8763_IRQ_WTSREVNT,
 188         S5M8763_IRQ_SMPLEVNT,
 189         S5M8763_IRQ_ALARM1,
 190         S5M8763_IRQ_ALARM0,
 191
 192         S5M8763_IRQ_ONKEY1S,
 193         S5M8763_IRQ_TOPOFFR,
 194         S5M8763_IRQ_DCINOVPR,
 195         S5M8763_IRQ_CHGRSTF,
 196         S5M8763_IRQ_DONER,
 197         S5M8763_IRQ_CHGFAULT,
 198
 199         S5M8763_IRQ_LOBAT1,
 200         S5M8763_IRQ_LOBAT2,
 201
 202         S5M8763_IRQ_NR,
 203 };
 204
 205 #define S5M8763_IRQ_DCINF_MASK          (1 << 2)
 206 #define S5M8763_IRQ_DCINR_MASK          (1 << 3)
 207 #define S5M8763_IRQ_JIGF_MASK           (1 << 4)
 208 #define S5M8763_IRQ_JIGR_MASK           (1 << 5)
 209 #define S5M8763_IRQ_PWRONF_MASK         (1 << 6)
 210 #define S5M8763_IRQ_PWRONR_MASK         (1 << 7)
 211
 212 #define S5M8763_IRQ_WTSREVNT_MASK       (1 << 0)
 213 #define S5M8763_IRQ_SMPLEVNT_MASK       (1 << 1)
 214 #define S5M8763_IRQ_ALARM1_MASK         (1 << 2)
 215 #define S5M8763_IRQ_ALARM0_MASK         (1 << 3)
 216
 217 #define S5M8763_IRQ_ONKEY1S_MASK        (1 << 0)
 218 #define S5M8763_IRQ_TOPOFFR_MASK        (1 << 2)
 219 #define S5M8763_IRQ_DCINOVPR_MASK       (1 << 3)
 220 #define S5M8763_IRQ_CHGRSTF_MASK        (1 << 4)
 221 #define S5M8763_IRQ_DONER_MASK          (1 << 5)
 222 #define S5M8763_IRQ_CHGFAULT_MASK       (1 << 7)
 223
 224 #define S5M8763_IRQ_LOBAT1_MASK         (1 << 0)
 225 #define S5M8763_IRQ_LOBAT2_MASK         (1 << 1)
 226
 227 #define S5M8763_ENRAMP                  (1 << 4)
 228
 229 #endif /*  __LINUX_MFD_SEC_IRQ_H */