5f770064e0c5f252421d954d410b73afc4084667
2 * tps65910.h -- TI TPS6591x
4 * Copyright 2010-2011 Texas Instruments Inc.
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * Author: Arnaud Deconinck <a-deconinck@ti.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 #ifndef __LINUX_MFD_TPS65910_H
18 #define __LINUX_MFD_TPS65910_H
20 /* TPS chip id list */
24 /* TPS regulator type list */
25 #define REGULATOR_LDO 0
26 #define REGULATOR_DCDC 1
29 * List of registers for component TPS65910
33 #define TPS65910_SECONDS 0x0
34 #define TPS65910_MINUTES 0x1
35 #define TPS65910_HOURS 0x2
36 #define TPS65910_DAYS 0x3
37 #define TPS65910_MONTHS 0x4
38 #define TPS65910_YEARS 0x5
39 #define TPS65910_WEEKS 0x6
40 #define TPS65910_ALARM_SECONDS 0x8
41 #define TPS65910_ALARM_MINUTES 0x9
42 #define TPS65910_ALARM_HOURS 0xA
43 #define TPS65910_ALARM_DAYS 0xB
44 #define TPS65910_ALARM_MONTHS 0xC
45 #define TPS65910_ALARM_YEARS 0xD
46 #define TPS65910_RTC_CTRL 0x10
47 #define TPS65910_RTC_STATUS 0x11
48 #define TPS65910_RTC_INTERRUPTS 0x12
49 #define TPS65910_RTC_COMP_LSB 0x13
50 #define TPS65910_RTC_COMP_MSB 0x14
51 #define TPS65910_RTC_RES_PROG 0x15
52 #define TPS65910_RTC_RESET_STATUS 0x16
53 #define TPS65910_BCK1 0x17
54 #define TPS65910_BCK2 0x18
55 #define TPS65910_BCK3 0x19
56 #define TPS65910_BCK4 0x1A
57 #define TPS65910_BCK5 0x1B
58 #define TPS65910_PUADEN 0x1C
59 #define TPS65910_REF 0x1D
60 #define TPS65910_VRTC 0x1E
61 #define TPS65910_VIO 0x20
62 #define TPS65910_VDD1 0x21
63 #define TPS65910_VDD1_OP 0x22
64 #define TPS65910_VDD1_SR 0x23
65 #define TPS65910_VDD2 0x24
66 #define TPS65910_VDD2_OP 0x25
67 #define TPS65910_VDD2_SR 0x26
68 #define TPS65910_VDD3 0x27
69 #define TPS65910_VDIG1 0x30
70 #define TPS65910_VDIG2 0x31
71 #define TPS65910_VAUX1 0x32
72 #define TPS65910_VAUX2 0x33
73 #define TPS65910_VAUX33 0x34
74 #define TPS65910_VMMC 0x35
75 #define TPS65910_VPLL 0x36
76 #define TPS65910_VDAC 0x37
77 #define TPS65910_THERM 0x38
78 #define TPS65910_BBCH 0x39
79 #define TPS65910_DCDCCTRL 0x3E
80 #define TPS65910_DEVCTRL 0x3F
81 #define TPS65910_DEVCTRL2 0x40
82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41
83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42
84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43
85 #define TPS65910_SLEEP_SET_RES_OFF 0x44
86 #define TPS65910_EN1_LDO_ASS 0x45
87 #define TPS65910_EN1_SMPS_ASS 0x46
88 #define TPS65910_EN2_LDO_ASS 0x47
89 #define TPS65910_EN2_SMPS_ASS 0x48
90 #define TPS65910_EN3_LDO_ASS 0x49
91 #define TPS65910_SPARE 0x4A
92 #define TPS65910_INT_STS 0x50
93 #define TPS65910_INT_MSK 0x51
94 #define TPS65910_INT_STS2 0x52
95 #define TPS65910_INT_MSK2 0x53
96 #define TPS65910_INT_STS3 0x54
97 #define TPS65910_INT_MSK3 0x55
98 #define TPS65910_GPIO0 0x60
99 #define TPS65910_GPIO1 0x61
100 #define TPS65910_GPIO2 0x62
101 #define TPS65910_GPIO3 0x63
102 #define TPS65910_GPIO4 0x64
103 #define TPS65910_GPIO5 0x65
104 #define TPS65910_GPIO6 0x66
105 #define TPS65910_GPIO7 0x67
106 #define TPS65910_GPIO8 0x68
107 #define TPS65910_JTAGVERNUM 0x80
108 #define TPS65910_MAX_REGISTER 0x80
111 * List of registers specific to TPS65911
113 #define TPS65911_VDDCTRL 0x27
114 #define TPS65911_VDDCTRL_OP 0x28
115 #define TPS65911_VDDCTRL_SR 0x29
116 #define TPS65911_LDO1 0x30
117 #define TPS65911_LDO2 0x31
118 #define TPS65911_LDO5 0x32
119 #define TPS65911_LDO8 0x33
120 #define TPS65911_LDO7 0x34
121 #define TPS65911_LDO6 0x35
122 #define TPS65911_LDO4 0x36
123 #define TPS65911_LDO3 0x37
126 * List of register bitfields for component TPS65910
131 /*Register BCK1 (0x80) register.RegisterDescription */
132 #define BCK1_BCKUP_MASK 0xFF
133 #define BCK1_BCKUP_SHIFT 0
136 /*Register BCK2 (0x80) register.RegisterDescription */
137 #define BCK2_BCKUP_MASK 0xFF
138 #define BCK2_BCKUP_SHIFT 0
141 /*Register BCK3 (0x80) register.RegisterDescription */
142 #define BCK3_BCKUP_MASK 0xFF
143 #define BCK3_BCKUP_SHIFT 0
146 /*Register BCK4 (0x80) register.RegisterDescription */
147 #define BCK4_BCKUP_MASK 0xFF
148 #define BCK4_BCKUP_SHIFT 0
151 /*Register BCK5 (0x80) register.RegisterDescription */
152 #define BCK5_BCKUP_MASK 0xFF
153 #define BCK5_BCKUP_SHIFT 0
156 /*Register PUADEN (0x80) register.RegisterDescription */
157 #define PUADEN_EN3P_MASK 0x80
158 #define PUADEN_EN3P_SHIFT 7
159 #define PUADEN_I2CCTLP_MASK 0x40
160 #define PUADEN_I2CCTLP_SHIFT 6
161 #define PUADEN_I2CSRP_MASK 0x20
162 #define PUADEN_I2CSRP_SHIFT 5
163 #define PUADEN_PWRONP_MASK 0x10
164 #define PUADEN_PWRONP_SHIFT 4
165 #define PUADEN_SLEEPP_MASK 0x08
166 #define PUADEN_SLEEPP_SHIFT 3
167 #define PUADEN_PWRHOLDP_MASK 0x04
168 #define PUADEN_PWRHOLDP_SHIFT 2
169 #define PUADEN_BOOT1P_MASK 0x02
170 #define PUADEN_BOOT1P_SHIFT 1
171 #define PUADEN_BOOT0P_MASK 0x01
172 #define PUADEN_BOOT0P_SHIFT 0
175 /*Register REF (0x80) register.RegisterDescription */
176 #define REF_VMBCH_SEL_MASK 0x0C
177 #define REF_VMBCH_SEL_SHIFT 2
178 #define REF_ST_MASK 0x03
179 #define REF_ST_SHIFT 0
182 /*Register VRTC (0x80) register.RegisterDescription */
183 #define VRTC_VRTC_OFFMASK_MASK 0x08
184 #define VRTC_VRTC_OFFMASK_SHIFT 3
185 #define VRTC_ST_MASK 0x03
186 #define VRTC_ST_SHIFT 0
189 /*Register VIO (0x80) register.RegisterDescription */
190 #define VIO_ILMAX_MASK 0xC0
191 #define VIO_ILMAX_SHIFT 6
192 #define VIO_SEL_MASK 0x0C
193 #define VIO_SEL_SHIFT 2
194 #define VIO_ST_MASK 0x03
195 #define VIO_ST_SHIFT 0
198 /*Register VDD1 (0x80) register.RegisterDescription */
199 #define VDD1_VGAIN_SEL_MASK 0xC0
200 #define VDD1_VGAIN_SEL_SHIFT 6
201 #define VDD1_ILMAX_MASK 0x20
202 #define VDD1_ILMAX_SHIFT 5
203 #define VDD1_TSTEP_MASK 0x1C
204 #define VDD1_TSTEP_SHIFT 2
205 #define VDD1_ST_MASK 0x03
206 #define VDD1_ST_SHIFT 0
209 /*Register VDD1_OP (0x80) register.RegisterDescription */
210 #define VDD1_OP_CMD_MASK 0x80
211 #define VDD1_OP_CMD_SHIFT 7
212 #define VDD1_OP_SEL_MASK 0x7F
213 #define VDD1_OP_SEL_SHIFT 0
216 /*Register VDD1_SR (0x80) register.RegisterDescription */
217 #define VDD1_SR_SEL_MASK 0x7F
218 #define VDD1_SR_SEL_SHIFT 0
221 /*Register VDD2 (0x80) register.RegisterDescription */
222 #define VDD2_VGAIN_SEL_MASK 0xC0
223 #define VDD2_VGAIN_SEL_SHIFT 6
224 #define VDD2_ILMAX_MASK 0x20
225 #define VDD2_ILMAX_SHIFT 5
226 #define VDD2_TSTEP_MASK 0x1C
227 #define VDD2_TSTEP_SHIFT 2
228 #define VDD2_ST_MASK 0x03
229 #define VDD2_ST_SHIFT 0
232 /*Register VDD2_OP (0x80) register.RegisterDescription */
233 #define VDD2_OP_CMD_MASK 0x80
234 #define VDD2_OP_CMD_SHIFT 7
235 #define VDD2_OP_SEL_MASK 0x7F
236 #define VDD2_OP_SEL_SHIFT 0
238 /*Register VDD2_SR (0x80) register.RegisterDescription */
239 #define VDD2_SR_SEL_MASK 0x7F
240 #define VDD2_SR_SEL_SHIFT 0
243 /*Registers VDD1, VDD2 voltage values definitions */
244 #define VDD1_2_NUM_VOLTS 73
245 #define VDD1_2_MIN_VOLT 6000
246 #define VDD1_2_OFFSET 125
249 /*Register VDD3 (0x80) register.RegisterDescription */
250 #define VDD3_CKINEN_MASK 0x04
251 #define VDD3_CKINEN_SHIFT 2
252 #define VDD3_ST_MASK 0x03
253 #define VDD3_ST_SHIFT 0
254 #define VDDCTRL_MIN_VOLT 6000
255 #define VDDCTRL_OFFSET 125
257 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
258 #define LDO_SEL_MASK 0x0C
259 #define LDO_SEL_SHIFT 2
260 #define LDO_ST_MASK 0x03
261 #define LDO_ST_SHIFT 0
262 #define LDO_ST_ON_BIT 0x01
263 #define LDO_ST_MODE_BIT 0x02
266 /* Registers LDO1 to LDO8 in tps65910 */
267 #define LDO1_SEL_MASK 0xFC
268 #define LDO3_SEL_MASK 0x7C
269 #define LDO_MIN_VOLT 1000
270 #define LDO_MAX_VOLT 3300;
273 /*Register VDIG1 (0x80) register.RegisterDescription */
274 #define VDIG1_SEL_MASK 0x0C
275 #define VDIG1_SEL_SHIFT 2
276 #define VDIG1_ST_MASK 0x03
277 #define VDIG1_ST_SHIFT 0
280 /*Register VDIG2 (0x80) register.RegisterDescription */
281 #define VDIG2_SEL_MASK 0x0C
282 #define VDIG2_SEL_SHIFT 2
283 #define VDIG2_ST_MASK 0x03
284 #define VDIG2_ST_SHIFT 0
287 /*Register VAUX1 (0x80) register.RegisterDescription */
288 #define VAUX1_SEL_MASK 0x0C
289 #define VAUX1_SEL_SHIFT 2
290 #define VAUX1_ST_MASK 0x03
291 #define VAUX1_ST_SHIFT 0
294 /*Register VAUX2 (0x80) register.RegisterDescription */
295 #define VAUX2_SEL_MASK 0x0C
296 #define VAUX2_SEL_SHIFT 2
297 #define VAUX2_ST_MASK 0x03
298 #define VAUX2_ST_SHIFT 0
301 /*Register VAUX33 (0x80) register.RegisterDescription */
302 #define VAUX33_SEL_MASK 0x0C
303 #define VAUX33_SEL_SHIFT 2
304 #define VAUX33_ST_MASK 0x03
305 #define VAUX33_ST_SHIFT 0
308 /*Register VMMC (0x80) register.RegisterDescription */
309 #define VMMC_SEL_MASK 0x0C
310 #define VMMC_SEL_SHIFT 2
311 #define VMMC_ST_MASK 0x03
312 #define VMMC_ST_SHIFT 0
315 /*Register VPLL (0x80) register.RegisterDescription */
316 #define VPLL_SEL_MASK 0x0C
317 #define VPLL_SEL_SHIFT 2
318 #define VPLL_ST_MASK 0x03
319 #define VPLL_ST_SHIFT 0
322 /*Register VDAC (0x80) register.RegisterDescription */
323 #define VDAC_SEL_MASK 0x0C
324 #define VDAC_SEL_SHIFT 2
325 #define VDAC_ST_MASK 0x03
326 #define VDAC_ST_SHIFT 0
329 /*Register THERM (0x80) register.RegisterDescription */
330 #define THERM_THERM_HD_MASK 0x20
331 #define THERM_THERM_HD_SHIFT 5
332 #define THERM_THERM_TS_MASK 0x10
333 #define THERM_THERM_TS_SHIFT 4
334 #define THERM_THERM_HDSEL_MASK 0x0C
335 #define THERM_THERM_HDSEL_SHIFT 2
336 #define THERM_RSVD1_MASK 0x02
337 #define THERM_RSVD1_SHIFT 1
338 #define THERM_THERM_STATE_MASK 0x01
339 #define THERM_THERM_STATE_SHIFT 0
342 /*Register BBCH (0x80) register.RegisterDescription */
343 #define BBCH_BBSEL_MASK 0x06
344 #define BBCH_BBSEL_SHIFT 1
345 #define BBCH_BBCHEN_MASK 0x01
346 #define BBCH_BBCHEN_SHIFT 0
349 /*Register DCDCCTRL (0x80) register.RegisterDescription */
350 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20
351 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5
352 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10
353 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4
354 #define DCDCCTRL_VIO_PSKIP_MASK 0x08
355 #define DCDCCTRL_VIO_PSKIP_SHIFT 3
356 #define DCDCCTRL_DCDCCKEXT_MASK 0x04
357 #define DCDCCTRL_DCDCCKEXT_SHIFT 2
358 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03
359 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0
362 /*Register DEVCTRL (0x80) register.RegisterDescription */
363 #define DEVCTRL_RTC_PWDN_MASK 0x40
364 #define DEVCTRL_RTC_PWDN_SHIFT 6
365 #define DEVCTRL_CK32K_CTRL_MASK 0x20
366 #define DEVCTRL_CK32K_CTRL_SHIFT 5
367 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
368 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
369 #define DEVCTRL_DEV_OFF_RST_MASK 0x08
370 #define DEVCTRL_DEV_OFF_RST_SHIFT 3
371 #define DEVCTRL_DEV_ON_MASK 0x04
372 #define DEVCTRL_DEV_ON_SHIFT 2
373 #define DEVCTRL_DEV_SLP_MASK 0x02
374 #define DEVCTRL_DEV_SLP_SHIFT 1
375 #define DEVCTRL_DEV_OFF_MASK 0x01
376 #define DEVCTRL_DEV_OFF_SHIFT 0
379 /*Register DEVCTRL2 (0x80) register.RegisterDescription */
380 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
381 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
382 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
383 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
384 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04
385 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2
386 #define DEVCTRL2_PWON_LP_RST_MASK 0x02
387 #define DEVCTRL2_PWON_LP_RST_SHIFT 1
388 #define DEVCTRL2_IT_POL_MASK 0x01
389 #define DEVCTRL2_IT_POL_SHIFT 0
392 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
393 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
394 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
395 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
396 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
397 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
398 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
399 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
400 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
401 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
402 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
403 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
404 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
405 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
406 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
407 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
408 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
411 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
412 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
413 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
414 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
415 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
416 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
417 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
418 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
419 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
420 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
421 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
422 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
423 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
424 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
425 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
426 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
427 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
430 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
431 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
432 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
433 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
434 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
435 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
436 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
437 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
438 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
439 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
440 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
441 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
442 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
443 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
444 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
445 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
446 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
449 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
450 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
451 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
452 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
453 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
454 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
455 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
456 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
457 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
458 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
459 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
460 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
461 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
462 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
463 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
466 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
467 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
468 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
469 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
470 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
471 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
472 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
473 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
474 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
475 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
476 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
477 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
478 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
479 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
480 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
481 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
482 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
485 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
486 #define EN1_SMPS_ASS_RSVD_MASK 0xE0
487 #define EN1_SMPS_ASS_RSVD_SHIFT 5
488 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
489 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
490 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
491 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
492 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
493 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
494 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
495 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
496 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
497 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
500 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
501 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
502 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
503 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
504 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
505 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
506 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
507 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
508 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
509 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
510 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
511 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
512 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
513 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
514 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
515 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
516 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
519 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
520 #define EN2_SMPS_ASS_RSVD_MASK 0xE0
521 #define EN2_SMPS_ASS_RSVD_SHIFT 5
522 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
523 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
524 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
525 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
526 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
527 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
528 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
529 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
530 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
531 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
534 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
535 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
536 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
537 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
538 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
539 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
540 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
541 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
542 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
543 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
544 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
545 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
546 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
547 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
548 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
549 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
550 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
553 /*Register SPARE (0x80) register.RegisterDescription */
554 #define SPARE_SPARE_MASK 0xFF
555 #define SPARE_SPARE_SHIFT 0
558 /*Register INT_STS (0x80) register.RegisterDescription */
559 #define INT_STS_RTC_PERIOD_IT_MASK 0x80
560 #define INT_STS_RTC_PERIOD_IT_SHIFT 7
561 #define INT_STS_RTC_ALARM_IT_MASK 0x40
562 #define INT_STS_RTC_ALARM_IT_SHIFT 6
563 #define INT_STS_HOTDIE_IT_MASK 0x20
564 #define INT_STS_HOTDIE_IT_SHIFT 5
565 #define INT_STS_PWRHOLD_IT_MASK 0x10
566 #define INT_STS_PWRHOLD_IT_SHIFT 4
567 #define INT_STS_PWRON_LP_IT_MASK 0x08
568 #define INT_STS_PWRON_LP_IT_SHIFT 3
569 #define INT_STS_PWRON_IT_MASK 0x04
570 #define INT_STS_PWRON_IT_SHIFT 2
571 #define INT_STS_VMBHI_IT_MASK 0x02
572 #define INT_STS_VMBHI_IT_SHIFT 1
573 #define INT_STS_VMBDCH_IT_MASK 0x01
574 #define INT_STS_VMBDCH_IT_SHIFT 0
577 /*Register INT_MSK (0x80) register.RegisterDescription */
578 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
579 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
580 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
581 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
582 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
583 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
584 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
585 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
586 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
587 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
588 #define INT_MSK_PWRON_IT_MSK_MASK 0x04
589 #define INT_MSK_PWRON_IT_MSK_SHIFT 2
590 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02
591 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1
592 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
593 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
596 /*Register INT_STS2 (0x80) register.RegisterDescription */
597 #define INT_STS2_GPIO3_F_IT_MASK 0x80
598 #define INT_STS2_GPIO3_F_IT_SHIFT 7
599 #define INT_STS2_GPIO3_R_IT_MASK 0x40
600 #define INT_STS2_GPIO3_R_IT_SHIFT 6
601 #define INT_STS2_GPIO2_F_IT_MASK 0x20
602 #define INT_STS2_GPIO2_F_IT_SHIFT 5
603 #define INT_STS2_GPIO2_R_IT_MASK 0x10
604 #define INT_STS2_GPIO2_R_IT_SHIFT 4
605 #define INT_STS2_GPIO1_F_IT_MASK 0x08
606 #define INT_STS2_GPIO1_F_IT_SHIFT 3
607 #define INT_STS2_GPIO1_R_IT_MASK 0x04
608 #define INT_STS2_GPIO1_R_IT_SHIFT 2
609 #define INT_STS2_GPIO0_F_IT_MASK 0x02
610 #define INT_STS2_GPIO0_F_IT_SHIFT 1
611 #define INT_STS2_GPIO0_R_IT_MASK 0x01
612 #define INT_STS2_GPIO0_R_IT_SHIFT 0
615 /*Register INT_MSK2 (0x80) register.RegisterDescription */
616 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
617 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
618 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
619 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
620 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
621 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
622 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
623 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
624 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
625 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
626 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
627 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
628 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
629 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
630 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
631 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
634 /*Register INT_STS3 (0x80) register.RegisterDescription */
635 #define INT_STS3_GPIO5_F_IT_MASK 0x08
636 #define INT_STS3_GPIO5_F_IT_SHIFT 3
637 #define INT_STS3_GPIO5_R_IT_MASK 0x04
638 #define INT_STS3_GPIO5_R_IT_SHIFT 2
639 #define INT_STS3_GPIO4_F_IT_MASK 0x02
640 #define INT_STS3_GPIO4_F_IT_SHIFT 1
641 #define INT_STS3_GPIO4_R_IT_MASK 0x01
642 #define INT_STS3_GPIO4_R_IT_SHIFT 0
645 /*Register INT_MSK3 (0x80) register.RegisterDescription */
646 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
647 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
648 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
649 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
650 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
651 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
652 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
653 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
656 /*Register GPIO (0x80) register.RegisterDescription */
657 #define GPIO_DEB_MASK 0x10
658 #define GPIO_DEB_SHIFT 4
659 #define GPIO_PUEN_MASK 0x08
660 #define GPIO_PUEN_SHIFT 3
661 #define GPIO_CFG_MASK 0x04
662 #define GPIO_CFG_SHIFT 2
663 #define GPIO_STS_MASK 0x02
664 #define GPIO_STS_SHIFT 1
665 #define GPIO_SET_MASK 0x01
666 #define GPIO_SET_SHIFT 0
669 /*Register JTAGVERNUM (0x80) register.RegisterDescription */
670 #define JTAGVERNUM_VERNUM_MASK 0x0F
671 #define JTAGVERNUM_VERNUM_SHIFT 0
674 /* Register VDDCTRL (0x27) bit definitions */
675 #define VDDCTRL_ST_MASK 0x03
676 #define VDDCTRL_ST_SHIFT 0
679 /*Register VDDCTRL_OP (0x28) bit definitios */
680 #define VDDCTRL_OP_CMD_MASK 0x80
681 #define VDDCTRL_OP_CMD_SHIFT 7
682 #define VDDCTRL_OP_SEL_MASK 0x7F
683 #define VDDCTRL_OP_SEL_SHIFT 0
686 /*Register VDDCTRL_SR (0x29) bit definitions */
687 #define VDDCTRL_SR_SEL_MASK 0x7F
688 #define VDDCTRL_SR_SEL_SHIFT 0
691 /* IRQ Definitions */
692 #define TPS65910_IRQ_VBAT_VMBDCH 0
693 #define TPS65910_IRQ_VBAT_VMHI 1
694 #define TPS65910_IRQ_PWRON 2
695 #define TPS65910_IRQ_PWRON_LP 3
696 #define TPS65910_IRQ_PWRHOLD 4
697 #define TPS65910_IRQ_HOTDIE 5
698 #define TPS65910_IRQ_RTC_ALARM 6
699 #define TPS65910_IRQ_RTC_PERIOD 7
700 #define TPS65910_IRQ_GPIO_R 8
701 #define TPS65910_IRQ_GPIO_F 9
702 #define TPS65910_NUM_IRQ 10
704 #define TPS65911_IRQ_VBAT_VMBDCH 0
705 #define TPS65911_IRQ_VBAT_VMBDCH2L 1
706 #define TPS65911_IRQ_VBAT_VMBDCH2H 2
707 #define TPS65911_IRQ_VBAT_VMHI 3
708 #define TPS65911_IRQ_PWRON 4
709 #define TPS65911_IRQ_PWRON_LP 5
710 #define TPS65911_IRQ_PWRHOLD_F 6
711 #define TPS65911_IRQ_PWRHOLD_R 7
712 #define TPS65911_IRQ_HOTDIE 8
713 #define TPS65911_IRQ_RTC_ALARM 9
714 #define TPS65911_IRQ_RTC_PERIOD 10
715 #define TPS65911_IRQ_GPIO0_R 11
716 #define TPS65911_IRQ_GPIO0_F 12
717 #define TPS65911_IRQ_GPIO1_R 13
718 #define TPS65911_IRQ_GPIO1_F 14
719 #define TPS65911_IRQ_GPIO2_R 15
720 #define TPS65911_IRQ_GPIO2_F 16
721 #define TPS65911_IRQ_GPIO3_R 17
722 #define TPS65911_IRQ_GPIO3_F 18
723 #define TPS65911_IRQ_GPIO4_R 19
724 #define TPS65911_IRQ_GPIO4_F 20
725 #define TPS65911_IRQ_GPIO5_R 21
726 #define TPS65911_IRQ_GPIO5_F 22
727 #define TPS65911_IRQ_WTCHDG 23
728 #define TPS65911_IRQ_PWRDN 24
730 #define TPS65911_NUM_IRQ 25
733 /* GPIO Register Definitions */
734 #define TPS65910_GPIO_DEB BIT(2)
735 #define TPS65910_GPIO_PUEN BIT(3)
736 #define TPS65910_GPIO_CFG BIT(2)
737 #define TPS65910_GPIO_STS BIT(1)
738 #define TPS65910_GPIO_SET BIT(0)
741 * struct tps65910_board
742 * Board platform data may be used to initialize regulators.
745 struct tps65910_board
{
749 struct regulator_init_data
*tps65910_pmic_init_data
;
753 * struct tps65910 - tps65910 sub-driver chip access routines
758 struct i2c_client
*i2c_client
;
759 struct mutex io_mutex
;
761 int (*read
)(struct tps65910
*tps65910
, u8 reg
, int size
, void *dest
);
762 int (*write
)(struct tps65910
*tps65910
, u8 reg
, int size
, void *src
);
765 struct tps65910_pmic
*pmic
;
766 struct tps65910_rtc
*rtc
;
767 struct tps65910_power
*power
;
770 struct gpio_chip gpio
;
773 struct mutex irq_lock
;
780 struct tps65910_platform_data
{
785 int tps65910_set_bits(struct tps65910
*tps65910
, u8 reg
, u8 mask
);
786 int tps65910_clear_bits(struct tps65910
*tps65910
, u8 reg
, u8 mask
);
787 void tps65910_gpio_init(struct tps65910
*tps65910
, int gpio_base
);
788 int tps65910_irq_init(struct tps65910
*tps65910
, int irq
,
789 struct tps65910_platform_data
*pdata
);
791 static inline int tps65910_chip_id(struct tps65910
*tps65910
)
796 #endif /* __LINUX_MFD_TPS65910_H */
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