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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define DEFAULT_UAR_PAGE_SHIFT 12
48
49 #define MAX_MSIX_P_PORT 17
50 #define MAX_MSIX 64
51 #define MIN_MSIX_P_PORT 5
52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)
54
55 #define MLX4_MAX_100M_UNITS_VAL 255 /*
56 * work around: can't set values
57 * greater then this value when
58 * using 100 Mbps units.
59 */
60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
62 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63
64 #define MLX4_ROCE_MAX_GIDS 128
65 #define MLX4_ROCE_PF_GIDS 16
66
67 enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
74 MLX4_FLAG_BONDED = 1 << 7
75 };
76
77 enum {
78 MLX4_PORT_CAP_IS_SM = 1 << 1,
79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
80 };
81
82 enum {
83 MLX4_MAX_PORTS = 2,
84 MLX4_MAX_PORT_PKEYS = 128,
85 MLX4_MAX_PORT_GIDS = 128
86 };
87
88 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
89 * These qkeys must not be allowed for general use. This is a 64k range,
90 * and to test for violation, we use the mask (protect against future chg).
91 */
92 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
93 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
94
95 enum {
96 MLX4_BOARD_ID_LEN = 64
97 };
98
99 enum {
100 MLX4_MAX_NUM_PF = 16,
101 MLX4_MAX_NUM_VF = 126,
102 MLX4_MAX_NUM_VF_P_PORT = 64,
103 MLX4_MFUNC_MAX = 128,
104 MLX4_MAX_EQ_NUM = 1024,
105 MLX4_MFUNC_EQ_NUM = 4,
106 MLX4_MFUNC_MAX_EQES = 8,
107 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
108 };
109
110 /* Driver supports 3 diffrent device methods to manage traffic steering:
111 * -device managed - High level API for ib and eth flow steering. FW is
112 * managing flow steering tables.
113 * - B0 steering mode - Common low level API for ib and (if supported) eth.
114 * - A0 steering mode - Limited low level API for eth. In case of IB,
115 * B0 mode is in use.
116 */
117 enum {
118 MLX4_STEERING_MODE_A0,
119 MLX4_STEERING_MODE_B0,
120 MLX4_STEERING_MODE_DEVICE_MANAGED
121 };
122
123 enum {
124 MLX4_STEERING_DMFS_A0_DEFAULT,
125 MLX4_STEERING_DMFS_A0_DYNAMIC,
126 MLX4_STEERING_DMFS_A0_STATIC,
127 MLX4_STEERING_DMFS_A0_DISABLE,
128 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
129 };
130
131 static inline const char *mlx4_steering_mode_str(int steering_mode)
132 {
133 switch (steering_mode) {
134 case MLX4_STEERING_MODE_A0:
135 return "A0 steering";
136
137 case MLX4_STEERING_MODE_B0:
138 return "B0 steering";
139
140 case MLX4_STEERING_MODE_DEVICE_MANAGED:
141 return "Device managed flow steering";
142
143 default:
144 return "Unrecognize steering mode";
145 }
146 }
147
148 enum {
149 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
150 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
151 };
152
153 enum {
154 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
155 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
156 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
157 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
158 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
159 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
160 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
161 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
162 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
163 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
164 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
165 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
166 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
167 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
168 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
169 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
170 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
171 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
172 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
173 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
174 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
175 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
176 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
177 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
178 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
179 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
180 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
181 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
185 };
186
187 enum {
188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
192 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
193 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
194 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
195 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
196 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
197 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
198 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
199 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
200 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
201 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
202 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
203 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
204 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
205 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
207 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
208 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
209 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
210 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
211 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
212 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
213 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
214 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
215 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
216 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
217 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
218 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
219 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
220 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
221 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
222 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
223 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
224 };
225
226 enum {
227 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
228 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
229 };
230
231 enum {
232 MLX4_VF_CAP_FLAG_RESET = 1 << 0
233 };
234
235 /* bit enums for an 8-bit flags field indicating special use
236 * QPs which require special handling in qp_reserve_range.
237 * Currently, this only includes QPs used by the ETH interface,
238 * where we expect to use blueflame. These QPs must not have
239 * bits 6 and 7 set in their qp number.
240 *
241 * This enum may use only bits 0..7.
242 */
243 enum {
244 MLX4_RESERVE_A0_QP = 1 << 6,
245 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
246 };
247
248 enum {
249 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
250 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
251 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
252 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
253 };
254
255 enum {
256 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
257 };
258
259 enum {
260 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
261 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
262 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
263 };
264
265
266 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
267
268 enum {
269 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
270 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
271 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
272 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
273 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
274 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
275 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
276 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
277 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
278 };
279
280 enum {
281 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
282 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
283 };
284
285 enum mlx4_event {
286 MLX4_EVENT_TYPE_COMP = 0x00,
287 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
288 MLX4_EVENT_TYPE_COMM_EST = 0x02,
289 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
290 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
291 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
292 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
293 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
294 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
295 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
296 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
297 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
298 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
299 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
300 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
301 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
302 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
303 MLX4_EVENT_TYPE_CMD = 0x0a,
304 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
305 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
306 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
307 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
308 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
309 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
310 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
311 MLX4_EVENT_TYPE_NONE = 0xff,
312 };
313
314 enum {
315 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
316 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
317 };
318
319 enum {
320 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
321 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
322 };
323
324 enum {
325 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
326 };
327
328 enum slave_port_state {
329 SLAVE_PORT_DOWN = 0,
330 SLAVE_PENDING_UP,
331 SLAVE_PORT_UP,
332 };
333
334 enum slave_port_gen_event {
335 SLAVE_PORT_GEN_EVENT_DOWN = 0,
336 SLAVE_PORT_GEN_EVENT_UP,
337 SLAVE_PORT_GEN_EVENT_NONE,
338 };
339
340 enum slave_port_state_event {
341 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
342 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
343 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
344 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
345 };
346
347 enum {
348 MLX4_PERM_LOCAL_READ = 1 << 10,
349 MLX4_PERM_LOCAL_WRITE = 1 << 11,
350 MLX4_PERM_REMOTE_READ = 1 << 12,
351 MLX4_PERM_REMOTE_WRITE = 1 << 13,
352 MLX4_PERM_ATOMIC = 1 << 14,
353 MLX4_PERM_BIND_MW = 1 << 15,
354 MLX4_PERM_MASK = 0xFC00
355 };
356
357 enum {
358 MLX4_OPCODE_NOP = 0x00,
359 MLX4_OPCODE_SEND_INVAL = 0x01,
360 MLX4_OPCODE_RDMA_WRITE = 0x08,
361 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
362 MLX4_OPCODE_SEND = 0x0a,
363 MLX4_OPCODE_SEND_IMM = 0x0b,
364 MLX4_OPCODE_LSO = 0x0e,
365 MLX4_OPCODE_RDMA_READ = 0x10,
366 MLX4_OPCODE_ATOMIC_CS = 0x11,
367 MLX4_OPCODE_ATOMIC_FA = 0x12,
368 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
369 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
370 MLX4_OPCODE_BIND_MW = 0x18,
371 MLX4_OPCODE_FMR = 0x19,
372 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
373 MLX4_OPCODE_CONFIG_CMD = 0x1f,
374
375 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
376 MLX4_RECV_OPCODE_SEND = 0x01,
377 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
378 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
379
380 MLX4_CQE_OPCODE_ERROR = 0x1e,
381 MLX4_CQE_OPCODE_RESIZE = 0x16,
382 };
383
384 enum {
385 MLX4_STAT_RATE_OFFSET = 5
386 };
387
388 enum mlx4_protocol {
389 MLX4_PROT_IB_IPV6 = 0,
390 MLX4_PROT_ETH,
391 MLX4_PROT_IB_IPV4,
392 MLX4_PROT_FCOE
393 };
394
395 enum {
396 MLX4_MTT_FLAG_PRESENT = 1
397 };
398
399 enum mlx4_qp_region {
400 MLX4_QP_REGION_FW = 0,
401 MLX4_QP_REGION_RSS_RAW_ETH,
402 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
403 MLX4_QP_REGION_ETH_ADDR,
404 MLX4_QP_REGION_FC_ADDR,
405 MLX4_QP_REGION_FC_EXCH,
406 MLX4_NUM_QP_REGION
407 };
408
409 enum mlx4_port_type {
410 MLX4_PORT_TYPE_NONE = 0,
411 MLX4_PORT_TYPE_IB = 1,
412 MLX4_PORT_TYPE_ETH = 2,
413 MLX4_PORT_TYPE_AUTO = 3
414 };
415
416 enum mlx4_special_vlan_idx {
417 MLX4_NO_VLAN_IDX = 0,
418 MLX4_VLAN_MISS_IDX,
419 MLX4_VLAN_REGULAR
420 };
421
422 enum mlx4_steer_type {
423 MLX4_MC_STEER = 0,
424 MLX4_UC_STEER,
425 MLX4_NUM_STEERS
426 };
427
428 enum {
429 MLX4_NUM_FEXCH = 64 * 1024,
430 };
431
432 enum {
433 MLX4_MAX_FAST_REG_PAGES = 511,
434 };
435
436 enum {
437 /*
438 * Max wqe size for rdma read is 512 bytes, so this
439 * limits our max_sge_rd as the wqe needs to fit:
440 * - ctrl segment (16 bytes)
441 * - rdma segment (16 bytes)
442 * - scatter elements (16 bytes each)
443 */
444 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
445 };
446
447 enum {
448 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
449 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
450 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
451 };
452
453 /* Port mgmt change event handling */
454 enum {
455 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
456 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
457 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
458 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
459 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
460 };
461
462 enum {
463 MLX4_DEVICE_STATE_UP = 1 << 0,
464 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
465 };
466
467 enum {
468 MLX4_INTERFACE_STATE_UP = 1 << 0,
469 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
470 MLX4_INTERFACE_STATE_SHUTDOWN = 1 << 2,
471 };
472
473 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
474 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
475
476 enum mlx4_module_id {
477 MLX4_MODULE_ID_SFP = 0x3,
478 MLX4_MODULE_ID_QSFP = 0xC,
479 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
480 MLX4_MODULE_ID_QSFP28 = 0x11,
481 };
482
483 enum { /* rl */
484 MLX4_QP_RATE_LIMIT_NONE = 0,
485 MLX4_QP_RATE_LIMIT_KBS = 1,
486 MLX4_QP_RATE_LIMIT_MBS = 2,
487 MLX4_QP_RATE_LIMIT_GBS = 3
488 };
489
490 struct mlx4_rate_limit_caps {
491 u16 num_rates; /* Number of different rates */
492 u8 min_unit;
493 u16 min_val;
494 u8 max_unit;
495 u16 max_val;
496 };
497
498 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
499 {
500 return (major << 32) | (minor << 16) | subminor;
501 }
502
503 struct mlx4_phys_caps {
504 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
505 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
506 u32 num_phys_eqs;
507 u32 base_sqpn;
508 u32 base_proxy_sqpn;
509 u32 base_tunnel_sqpn;
510 };
511
512 struct mlx4_caps {
513 u64 fw_ver;
514 u32 function;
515 int num_ports;
516 int vl_cap[MLX4_MAX_PORTS + 1];
517 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
518 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
519 u64 def_mac[MLX4_MAX_PORTS + 1];
520 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
521 int gid_table_len[MLX4_MAX_PORTS + 1];
522 int pkey_table_len[MLX4_MAX_PORTS + 1];
523 int trans_type[MLX4_MAX_PORTS + 1];
524 int vendor_oui[MLX4_MAX_PORTS + 1];
525 int wavelength[MLX4_MAX_PORTS + 1];
526 u64 trans_code[MLX4_MAX_PORTS + 1];
527 int local_ca_ack_delay;
528 int num_uars;
529 u32 uar_page_size;
530 int bf_reg_size;
531 int bf_regs_per_page;
532 int max_sq_sg;
533 int max_rq_sg;
534 int num_qps;
535 int max_wqes;
536 int max_sq_desc_sz;
537 int max_rq_desc_sz;
538 int max_qp_init_rdma;
539 int max_qp_dest_rdma;
540 int max_tc_eth;
541 u32 *qp0_qkey;
542 u32 *qp0_proxy;
543 u32 *qp1_proxy;
544 u32 *qp0_tunnel;
545 u32 *qp1_tunnel;
546 int num_srqs;
547 int max_srq_wqes;
548 int max_srq_sge;
549 int reserved_srqs;
550 int num_cqs;
551 int max_cqes;
552 int reserved_cqs;
553 int num_sys_eqs;
554 int num_eqs;
555 int reserved_eqs;
556 int num_comp_vectors;
557 int num_mpts;
558 int max_fmr_maps;
559 int num_mtts;
560 int fmr_reserved_mtts;
561 int reserved_mtts;
562 int reserved_mrws;
563 int reserved_uars;
564 int num_mgms;
565 int num_amgms;
566 int reserved_mcgs;
567 int num_qp_per_mgm;
568 int steering_mode;
569 int dmfs_high_steer_mode;
570 int fs_log_max_ucast_qp_range_size;
571 int num_pds;
572 int reserved_pds;
573 int max_xrcds;
574 int reserved_xrcds;
575 int mtt_entry_sz;
576 u32 max_msg_sz;
577 u32 page_size_cap;
578 u64 flags;
579 u64 flags2;
580 u32 bmme_flags;
581 u32 reserved_lkey;
582 u16 stat_rate_support;
583 u8 port_width_cap[MLX4_MAX_PORTS + 1];
584 int max_gso_sz;
585 int max_rss_tbl_sz;
586 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
587 int reserved_qps;
588 int reserved_qps_base[MLX4_NUM_QP_REGION];
589 int log_num_macs;
590 int log_num_vlans;
591 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
592 u8 supported_type[MLX4_MAX_PORTS + 1];
593 u8 suggested_type[MLX4_MAX_PORTS + 1];
594 u8 default_sense[MLX4_MAX_PORTS + 1];
595 u32 port_mask[MLX4_MAX_PORTS + 1];
596 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
597 u32 max_counters;
598 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
599 u16 sqp_demux;
600 u32 eqe_size;
601 u32 cqe_size;
602 u8 eqe_factor;
603 u32 userspace_caps; /* userspace must be aware of these */
604 u32 function_caps; /* VFs must be aware of these */
605 u16 hca_core_clock;
606 u64 phys_port_id[MLX4_MAX_PORTS + 1];
607 int tunnel_offload_mode;
608 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
609 u8 phv_bit[MLX4_MAX_PORTS + 1];
610 u8 alloc_res_qp_mask;
611 u32 dmfs_high_rate_qpn_base;
612 u32 dmfs_high_rate_qpn_range;
613 u32 vf_caps;
614 struct mlx4_rate_limit_caps rl_caps;
615 };
616
617 struct mlx4_buf_list {
618 void *buf;
619 dma_addr_t map;
620 };
621
622 struct mlx4_buf {
623 struct mlx4_buf_list direct;
624 struct mlx4_buf_list *page_list;
625 int nbufs;
626 int npages;
627 int page_shift;
628 };
629
630 struct mlx4_mtt {
631 u32 offset;
632 int order;
633 int page_shift;
634 };
635
636 enum {
637 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
638 };
639
640 struct mlx4_db_pgdir {
641 struct list_head list;
642 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
643 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
644 unsigned long *bits[2];
645 __be32 *db_page;
646 dma_addr_t db_dma;
647 };
648
649 struct mlx4_ib_user_db_page;
650
651 struct mlx4_db {
652 __be32 *db;
653 union {
654 struct mlx4_db_pgdir *pgdir;
655 struct mlx4_ib_user_db_page *user_page;
656 } u;
657 dma_addr_t dma;
658 int index;
659 int order;
660 };
661
662 struct mlx4_hwq_resources {
663 struct mlx4_db db;
664 struct mlx4_mtt mtt;
665 struct mlx4_buf buf;
666 };
667
668 struct mlx4_mr {
669 struct mlx4_mtt mtt;
670 u64 iova;
671 u64 size;
672 u32 key;
673 u32 pd;
674 u32 access;
675 int enabled;
676 };
677
678 enum mlx4_mw_type {
679 MLX4_MW_TYPE_1 = 1,
680 MLX4_MW_TYPE_2 = 2,
681 };
682
683 struct mlx4_mw {
684 u32 key;
685 u32 pd;
686 enum mlx4_mw_type type;
687 int enabled;
688 };
689
690 struct mlx4_fmr {
691 struct mlx4_mr mr;
692 struct mlx4_mpt_entry *mpt;
693 __be64 *mtts;
694 dma_addr_t dma_handle;
695 int max_pages;
696 int max_maps;
697 int maps;
698 u8 page_shift;
699 };
700
701 struct mlx4_uar {
702 unsigned long pfn;
703 int index;
704 struct list_head bf_list;
705 unsigned free_bf_bmap;
706 void __iomem *map;
707 void __iomem *bf_map;
708 };
709
710 struct mlx4_bf {
711 unsigned int offset;
712 int buf_size;
713 struct mlx4_uar *uar;
714 void __iomem *reg;
715 };
716
717 struct mlx4_cq {
718 void (*comp) (struct mlx4_cq *);
719 void (*event) (struct mlx4_cq *, enum mlx4_event);
720
721 struct mlx4_uar *uar;
722
723 u32 cons_index;
724
725 u16 irq;
726 __be32 *set_ci_db;
727 __be32 *arm_db;
728 int arm_sn;
729
730 int cqn;
731 unsigned vector;
732
733 atomic_t refcount;
734 struct completion free;
735 struct {
736 struct list_head list;
737 void (*comp)(struct mlx4_cq *);
738 void *priv;
739 } tasklet_ctx;
740 int reset_notify_added;
741 struct list_head reset_notify;
742 };
743
744 struct mlx4_qp {
745 void (*event) (struct mlx4_qp *, enum mlx4_event);
746
747 int qpn;
748
749 atomic_t refcount;
750 struct completion free;
751 };
752
753 struct mlx4_srq {
754 void (*event) (struct mlx4_srq *, enum mlx4_event);
755
756 int srqn;
757 int max;
758 int max_gs;
759 int wqe_shift;
760
761 atomic_t refcount;
762 struct completion free;
763 };
764
765 struct mlx4_av {
766 __be32 port_pd;
767 u8 reserved1;
768 u8 g_slid;
769 __be16 dlid;
770 u8 reserved2;
771 u8 gid_index;
772 u8 stat_rate;
773 u8 hop_limit;
774 __be32 sl_tclass_flowlabel;
775 u8 dgid[16];
776 };
777
778 struct mlx4_eth_av {
779 __be32 port_pd;
780 u8 reserved1;
781 u8 smac_idx;
782 u16 reserved2;
783 u8 reserved3;
784 u8 gid_index;
785 u8 stat_rate;
786 u8 hop_limit;
787 __be32 sl_tclass_flowlabel;
788 u8 dgid[16];
789 u8 s_mac[6];
790 u8 reserved4[2];
791 __be16 vlan;
792 u8 mac[ETH_ALEN];
793 };
794
795 union mlx4_ext_av {
796 struct mlx4_av ib;
797 struct mlx4_eth_av eth;
798 };
799
800 /* Counters should be saturate once they reach their maximum value */
801 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
802 if ((value) > U32_MAX) \
803 counter = cpu_to_be32(U32_MAX); \
804 else \
805 counter = cpu_to_be32(value); \
806 } while (0)
807
808 struct mlx4_counter {
809 u8 reserved1[3];
810 u8 counter_mode;
811 __be32 num_ifc;
812 u32 reserved2[2];
813 __be64 rx_frames;
814 __be64 rx_bytes;
815 __be64 tx_frames;
816 __be64 tx_bytes;
817 };
818
819 struct mlx4_quotas {
820 int qp;
821 int cq;
822 int srq;
823 int mpt;
824 int mtt;
825 int counter;
826 int xrcd;
827 };
828
829 struct mlx4_vf_dev {
830 u8 min_port;
831 u8 n_ports;
832 };
833
834 enum mlx4_pci_status {
835 MLX4_PCI_STATUS_DISABLED,
836 MLX4_PCI_STATUS_ENABLED,
837 };
838
839 struct mlx4_dev_persistent {
840 struct pci_dev *pdev;
841 struct mlx4_dev *dev;
842 int nvfs[MLX4_MAX_PORTS + 1];
843 int num_vfs;
844 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
845 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
846 struct work_struct catas_work;
847 struct workqueue_struct *catas_wq;
848 struct mutex device_state_mutex; /* protect HW state */
849 u8 state;
850 struct mutex interface_state_mutex; /* protect SW state */
851 u8 interface_state;
852 struct mutex pci_status_mutex; /* sync pci state */
853 enum mlx4_pci_status pci_status;
854 };
855
856 struct mlx4_dev {
857 struct mlx4_dev_persistent *persist;
858 unsigned long flags;
859 unsigned long num_slaves;
860 struct mlx4_caps caps;
861 struct mlx4_phys_caps phys_caps;
862 struct mlx4_quotas quotas;
863 struct radix_tree_root qp_table_tree;
864 u8 rev_id;
865 u8 port_random_macs;
866 char board_id[MLX4_BOARD_ID_LEN];
867 int numa_node;
868 int oper_log_mgm_entry_size;
869 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
870 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
871 struct mlx4_vf_dev *dev_vfs;
872 u8 uar_page_shift;
873 };
874
875 struct mlx4_clock_params {
876 u64 offset;
877 u8 bar;
878 u8 size;
879 };
880
881 struct mlx4_eqe {
882 u8 reserved1;
883 u8 type;
884 u8 reserved2;
885 u8 subtype;
886 union {
887 u32 raw[6];
888 struct {
889 __be32 cqn;
890 } __packed comp;
891 struct {
892 u16 reserved1;
893 __be16 token;
894 u32 reserved2;
895 u8 reserved3[3];
896 u8 status;
897 __be64 out_param;
898 } __packed cmd;
899 struct {
900 __be32 qpn;
901 } __packed qp;
902 struct {
903 __be32 srqn;
904 } __packed srq;
905 struct {
906 __be32 cqn;
907 u32 reserved1;
908 u8 reserved2[3];
909 u8 syndrome;
910 } __packed cq_err;
911 struct {
912 u32 reserved1[2];
913 __be32 port;
914 } __packed port_change;
915 struct {
916 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
917 u32 reserved;
918 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
919 } __packed comm_channel_arm;
920 struct {
921 u8 port;
922 u8 reserved[3];
923 __be64 mac;
924 } __packed mac_update;
925 struct {
926 __be32 slave_id;
927 } __packed flr_event;
928 struct {
929 __be16 current_temperature;
930 __be16 warning_threshold;
931 } __packed warming;
932 struct {
933 u8 reserved[3];
934 u8 port;
935 union {
936 struct {
937 __be16 mstr_sm_lid;
938 __be16 port_lid;
939 __be32 changed_attr;
940 u8 reserved[3];
941 u8 mstr_sm_sl;
942 __be64 gid_prefix;
943 } __packed port_info;
944 struct {
945 __be32 block_ptr;
946 __be32 tbl_entries_mask;
947 } __packed tbl_change_info;
948 } params;
949 } __packed port_mgmt_change;
950 struct {
951 u8 reserved[3];
952 u8 port;
953 u32 reserved1[5];
954 } __packed bad_cable;
955 } event;
956 u8 slave_id;
957 u8 reserved3[2];
958 u8 owner;
959 } __packed;
960
961 struct mlx4_init_port_param {
962 int set_guid0;
963 int set_node_guid;
964 int set_si_guid;
965 u16 mtu;
966 int port_width_cap;
967 u16 vl_cap;
968 u16 max_gid;
969 u16 max_pkey;
970 u64 guid0;
971 u64 node_guid;
972 u64 si_guid;
973 };
974
975 #define MAD_IFC_DATA_SZ 192
976 /* MAD IFC Mailbox */
977 struct mlx4_mad_ifc {
978 u8 base_version;
979 u8 mgmt_class;
980 u8 class_version;
981 u8 method;
982 __be16 status;
983 __be16 class_specific;
984 __be64 tid;
985 __be16 attr_id;
986 __be16 resv;
987 __be32 attr_mod;
988 __be64 mkey;
989 __be16 dr_slid;
990 __be16 dr_dlid;
991 u8 reserved[28];
992 u8 data[MAD_IFC_DATA_SZ];
993 } __packed;
994
995 #define mlx4_foreach_port(port, dev, type) \
996 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
997 if ((type) == (dev)->caps.port_mask[(port)])
998
999 #define mlx4_foreach_ib_transport_port(port, dev) \
1000 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1001 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1002 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \
1003 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2))
1004
1005 #define MLX4_INVALID_SLAVE_ID 0xFF
1006 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1007
1008 void handle_port_mgmt_change_event(struct work_struct *work);
1009
1010 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1011 {
1012 return dev->caps.function;
1013 }
1014
1015 static inline int mlx4_is_master(struct mlx4_dev *dev)
1016 {
1017 return dev->flags & MLX4_FLAG_MASTER;
1018 }
1019
1020 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1021 {
1022 return dev->phys_caps.base_sqpn + 8 +
1023 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1024 }
1025
1026 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1027 {
1028 return (qpn < dev->phys_caps.base_sqpn + 8 +
1029 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1030 qpn >= dev->phys_caps.base_sqpn) ||
1031 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1032 }
1033
1034 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1035 {
1036 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1037
1038 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1039 return 1;
1040
1041 return 0;
1042 }
1043
1044 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1045 {
1046 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1047 }
1048
1049 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1050 {
1051 return dev->flags & MLX4_FLAG_SLAVE;
1052 }
1053
1054 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1055 {
1056 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1057 }
1058
1059 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1060 struct mlx4_buf *buf, gfp_t gfp);
1061 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1062 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1063 {
1064 if (buf->nbufs == 1)
1065 return buf->direct.buf + offset;
1066 else
1067 return buf->page_list[offset >> PAGE_SHIFT].buf +
1068 (offset & (PAGE_SIZE - 1));
1069 }
1070
1071 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1072 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1073 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1074 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1075
1076 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1077 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1078 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1079 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1080
1081 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1082 struct mlx4_mtt *mtt);
1083 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1084 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1085
1086 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1087 int npages, int page_shift, struct mlx4_mr *mr);
1088 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1089 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1090 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1091 struct mlx4_mw *mw);
1092 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1093 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1094 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1095 int start_index, int npages, u64 *page_list);
1096 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1097 struct mlx4_buf *buf, gfp_t gfp);
1098
1099 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1100 gfp_t gfp);
1101 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1102
1103 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1104 int size);
1105 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1106 int size);
1107
1108 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1109 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1110 unsigned vector, int collapsed, int timestamp_en);
1111 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1112 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1113 int *base, u8 flags);
1114 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1115
1116 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1117 gfp_t gfp);
1118 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1119
1120 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1121 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1122 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1123 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1124 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1125
1126 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1127 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1128
1129 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1130 int block_mcast_loopback, enum mlx4_protocol prot);
1131 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1132 enum mlx4_protocol prot);
1133 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1134 u8 port, int block_mcast_loopback,
1135 enum mlx4_protocol protocol, u64 *reg_id);
1136 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1137 enum mlx4_protocol protocol, u64 reg_id);
1138
1139 enum {
1140 MLX4_DOMAIN_UVERBS = 0x1000,
1141 MLX4_DOMAIN_ETHTOOL = 0x2000,
1142 MLX4_DOMAIN_RFS = 0x3000,
1143 MLX4_DOMAIN_NIC = 0x5000,
1144 };
1145
1146 enum mlx4_net_trans_rule_id {
1147 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1148 MLX4_NET_TRANS_RULE_ID_IB,
1149 MLX4_NET_TRANS_RULE_ID_IPV6,
1150 MLX4_NET_TRANS_RULE_ID_IPV4,
1151 MLX4_NET_TRANS_RULE_ID_TCP,
1152 MLX4_NET_TRANS_RULE_ID_UDP,
1153 MLX4_NET_TRANS_RULE_ID_VXLAN,
1154 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1155 };
1156
1157 extern const u16 __sw_id_hw[];
1158
1159 static inline int map_hw_to_sw_id(u16 header_id)
1160 {
1161
1162 int i;
1163 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1164 if (header_id == __sw_id_hw[i])
1165 return i;
1166 }
1167 return -EINVAL;
1168 }
1169
1170 enum mlx4_net_trans_promisc_mode {
1171 MLX4_FS_REGULAR = 1,
1172 MLX4_FS_ALL_DEFAULT,
1173 MLX4_FS_MC_DEFAULT,
1174 MLX4_FS_MIRROR_RX_PORT,
1175 MLX4_FS_MIRROR_SX_PORT,
1176 MLX4_FS_UC_SNIFFER,
1177 MLX4_FS_MC_SNIFFER,
1178 MLX4_FS_MODE_NUM, /* should be last */
1179 };
1180
1181 struct mlx4_spec_eth {
1182 u8 dst_mac[ETH_ALEN];
1183 u8 dst_mac_msk[ETH_ALEN];
1184 u8 src_mac[ETH_ALEN];
1185 u8 src_mac_msk[ETH_ALEN];
1186 u8 ether_type_enable;
1187 __be16 ether_type;
1188 __be16 vlan_id_msk;
1189 __be16 vlan_id;
1190 };
1191
1192 struct mlx4_spec_tcp_udp {
1193 __be16 dst_port;
1194 __be16 dst_port_msk;
1195 __be16 src_port;
1196 __be16 src_port_msk;
1197 };
1198
1199 struct mlx4_spec_ipv4 {
1200 __be32 dst_ip;
1201 __be32 dst_ip_msk;
1202 __be32 src_ip;
1203 __be32 src_ip_msk;
1204 };
1205
1206 struct mlx4_spec_ib {
1207 __be32 l3_qpn;
1208 __be32 qpn_msk;
1209 u8 dst_gid[16];
1210 u8 dst_gid_msk[16];
1211 };
1212
1213 struct mlx4_spec_vxlan {
1214 __be32 vni;
1215 __be32 vni_mask;
1216
1217 };
1218
1219 struct mlx4_spec_list {
1220 struct list_head list;
1221 enum mlx4_net_trans_rule_id id;
1222 union {
1223 struct mlx4_spec_eth eth;
1224 struct mlx4_spec_ib ib;
1225 struct mlx4_spec_ipv4 ipv4;
1226 struct mlx4_spec_tcp_udp tcp_udp;
1227 struct mlx4_spec_vxlan vxlan;
1228 };
1229 };
1230
1231 enum mlx4_net_trans_hw_rule_queue {
1232 MLX4_NET_TRANS_Q_FIFO,
1233 MLX4_NET_TRANS_Q_LIFO,
1234 };
1235
1236 struct mlx4_net_trans_rule {
1237 struct list_head list;
1238 enum mlx4_net_trans_hw_rule_queue queue_mode;
1239 bool exclusive;
1240 bool allow_loopback;
1241 enum mlx4_net_trans_promisc_mode promisc_mode;
1242 u8 port;
1243 u16 priority;
1244 u32 qpn;
1245 };
1246
1247 struct mlx4_net_trans_rule_hw_ctrl {
1248 __be16 prio;
1249 u8 type;
1250 u8 flags;
1251 u8 rsvd1;
1252 u8 funcid;
1253 u8 vep;
1254 u8 port;
1255 __be32 qpn;
1256 __be32 rsvd2;
1257 };
1258
1259 struct mlx4_net_trans_rule_hw_ib {
1260 u8 size;
1261 u8 rsvd1;
1262 __be16 id;
1263 u32 rsvd2;
1264 __be32 l3_qpn;
1265 __be32 qpn_mask;
1266 u8 dst_gid[16];
1267 u8 dst_gid_msk[16];
1268 } __packed;
1269
1270 struct mlx4_net_trans_rule_hw_eth {
1271 u8 size;
1272 u8 rsvd;
1273 __be16 id;
1274 u8 rsvd1[6];
1275 u8 dst_mac[6];
1276 u16 rsvd2;
1277 u8 dst_mac_msk[6];
1278 u16 rsvd3;
1279 u8 src_mac[6];
1280 u16 rsvd4;
1281 u8 src_mac_msk[6];
1282 u8 rsvd5;
1283 u8 ether_type_enable;
1284 __be16 ether_type;
1285 __be16 vlan_tag_msk;
1286 __be16 vlan_tag;
1287 } __packed;
1288
1289 struct mlx4_net_trans_rule_hw_tcp_udp {
1290 u8 size;
1291 u8 rsvd;
1292 __be16 id;
1293 __be16 rsvd1[3];
1294 __be16 dst_port;
1295 __be16 rsvd2;
1296 __be16 dst_port_msk;
1297 __be16 rsvd3;
1298 __be16 src_port;
1299 __be16 rsvd4;
1300 __be16 src_port_msk;
1301 } __packed;
1302
1303 struct mlx4_net_trans_rule_hw_ipv4 {
1304 u8 size;
1305 u8 rsvd;
1306 __be16 id;
1307 __be32 rsvd1;
1308 __be32 dst_ip;
1309 __be32 dst_ip_msk;
1310 __be32 src_ip;
1311 __be32 src_ip_msk;
1312 } __packed;
1313
1314 struct mlx4_net_trans_rule_hw_vxlan {
1315 u8 size;
1316 u8 rsvd;
1317 __be16 id;
1318 __be32 rsvd1;
1319 __be32 vni;
1320 __be32 vni_mask;
1321 } __packed;
1322
1323 struct _rule_hw {
1324 union {
1325 struct {
1326 u8 size;
1327 u8 rsvd;
1328 __be16 id;
1329 };
1330 struct mlx4_net_trans_rule_hw_eth eth;
1331 struct mlx4_net_trans_rule_hw_ib ib;
1332 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1333 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1334 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1335 };
1336 };
1337
1338 enum {
1339 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1340 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1341 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1342 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1343 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1344 };
1345
1346 enum {
1347 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1348 };
1349
1350 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1351 enum mlx4_net_trans_promisc_mode mode);
1352 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1353 enum mlx4_net_trans_promisc_mode mode);
1354 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1355 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1356 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1357 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1358 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1359
1360 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1361 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1362 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1363 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1364 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1365 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1366 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1367 u8 promisc);
1368 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1369 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1370 u8 ignore_fcs_value);
1371 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1372 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1373 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1374 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1375 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1376 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1377 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1378
1379 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1380 int npages, u64 iova, u32 *lkey, u32 *rkey);
1381 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1382 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1383 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1384 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1385 u32 *lkey, u32 *rkey);
1386 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1387 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1388 int mlx4_test_interrupts(struct mlx4_dev *dev);
1389 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1390 const u32 offset[], u32 value[],
1391 size_t array_len, u8 port);
1392 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1393 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1394 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1395 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1396 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1397
1398 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1399 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1400
1401 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1402 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1403 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1404
1405 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1406 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1407 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1408
1409 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1410 int port);
1411 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1412 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1413 int mlx4_flow_attach(struct mlx4_dev *dev,
1414 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1415 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1416 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1417 enum mlx4_net_trans_promisc_mode flow_type);
1418 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1419 enum mlx4_net_trans_rule_id id);
1420 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1421
1422 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1423 int port, int qpn, u16 prio, u64 *reg_id);
1424
1425 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1426 int i, int val);
1427
1428 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1429
1430 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1431 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1432 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1433 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1434 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1435 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1436 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1437
1438 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1439 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1440
1441 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1442 int *slave_id);
1443 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1444 u8 *gid);
1445
1446 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1447 u32 max_range_qpn);
1448
1449 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1450
1451 struct mlx4_active_ports {
1452 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1453 };
1454 /* Returns a bitmap of the physical ports which are assigned to slave */
1455 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1456
1457 /* Returns the physical port that represents the virtual port of the slave, */
1458 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1459 /* mapping is returned. */
1460 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1461
1462 struct mlx4_slaves_pport {
1463 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1464 };
1465 /* Returns a bitmap of all slaves that are assigned to port. */
1466 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1467 int port);
1468
1469 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1470 /* the ports that are set in crit_ports. */
1471 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1472 struct mlx4_dev *dev,
1473 const struct mlx4_active_ports *crit_ports);
1474
1475 /* Returns the slave's virtual port that represents the physical port. */
1476 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1477
1478 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1479
1480 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1481 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1482 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1483 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1484 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1485 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1486 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1487 int enable);
1488 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1489 struct mlx4_mpt_entry ***mpt_entry);
1490 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1491 struct mlx4_mpt_entry **mpt_entry);
1492 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1493 u32 pdn);
1494 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1495 struct mlx4_mpt_entry *mpt_entry,
1496 u32 access);
1497 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1498 struct mlx4_mpt_entry **mpt_entry);
1499 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1500 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1501 u64 iova, u64 size, int npages,
1502 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1503
1504 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1505 u16 offset, u16 size, u8 *data);
1506 int mlx4_max_tc(struct mlx4_dev *dev);
1507
1508 /* Returns true if running in low memory profile (kdump kernel) */
1509 static inline bool mlx4_low_memory_profile(void)
1510 {
1511 return is_kdump_kernel();
1512 }
1513
1514 /* ACCESS REG commands */
1515 enum mlx4_access_reg_method {
1516 MLX4_ACCESS_REG_QUERY = 0x1,
1517 MLX4_ACCESS_REG_WRITE = 0x2,
1518 };
1519
1520 /* ACCESS PTYS Reg command */
1521 enum mlx4_ptys_proto {
1522 MLX4_PTYS_IB = 1<<0,
1523 MLX4_PTYS_EN = 1<<2,
1524 };
1525
1526 struct mlx4_ptys_reg {
1527 u8 resrvd1;
1528 u8 local_port;
1529 u8 resrvd2;
1530 u8 proto_mask;
1531 __be32 resrvd3[2];
1532 __be32 eth_proto_cap;
1533 __be16 ib_width_cap;
1534 __be16 ib_speed_cap;
1535 __be32 resrvd4;
1536 __be32 eth_proto_admin;
1537 __be16 ib_width_admin;
1538 __be16 ib_speed_admin;
1539 __be32 resrvd5;
1540 __be32 eth_proto_oper;
1541 __be16 ib_width_oper;
1542 __be16 ib_speed_oper;
1543 __be32 resrvd6;
1544 __be32 eth_proto_lp_adv;
1545 } __packed;
1546
1547 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1548 enum mlx4_access_reg_method method,
1549 struct mlx4_ptys_reg *ptys_reg);
1550
1551 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1552 struct mlx4_clock_params *params);
1553
1554 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1555 {
1556 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1557 }
1558
1559 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1560 {
1561 /* The first 128 UARs are used for EQ doorbells */
1562 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1563 }
1564 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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