2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
41 #include <linux/atomic.h>
43 #define MAX_MSIX_P_PORT 17
45 #define MSIX_LEGACY_SZ 4
46 #define MIN_MSIX_P_PORT 5
49 MLX4_FLAG_MSI_X
= 1 << 0,
50 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
51 MLX4_FLAG_MASTER
= 1 << 2,
52 MLX4_FLAG_SLAVE
= 1 << 3,
53 MLX4_FLAG_SRIOV
= 1 << 4,
60 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
61 * These qkeys must not be allowed for general use. This is a 64k range,
62 * and to test for violation, we use the mask (protect against future chg).
64 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
65 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
68 MLX4_BOARD_ID_LEN
= 64
75 MLX4_MAX_EQ_NUM
= 1024,
76 MLX4_MFUNC_EQ_NUM
= 4,
77 MLX4_MFUNC_MAX_EQES
= 8,
78 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
81 /* Driver supports 3 diffrent device methods to manage traffic steering:
82 * -device managed - High level API for ib and eth flow steering. FW is
83 * managing flow steering tables.
84 * - B0 steering mode - Common low level API for ib and (if supported) eth.
85 * - A0 steering mode - Limited low level API for eth. In case of IB,
89 MLX4_STEERING_MODE_A0
,
90 MLX4_STEERING_MODE_B0
,
91 MLX4_STEERING_MODE_DEVICE_MANAGED
94 static inline const char *mlx4_steering_mode_str(int steering_mode
)
96 switch (steering_mode
) {
97 case MLX4_STEERING_MODE_A0
:
100 case MLX4_STEERING_MODE_B0
:
101 return "B0 steering";
103 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
104 return "Device managed flow steering";
107 return "Unrecognize steering mode";
112 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
113 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
114 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
115 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
116 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
117 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
118 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
119 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
120 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
121 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
122 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
123 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
124 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
125 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
126 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
127 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
128 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
129 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
130 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
131 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
132 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
133 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
134 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
135 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
136 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
137 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55,
138 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
= 1LL << 59,
142 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
143 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
144 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2,
145 MLX4_DEV_CAP_FLAG2_FS_EN
= 1LL << 3
148 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
151 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
152 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
153 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
154 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
155 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
159 MLX4_EVENT_TYPE_COMP
= 0x00,
160 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
161 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
162 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
163 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
164 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
165 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
166 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
167 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
168 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
169 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
170 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
171 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
172 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
173 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
174 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
175 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
176 MLX4_EVENT_TYPE_CMD
= 0x0a,
177 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
178 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
179 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
180 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
181 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT
= 0x1d,
182 MLX4_EVENT_TYPE_NONE
= 0xff,
186 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
187 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
191 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
195 MLX4_PERM_LOCAL_READ
= 1 << 10,
196 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
197 MLX4_PERM_REMOTE_READ
= 1 << 12,
198 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
199 MLX4_PERM_ATOMIC
= 1 << 14
203 MLX4_OPCODE_NOP
= 0x00,
204 MLX4_OPCODE_SEND_INVAL
= 0x01,
205 MLX4_OPCODE_RDMA_WRITE
= 0x08,
206 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
207 MLX4_OPCODE_SEND
= 0x0a,
208 MLX4_OPCODE_SEND_IMM
= 0x0b,
209 MLX4_OPCODE_LSO
= 0x0e,
210 MLX4_OPCODE_RDMA_READ
= 0x10,
211 MLX4_OPCODE_ATOMIC_CS
= 0x11,
212 MLX4_OPCODE_ATOMIC_FA
= 0x12,
213 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
214 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
215 MLX4_OPCODE_BIND_MW
= 0x18,
216 MLX4_OPCODE_FMR
= 0x19,
217 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
218 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
220 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
221 MLX4_RECV_OPCODE_SEND
= 0x01,
222 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
223 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
225 MLX4_CQE_OPCODE_ERROR
= 0x1e,
226 MLX4_CQE_OPCODE_RESIZE
= 0x16,
230 MLX4_STAT_RATE_OFFSET
= 5
234 MLX4_PROT_IB_IPV6
= 0,
241 MLX4_MTT_FLAG_PRESENT
= 1
244 enum mlx4_qp_region
{
245 MLX4_QP_REGION_FW
= 0,
246 MLX4_QP_REGION_ETH_ADDR
,
247 MLX4_QP_REGION_FC_ADDR
,
248 MLX4_QP_REGION_FC_EXCH
,
252 enum mlx4_port_type
{
253 MLX4_PORT_TYPE_NONE
= 0,
254 MLX4_PORT_TYPE_IB
= 1,
255 MLX4_PORT_TYPE_ETH
= 2,
256 MLX4_PORT_TYPE_AUTO
= 3
259 enum mlx4_special_vlan_idx
{
260 MLX4_NO_VLAN_IDX
= 0,
265 enum mlx4_steer_type
{
272 MLX4_NUM_FEXCH
= 64 * 1024,
276 MLX4_MAX_FAST_REG_PAGES
= 511,
280 MLX4_DEV_PMC_SUBTYPE_GUID_INFO
= 0x14,
281 MLX4_DEV_PMC_SUBTYPE_PORT_INFO
= 0x15,
282 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE
= 0x16,
285 /* Port mgmt change event handling */
287 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK
= 1 << 0,
288 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK
= 1 << 1,
289 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK
= 1 << 2,
290 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK
= 1 << 3,
291 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK
= 1 << 4,
294 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
295 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
297 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
299 return (major
<< 32) | (minor
<< 16) | subminor
;
302 struct mlx4_phys_caps
{
303 u32 gid_phys_table_len
[MLX4_MAX_PORTS
+ 1];
304 u32 pkey_phys_table_len
[MLX4_MAX_PORTS
+ 1];
312 int vl_cap
[MLX4_MAX_PORTS
+ 1];
313 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
314 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
315 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
316 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
317 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
318 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
319 int trans_type
[MLX4_MAX_PORTS
+ 1];
320 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
321 int wavelength
[MLX4_MAX_PORTS
+ 1];
322 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
323 int local_ca_ack_delay
;
327 int bf_regs_per_page
;
334 int max_qp_init_rdma
;
335 int max_qp_dest_rdma
;
338 u32 base_tunnel_sqpn
;
348 int num_comp_vectors
;
353 int fmr_reserved_mtts
;
362 int fs_log_max_ucast_qp_range_size
;
374 u16 stat_rate_support
;
375 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
378 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
380 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
384 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
385 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
386 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
387 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
388 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
389 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
391 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
394 struct mlx4_buf_list
{
400 struct mlx4_buf_list direct
;
401 struct mlx4_buf_list
*page_list
;
414 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
417 struct mlx4_db_pgdir
{
418 struct list_head list
;
419 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
420 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
421 unsigned long *bits
[2];
426 struct mlx4_ib_user_db_page
;
431 struct mlx4_db_pgdir
*pgdir
;
432 struct mlx4_ib_user_db_page
*user_page
;
439 struct mlx4_hwq_resources
{
457 struct mlx4_mpt_entry
*mpt
;
459 dma_addr_t dma_handle
;
469 struct list_head bf_list
;
470 unsigned free_bf_bmap
;
472 void __iomem
*bf_map
;
476 unsigned long offset
;
478 struct mlx4_uar
*uar
;
483 void (*comp
) (struct mlx4_cq
*);
484 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
486 struct mlx4_uar
*uar
;
498 struct completion free
;
502 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
507 struct completion free
;
511 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
519 struct completion free
;
531 __be32 sl_tclass_flowlabel
;
544 __be32 sl_tclass_flowlabel
;
553 struct mlx4_eth_av eth
;
556 struct mlx4_counter
{
568 struct pci_dev
*pdev
;
570 unsigned long num_slaves
;
571 struct mlx4_caps caps
;
572 struct mlx4_phys_caps phys_caps
;
573 struct radix_tree_root qp_table_tree
;
575 char board_id
[MLX4_BOARD_ID_LEN
];
577 u64 regid_promisc_array
[MLX4_MAX_PORTS
+ 1];
578 u64 regid_allmulti_array
[MLX4_MAX_PORTS
+ 1];
614 } __packed port_change
;
616 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
618 u32 bit_vec
[COMM_CHANNEL_BIT_ARRAY_SIZE
];
619 } __packed comm_channel_arm
;
624 } __packed mac_update
;
627 } __packed flr_event
;
629 __be16 current_temperature
;
630 __be16 warning_threshold
;
643 } __packed port_info
;
646 __be32 tbl_entries_mask
;
647 } __packed tbl_change_info
;
649 } __packed port_mgmt_change
;
656 struct mlx4_init_port_param
{
670 #define mlx4_foreach_port(port, dev, type) \
671 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
672 if ((type) == (dev)->caps.port_mask[(port)])
674 #define mlx4_foreach_ib_transport_port(port, dev) \
675 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
676 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
677 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
679 #define MLX4_INVALID_SLAVE_ID 0xFF
681 void handle_port_mgmt_change_event(struct work_struct
*work
);
683 static inline int mlx4_master_func_num(struct mlx4_dev
*dev
)
685 return dev
->caps
.function
;
688 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
690 return dev
->flags
& MLX4_FLAG_MASTER
;
693 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
695 return (qpn
< dev
->caps
.sqp_start
+ 8);
698 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
700 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
703 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
705 return dev
->flags
& MLX4_FLAG_SLAVE
;
708 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
709 struct mlx4_buf
*buf
);
710 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
711 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
713 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
714 return buf
->direct
.buf
+ offset
;
716 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
717 (offset
& (PAGE_SIZE
- 1));
720 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
721 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
722 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
723 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
725 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
726 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
727 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
728 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
730 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
731 struct mlx4_mtt
*mtt
);
732 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
733 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
735 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
736 int npages
, int page_shift
, struct mlx4_mr
*mr
);
737 void mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
738 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
739 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
740 int start_index
, int npages
, u64
*page_list
);
741 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
742 struct mlx4_buf
*buf
);
744 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
);
745 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
747 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
748 int size
, int max_direct
);
749 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
752 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
753 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
754 unsigned vector
, int collapsed
);
755 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
757 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
758 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
760 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
);
761 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
763 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
764 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
765 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
766 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
767 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
769 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
770 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
772 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
773 int block_mcast_loopback
, enum mlx4_protocol prot
);
774 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
775 enum mlx4_protocol prot
);
776 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
777 u8 port
, int block_mcast_loopback
,
778 enum mlx4_protocol protocol
, u64
*reg_id
);
779 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
780 enum mlx4_protocol protocol
, u64 reg_id
);
783 MLX4_DOMAIN_UVERBS
= 0x1000,
784 MLX4_DOMAIN_ETHTOOL
= 0x2000,
785 MLX4_DOMAIN_RFS
= 0x3000,
786 MLX4_DOMAIN_NIC
= 0x5000,
789 enum mlx4_net_trans_rule_id
{
790 MLX4_NET_TRANS_RULE_ID_ETH
= 0,
791 MLX4_NET_TRANS_RULE_ID_IB
,
792 MLX4_NET_TRANS_RULE_ID_IPV6
,
793 MLX4_NET_TRANS_RULE_ID_IPV4
,
794 MLX4_NET_TRANS_RULE_ID_TCP
,
795 MLX4_NET_TRANS_RULE_ID_UDP
,
796 MLX4_NET_TRANS_RULE_NUM
, /* should be last */
799 extern const u16 __sw_id_hw
[];
801 static inline int map_hw_to_sw_id(u16 header_id
)
805 for (i
= 0; i
< MLX4_NET_TRANS_RULE_NUM
; i
++) {
806 if (header_id
== __sw_id_hw
[i
])
812 enum mlx4_net_trans_promisc_mode
{
813 MLX4_FS_PROMISC_NONE
= 0,
814 MLX4_FS_PROMISC_UPLINK
,
815 /* For future use. Not implemented yet */
816 MLX4_FS_PROMISC_FUNCTION_PORT
,
817 MLX4_FS_PROMISC_ALL_MULTI
,
820 struct mlx4_spec_eth
{
825 u8 ether_type_enable
;
831 struct mlx4_spec_tcp_udp
{
838 struct mlx4_spec_ipv4
{
845 struct mlx4_spec_ib
{
852 struct mlx4_spec_list
{
853 struct list_head list
;
854 enum mlx4_net_trans_rule_id id
;
856 struct mlx4_spec_eth eth
;
857 struct mlx4_spec_ib ib
;
858 struct mlx4_spec_ipv4 ipv4
;
859 struct mlx4_spec_tcp_udp tcp_udp
;
863 enum mlx4_net_trans_hw_rule_queue
{
864 MLX4_NET_TRANS_Q_FIFO
,
865 MLX4_NET_TRANS_Q_LIFO
,
868 struct mlx4_net_trans_rule
{
869 struct list_head list
;
870 enum mlx4_net_trans_hw_rule_queue queue_mode
;
873 enum mlx4_net_trans_promisc_mode promisc_mode
;
879 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
, u32 qpn
,
880 enum mlx4_net_trans_promisc_mode mode
);
881 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
882 enum mlx4_net_trans_promisc_mode mode
);
883 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
884 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
885 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
886 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
887 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
889 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
890 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
891 int mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
892 int mlx4_get_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *qpn
);
893 void mlx4_put_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int qpn
);
894 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
);
895 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
896 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
897 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
899 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
);
900 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
901 u8
*pg
, u16
*ratelimit
);
902 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
903 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
904 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, int index
);
906 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
907 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
908 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
909 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
910 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
911 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
912 u32
*lkey
, u32
*rkey
);
913 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
914 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
915 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
916 int mlx4_assign_eq(struct mlx4_dev
*dev
, char *name
, struct cpu_rmap
*rmap
,
918 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
920 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
921 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
923 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
924 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
926 int mlx4_flow_attach(struct mlx4_dev
*dev
,
927 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
);
928 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
);
930 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
);
932 #endif /* MLX4_DEVICE_H */