2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <linux/atomic.h>
42 #define MAX_MSIX_P_PORT 17
44 #define MSIX_LEGACY_SZ 4
45 #define MIN_MSIX_P_PORT 5
48 MLX4_FLAG_MSI_X
= 1 << 0,
49 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
50 MLX4_FLAG_MASTER
= 1 << 2,
51 MLX4_FLAG_SLAVE
= 1 << 3,
52 MLX4_FLAG_SRIOV
= 1 << 4,
60 MLX4_BOARD_ID_LEN
= 64
67 MLX4_MAX_EQ_NUM
= 1024,
68 MLX4_MFUNC_EQ_NUM
= 4,
69 MLX4_MFUNC_MAX_EQES
= 8,
70 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
73 /* Driver supports 3 diffrent device methods to manage traffic steering:
74 * -device managed - High level API for ib and eth flow steering. FW is
75 * managing flow steering tables.
76 * - B0 steering mode - Common low level API for ib and (if supported) eth.
77 * - A0 steering mode - Limited low level API for eth. In case of IB,
81 MLX4_STEERING_MODE_A0
,
82 MLX4_STEERING_MODE_B0
,
83 MLX4_STEERING_MODE_DEVICE_MANAGED
86 static inline const char *mlx4_steering_mode_str(int steering_mode
)
88 switch (steering_mode
) {
89 case MLX4_STEERING_MODE_A0
:
92 case MLX4_STEERING_MODE_B0
:
95 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
96 return "Device managed flow steering";
99 return "Unrecognize steering mode";
104 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
105 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
106 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
107 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
108 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
109 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
110 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
111 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
112 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
113 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
114 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
115 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
116 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
117 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
118 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
119 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
120 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
121 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
122 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
123 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
124 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
125 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
126 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
127 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
128 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
129 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55
133 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
134 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
135 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2,
136 MLX4_DEV_CAP_FLAG2_FS_EN
= 1LL << 3
139 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
142 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
143 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
144 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
145 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
146 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
150 MLX4_EVENT_TYPE_COMP
= 0x00,
151 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
152 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
153 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
154 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
155 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
156 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
157 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
158 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
159 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
160 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
161 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
162 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
163 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
164 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
165 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
166 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
167 MLX4_EVENT_TYPE_CMD
= 0x0a,
168 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
169 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
170 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
171 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
172 MLX4_EVENT_TYPE_NONE
= 0xff,
176 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
177 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
181 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
185 MLX4_PERM_LOCAL_READ
= 1 << 10,
186 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
187 MLX4_PERM_REMOTE_READ
= 1 << 12,
188 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
189 MLX4_PERM_ATOMIC
= 1 << 14
193 MLX4_OPCODE_NOP
= 0x00,
194 MLX4_OPCODE_SEND_INVAL
= 0x01,
195 MLX4_OPCODE_RDMA_WRITE
= 0x08,
196 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
197 MLX4_OPCODE_SEND
= 0x0a,
198 MLX4_OPCODE_SEND_IMM
= 0x0b,
199 MLX4_OPCODE_LSO
= 0x0e,
200 MLX4_OPCODE_RDMA_READ
= 0x10,
201 MLX4_OPCODE_ATOMIC_CS
= 0x11,
202 MLX4_OPCODE_ATOMIC_FA
= 0x12,
203 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
204 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
205 MLX4_OPCODE_BIND_MW
= 0x18,
206 MLX4_OPCODE_FMR
= 0x19,
207 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
208 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
210 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
211 MLX4_RECV_OPCODE_SEND
= 0x01,
212 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
213 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
215 MLX4_CQE_OPCODE_ERROR
= 0x1e,
216 MLX4_CQE_OPCODE_RESIZE
= 0x16,
220 MLX4_STAT_RATE_OFFSET
= 5
224 MLX4_PROT_IB_IPV6
= 0,
231 MLX4_MTT_FLAG_PRESENT
= 1
234 enum mlx4_qp_region
{
235 MLX4_QP_REGION_FW
= 0,
236 MLX4_QP_REGION_ETH_ADDR
,
237 MLX4_QP_REGION_FC_ADDR
,
238 MLX4_QP_REGION_FC_EXCH
,
242 enum mlx4_port_type
{
243 MLX4_PORT_TYPE_NONE
= 0,
244 MLX4_PORT_TYPE_IB
= 1,
245 MLX4_PORT_TYPE_ETH
= 2,
246 MLX4_PORT_TYPE_AUTO
= 3
249 enum mlx4_special_vlan_idx
{
250 MLX4_NO_VLAN_IDX
= 0,
255 enum mlx4_steer_type
{
262 MLX4_NUM_FEXCH
= 64 * 1024,
266 MLX4_MAX_FAST_REG_PAGES
= 511,
269 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
271 return (major
<< 32) | (minor
<< 16) | subminor
;
274 struct mlx4_phys_caps
{
282 int vl_cap
[MLX4_MAX_PORTS
+ 1];
283 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
284 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
285 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
286 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
287 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
288 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
289 int trans_type
[MLX4_MAX_PORTS
+ 1];
290 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
291 int wavelength
[MLX4_MAX_PORTS
+ 1];
292 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
293 int local_ca_ack_delay
;
297 int bf_regs_per_page
;
304 int max_qp_init_rdma
;
305 int max_qp_dest_rdma
;
316 int num_comp_vectors
;
321 int fmr_reserved_mtts
;
330 int fs_log_max_ucast_qp_range_size
;
342 u16 stat_rate_support
;
343 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
346 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
348 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
352 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
353 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
354 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
355 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
356 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
357 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
359 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
362 struct mlx4_buf_list
{
368 struct mlx4_buf_list direct
;
369 struct mlx4_buf_list
*page_list
;
382 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
385 struct mlx4_db_pgdir
{
386 struct list_head list
;
387 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
388 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
389 unsigned long *bits
[2];
394 struct mlx4_ib_user_db_page
;
399 struct mlx4_db_pgdir
*pgdir
;
400 struct mlx4_ib_user_db_page
*user_page
;
407 struct mlx4_hwq_resources
{
425 struct mlx4_mpt_entry
*mpt
;
427 dma_addr_t dma_handle
;
437 struct list_head bf_list
;
438 unsigned free_bf_bmap
;
440 void __iomem
*bf_map
;
444 unsigned long offset
;
446 struct mlx4_uar
*uar
;
451 void (*comp
) (struct mlx4_cq
*);
452 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
454 struct mlx4_uar
*uar
;
466 struct completion free
;
470 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
475 struct completion free
;
479 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
487 struct completion free
;
499 __be32 sl_tclass_flowlabel
;
512 __be32 sl_tclass_flowlabel
;
521 struct mlx4_eth_av eth
;
524 struct mlx4_counter
{
536 struct pci_dev
*pdev
;
538 unsigned long num_slaves
;
539 struct mlx4_caps caps
;
540 struct mlx4_phys_caps phys_caps
;
541 struct radix_tree_root qp_table_tree
;
543 char board_id
[MLX4_BOARD_ID_LEN
];
545 u64 regid_promisc_array
[MLX4_MAX_PORTS
+ 1];
546 u64 regid_allmulti_array
[MLX4_MAX_PORTS
+ 1];
549 struct mlx4_init_port_param
{
563 #define mlx4_foreach_port(port, dev, type) \
564 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
565 if ((type) == (dev)->caps.port_mask[(port)])
567 #define mlx4_foreach_ib_transport_port(port, dev) \
568 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
569 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
570 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
572 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
574 return dev
->flags
& MLX4_FLAG_MASTER
;
577 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
579 return (qpn
< dev
->caps
.sqp_start
+ 8);
582 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
584 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
587 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
589 return dev
->flags
& MLX4_FLAG_SLAVE
;
592 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
593 struct mlx4_buf
*buf
);
594 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
595 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
597 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
598 return buf
->direct
.buf
+ offset
;
600 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
601 (offset
& (PAGE_SIZE
- 1));
604 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
605 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
606 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
607 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
609 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
610 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
611 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
612 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
614 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
615 struct mlx4_mtt
*mtt
);
616 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
617 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
619 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
620 int npages
, int page_shift
, struct mlx4_mr
*mr
);
621 void mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
622 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
623 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
624 int start_index
, int npages
, u64
*page_list
);
625 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
626 struct mlx4_buf
*buf
);
628 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
);
629 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
631 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
632 int size
, int max_direct
);
633 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
636 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
637 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
638 unsigned vector
, int collapsed
);
639 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
641 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
642 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
644 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
);
645 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
647 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
648 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
649 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
650 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
651 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
653 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
654 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
656 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
657 int block_mcast_loopback
, enum mlx4_protocol prot
);
658 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
659 enum mlx4_protocol prot
);
660 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
661 u8 port
, int block_mcast_loopback
,
662 enum mlx4_protocol protocol
, u64
*reg_id
);
663 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
664 enum mlx4_protocol protocol
, u64 reg_id
);
667 MLX4_DOMAIN_UVERBS
= 0x1000,
668 MLX4_DOMAIN_ETHTOOL
= 0x2000,
669 MLX4_DOMAIN_RFS
= 0x3000,
670 MLX4_DOMAIN_NIC
= 0x5000,
673 enum mlx4_net_trans_rule_id
{
674 MLX4_NET_TRANS_RULE_ID_ETH
= 0,
675 MLX4_NET_TRANS_RULE_ID_IB
,
676 MLX4_NET_TRANS_RULE_ID_IPV6
,
677 MLX4_NET_TRANS_RULE_ID_IPV4
,
678 MLX4_NET_TRANS_RULE_ID_TCP
,
679 MLX4_NET_TRANS_RULE_ID_UDP
,
680 MLX4_NET_TRANS_RULE_NUM
, /* should be last */
683 enum mlx4_net_trans_promisc_mode
{
684 MLX4_FS_PROMISC_NONE
= 0,
685 MLX4_FS_PROMISC_UPLINK
,
686 /* For future use. Not implemented yet */
687 MLX4_FS_PROMISC_FUNCTION_PORT
,
688 MLX4_FS_PROMISC_ALL_MULTI
,
691 struct mlx4_spec_eth
{
696 u8 ether_type_enable
;
702 struct mlx4_spec_tcp_udp
{
709 struct mlx4_spec_ipv4
{
716 struct mlx4_spec_ib
{
723 struct mlx4_spec_list
{
724 struct list_head list
;
725 enum mlx4_net_trans_rule_id id
;
727 struct mlx4_spec_eth eth
;
728 struct mlx4_spec_ib ib
;
729 struct mlx4_spec_ipv4 ipv4
;
730 struct mlx4_spec_tcp_udp tcp_udp
;
734 enum mlx4_net_trans_hw_rule_queue
{
735 MLX4_NET_TRANS_Q_FIFO
,
736 MLX4_NET_TRANS_Q_LIFO
,
739 struct mlx4_net_trans_rule
{
740 struct list_head list
;
741 enum mlx4_net_trans_hw_rule_queue queue_mode
;
744 enum mlx4_net_trans_promisc_mode promisc_mode
;
750 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
, u32 qpn
,
751 enum mlx4_net_trans_promisc_mode mode
);
752 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
753 enum mlx4_net_trans_promisc_mode mode
);
754 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
755 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
756 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
757 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
758 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
760 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
761 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
762 int mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
763 int mlx4_get_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *qpn
);
764 void mlx4_put_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int qpn
);
765 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
);
766 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
767 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
768 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
770 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
);
771 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
772 u8
*pg
, u16
*ratelimit
);
773 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
774 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
775 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, int index
);
777 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
778 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
779 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
780 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
781 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
782 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
783 u32
*lkey
, u32
*rkey
);
784 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
785 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
786 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
787 int mlx4_assign_eq(struct mlx4_dev
*dev
, char* name
, int* vector
);
788 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
790 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
791 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
793 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
794 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
796 int mlx4_flow_attach(struct mlx4_dev
*dev
,
797 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
);
798 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
);
800 #endif /* MLX4_DEVICE_H */