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[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41
42 #include <linux/atomic.h>
43
44 #include <linux/clocksource.h>
45
46 #define MAX_MSIX_P_PORT 17
47 #define MAX_MSIX 64
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
50
51 #define MLX4_ROCE_MAX_GIDS 128
52 #define MLX4_ROCE_PF_GIDS 16
53
54 enum {
55 MLX4_FLAG_MSI_X = 1 << 0,
56 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
57 MLX4_FLAG_MASTER = 1 << 2,
58 MLX4_FLAG_SLAVE = 1 << 3,
59 MLX4_FLAG_SRIOV = 1 << 4,
60 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
61 };
62
63 enum {
64 MLX4_PORT_CAP_IS_SM = 1 << 1,
65 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
66 };
67
68 enum {
69 MLX4_MAX_PORTS = 2,
70 MLX4_MAX_PORT_PKEYS = 128
71 };
72
73 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
74 * These qkeys must not be allowed for general use. This is a 64k range,
75 * and to test for violation, we use the mask (protect against future chg).
76 */
77 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
78 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
79
80 enum {
81 MLX4_BOARD_ID_LEN = 64
82 };
83
84 enum {
85 MLX4_MAX_NUM_PF = 16,
86 MLX4_MAX_NUM_VF = 64,
87 MLX4_MFUNC_MAX = 80,
88 MLX4_MAX_EQ_NUM = 1024,
89 MLX4_MFUNC_EQ_NUM = 4,
90 MLX4_MFUNC_MAX_EQES = 8,
91 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
92 };
93
94 /* Driver supports 3 diffrent device methods to manage traffic steering:
95 * -device managed - High level API for ib and eth flow steering. FW is
96 * managing flow steering tables.
97 * - B0 steering mode - Common low level API for ib and (if supported) eth.
98 * - A0 steering mode - Limited low level API for eth. In case of IB,
99 * B0 mode is in use.
100 */
101 enum {
102 MLX4_STEERING_MODE_A0,
103 MLX4_STEERING_MODE_B0,
104 MLX4_STEERING_MODE_DEVICE_MANAGED
105 };
106
107 static inline const char *mlx4_steering_mode_str(int steering_mode)
108 {
109 switch (steering_mode) {
110 case MLX4_STEERING_MODE_A0:
111 return "A0 steering";
112
113 case MLX4_STEERING_MODE_B0:
114 return "B0 steering";
115
116 case MLX4_STEERING_MODE_DEVICE_MANAGED:
117 return "Device managed flow steering";
118
119 default:
120 return "Unrecognize steering mode";
121 }
122 }
123
124 enum {
125 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
126 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
127 };
128
129 enum {
130 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
131 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
132 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
133 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
134 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
135 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
136 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
137 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
138 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
139 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
140 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
141 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
142 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
143 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
144 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
145 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
146 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
147 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
148 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
149 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
150 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
151 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
152 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
153 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
154 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
155 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
156 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
157 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
158 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
159 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
160 };
161
162 enum {
163 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
164 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
165 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
166 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
167 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
168 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
169 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
170 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
171 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
172 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
173 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
174 };
175
176 enum {
177 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
178 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
179 };
180
181 enum {
182 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
183 };
184
185 enum {
186 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
187 };
188
189
190 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
191
192 enum {
193 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
194 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
195 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
196 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
197 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
198 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
199 };
200
201 enum mlx4_event {
202 MLX4_EVENT_TYPE_COMP = 0x00,
203 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
204 MLX4_EVENT_TYPE_COMM_EST = 0x02,
205 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
206 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
207 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
208 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
209 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
210 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
211 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
212 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
213 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
214 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
215 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
216 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
217 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
218 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
219 MLX4_EVENT_TYPE_CMD = 0x0a,
220 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
221 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
222 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
223 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
224 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
225 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
226 MLX4_EVENT_TYPE_NONE = 0xff,
227 };
228
229 enum {
230 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
231 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
232 };
233
234 enum {
235 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
236 };
237
238 enum slave_port_state {
239 SLAVE_PORT_DOWN = 0,
240 SLAVE_PENDING_UP,
241 SLAVE_PORT_UP,
242 };
243
244 enum slave_port_gen_event {
245 SLAVE_PORT_GEN_EVENT_DOWN = 0,
246 SLAVE_PORT_GEN_EVENT_UP,
247 SLAVE_PORT_GEN_EVENT_NONE,
248 };
249
250 enum slave_port_state_event {
251 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
252 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
253 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
254 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
255 };
256
257 enum {
258 MLX4_PERM_LOCAL_READ = 1 << 10,
259 MLX4_PERM_LOCAL_WRITE = 1 << 11,
260 MLX4_PERM_REMOTE_READ = 1 << 12,
261 MLX4_PERM_REMOTE_WRITE = 1 << 13,
262 MLX4_PERM_ATOMIC = 1 << 14,
263 MLX4_PERM_BIND_MW = 1 << 15,
264 };
265
266 enum {
267 MLX4_OPCODE_NOP = 0x00,
268 MLX4_OPCODE_SEND_INVAL = 0x01,
269 MLX4_OPCODE_RDMA_WRITE = 0x08,
270 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
271 MLX4_OPCODE_SEND = 0x0a,
272 MLX4_OPCODE_SEND_IMM = 0x0b,
273 MLX4_OPCODE_LSO = 0x0e,
274 MLX4_OPCODE_RDMA_READ = 0x10,
275 MLX4_OPCODE_ATOMIC_CS = 0x11,
276 MLX4_OPCODE_ATOMIC_FA = 0x12,
277 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
278 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
279 MLX4_OPCODE_BIND_MW = 0x18,
280 MLX4_OPCODE_FMR = 0x19,
281 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
282 MLX4_OPCODE_CONFIG_CMD = 0x1f,
283
284 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
285 MLX4_RECV_OPCODE_SEND = 0x01,
286 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
287 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
288
289 MLX4_CQE_OPCODE_ERROR = 0x1e,
290 MLX4_CQE_OPCODE_RESIZE = 0x16,
291 };
292
293 enum {
294 MLX4_STAT_RATE_OFFSET = 5
295 };
296
297 enum mlx4_protocol {
298 MLX4_PROT_IB_IPV6 = 0,
299 MLX4_PROT_ETH,
300 MLX4_PROT_IB_IPV4,
301 MLX4_PROT_FCOE
302 };
303
304 enum {
305 MLX4_MTT_FLAG_PRESENT = 1
306 };
307
308 enum mlx4_qp_region {
309 MLX4_QP_REGION_FW = 0,
310 MLX4_QP_REGION_ETH_ADDR,
311 MLX4_QP_REGION_FC_ADDR,
312 MLX4_QP_REGION_FC_EXCH,
313 MLX4_NUM_QP_REGION
314 };
315
316 enum mlx4_port_type {
317 MLX4_PORT_TYPE_NONE = 0,
318 MLX4_PORT_TYPE_IB = 1,
319 MLX4_PORT_TYPE_ETH = 2,
320 MLX4_PORT_TYPE_AUTO = 3
321 };
322
323 enum mlx4_special_vlan_idx {
324 MLX4_NO_VLAN_IDX = 0,
325 MLX4_VLAN_MISS_IDX,
326 MLX4_VLAN_REGULAR
327 };
328
329 enum mlx4_steer_type {
330 MLX4_MC_STEER = 0,
331 MLX4_UC_STEER,
332 MLX4_NUM_STEERS
333 };
334
335 enum {
336 MLX4_NUM_FEXCH = 64 * 1024,
337 };
338
339 enum {
340 MLX4_MAX_FAST_REG_PAGES = 511,
341 };
342
343 enum {
344 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
345 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
346 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
347 };
348
349 /* Port mgmt change event handling */
350 enum {
351 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
352 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
353 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
354 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
355 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
356 };
357
358 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
359 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
360
361 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
362 {
363 return (major << 32) | (minor << 16) | subminor;
364 }
365
366 struct mlx4_phys_caps {
367 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
368 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
369 u32 num_phys_eqs;
370 u32 base_sqpn;
371 u32 base_proxy_sqpn;
372 u32 base_tunnel_sqpn;
373 };
374
375 struct mlx4_caps {
376 u64 fw_ver;
377 u32 function;
378 int num_ports;
379 int vl_cap[MLX4_MAX_PORTS + 1];
380 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
381 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
382 u64 def_mac[MLX4_MAX_PORTS + 1];
383 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
384 int gid_table_len[MLX4_MAX_PORTS + 1];
385 int pkey_table_len[MLX4_MAX_PORTS + 1];
386 int trans_type[MLX4_MAX_PORTS + 1];
387 int vendor_oui[MLX4_MAX_PORTS + 1];
388 int wavelength[MLX4_MAX_PORTS + 1];
389 u64 trans_code[MLX4_MAX_PORTS + 1];
390 int local_ca_ack_delay;
391 int num_uars;
392 u32 uar_page_size;
393 int bf_reg_size;
394 int bf_regs_per_page;
395 int max_sq_sg;
396 int max_rq_sg;
397 int num_qps;
398 int max_wqes;
399 int max_sq_desc_sz;
400 int max_rq_desc_sz;
401 int max_qp_init_rdma;
402 int max_qp_dest_rdma;
403 u32 *qp0_proxy;
404 u32 *qp1_proxy;
405 u32 *qp0_tunnel;
406 u32 *qp1_tunnel;
407 int num_srqs;
408 int max_srq_wqes;
409 int max_srq_sge;
410 int reserved_srqs;
411 int num_cqs;
412 int max_cqes;
413 int reserved_cqs;
414 int num_eqs;
415 int reserved_eqs;
416 int num_comp_vectors;
417 int comp_pool;
418 int num_mpts;
419 int max_fmr_maps;
420 int num_mtts;
421 int fmr_reserved_mtts;
422 int reserved_mtts;
423 int reserved_mrws;
424 int reserved_uars;
425 int num_mgms;
426 int num_amgms;
427 int reserved_mcgs;
428 int num_qp_per_mgm;
429 int steering_mode;
430 int fs_log_max_ucast_qp_range_size;
431 int num_pds;
432 int reserved_pds;
433 int max_xrcds;
434 int reserved_xrcds;
435 int mtt_entry_sz;
436 u32 max_msg_sz;
437 u32 page_size_cap;
438 u64 flags;
439 u64 flags2;
440 u32 bmme_flags;
441 u32 reserved_lkey;
442 u16 stat_rate_support;
443 u8 port_width_cap[MLX4_MAX_PORTS + 1];
444 int max_gso_sz;
445 int max_rss_tbl_sz;
446 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
447 int reserved_qps;
448 int reserved_qps_base[MLX4_NUM_QP_REGION];
449 int log_num_macs;
450 int log_num_vlans;
451 int log_num_prios;
452 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
453 u8 supported_type[MLX4_MAX_PORTS + 1];
454 u8 suggested_type[MLX4_MAX_PORTS + 1];
455 u8 default_sense[MLX4_MAX_PORTS + 1];
456 u32 port_mask[MLX4_MAX_PORTS + 1];
457 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
458 u32 max_counters;
459 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
460 u16 sqp_demux;
461 u32 eqe_size;
462 u32 cqe_size;
463 u8 eqe_factor;
464 u32 userspace_caps; /* userspace must be aware of these */
465 u32 function_caps; /* VFs must be aware of these */
466 u16 hca_core_clock;
467 u64 phys_port_id[MLX4_MAX_PORTS + 1];
468 int tunnel_offload_mode;
469 };
470
471 struct mlx4_buf_list {
472 void *buf;
473 dma_addr_t map;
474 };
475
476 struct mlx4_buf {
477 struct mlx4_buf_list direct;
478 struct mlx4_buf_list *page_list;
479 int nbufs;
480 int npages;
481 int page_shift;
482 };
483
484 struct mlx4_mtt {
485 u32 offset;
486 int order;
487 int page_shift;
488 };
489
490 enum {
491 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
492 };
493
494 struct mlx4_db_pgdir {
495 struct list_head list;
496 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
497 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
498 unsigned long *bits[2];
499 __be32 *db_page;
500 dma_addr_t db_dma;
501 };
502
503 struct mlx4_ib_user_db_page;
504
505 struct mlx4_db {
506 __be32 *db;
507 union {
508 struct mlx4_db_pgdir *pgdir;
509 struct mlx4_ib_user_db_page *user_page;
510 } u;
511 dma_addr_t dma;
512 int index;
513 int order;
514 };
515
516 struct mlx4_hwq_resources {
517 struct mlx4_db db;
518 struct mlx4_mtt mtt;
519 struct mlx4_buf buf;
520 };
521
522 struct mlx4_mr {
523 struct mlx4_mtt mtt;
524 u64 iova;
525 u64 size;
526 u32 key;
527 u32 pd;
528 u32 access;
529 int enabled;
530 };
531
532 enum mlx4_mw_type {
533 MLX4_MW_TYPE_1 = 1,
534 MLX4_MW_TYPE_2 = 2,
535 };
536
537 struct mlx4_mw {
538 u32 key;
539 u32 pd;
540 enum mlx4_mw_type type;
541 int enabled;
542 };
543
544 struct mlx4_fmr {
545 struct mlx4_mr mr;
546 struct mlx4_mpt_entry *mpt;
547 __be64 *mtts;
548 dma_addr_t dma_handle;
549 int max_pages;
550 int max_maps;
551 int maps;
552 u8 page_shift;
553 };
554
555 struct mlx4_uar {
556 unsigned long pfn;
557 int index;
558 struct list_head bf_list;
559 unsigned free_bf_bmap;
560 void __iomem *map;
561 void __iomem *bf_map;
562 };
563
564 struct mlx4_bf {
565 unsigned long offset;
566 int buf_size;
567 struct mlx4_uar *uar;
568 void __iomem *reg;
569 };
570
571 struct mlx4_cq {
572 void (*comp) (struct mlx4_cq *);
573 void (*event) (struct mlx4_cq *, enum mlx4_event);
574
575 struct mlx4_uar *uar;
576
577 u32 cons_index;
578
579 __be32 *set_ci_db;
580 __be32 *arm_db;
581 int arm_sn;
582
583 int cqn;
584 unsigned vector;
585
586 atomic_t refcount;
587 struct completion free;
588 };
589
590 struct mlx4_qp {
591 void (*event) (struct mlx4_qp *, enum mlx4_event);
592
593 int qpn;
594
595 atomic_t refcount;
596 struct completion free;
597 };
598
599 struct mlx4_srq {
600 void (*event) (struct mlx4_srq *, enum mlx4_event);
601
602 int srqn;
603 int max;
604 int max_gs;
605 int wqe_shift;
606
607 atomic_t refcount;
608 struct completion free;
609 };
610
611 struct mlx4_av {
612 __be32 port_pd;
613 u8 reserved1;
614 u8 g_slid;
615 __be16 dlid;
616 u8 reserved2;
617 u8 gid_index;
618 u8 stat_rate;
619 u8 hop_limit;
620 __be32 sl_tclass_flowlabel;
621 u8 dgid[16];
622 };
623
624 struct mlx4_eth_av {
625 __be32 port_pd;
626 u8 reserved1;
627 u8 smac_idx;
628 u16 reserved2;
629 u8 reserved3;
630 u8 gid_index;
631 u8 stat_rate;
632 u8 hop_limit;
633 __be32 sl_tclass_flowlabel;
634 u8 dgid[16];
635 u32 reserved4[2];
636 __be16 vlan;
637 u8 mac[ETH_ALEN];
638 };
639
640 union mlx4_ext_av {
641 struct mlx4_av ib;
642 struct mlx4_eth_av eth;
643 };
644
645 struct mlx4_counter {
646 u8 reserved1[3];
647 u8 counter_mode;
648 __be32 num_ifc;
649 u32 reserved2[2];
650 __be64 rx_frames;
651 __be64 rx_bytes;
652 __be64 tx_frames;
653 __be64 tx_bytes;
654 };
655
656 struct mlx4_quotas {
657 int qp;
658 int cq;
659 int srq;
660 int mpt;
661 int mtt;
662 int counter;
663 int xrcd;
664 };
665
666 struct mlx4_dev {
667 struct pci_dev *pdev;
668 unsigned long flags;
669 unsigned long num_slaves;
670 struct mlx4_caps caps;
671 struct mlx4_phys_caps phys_caps;
672 struct mlx4_quotas quotas;
673 struct radix_tree_root qp_table_tree;
674 u8 rev_id;
675 char board_id[MLX4_BOARD_ID_LEN];
676 int num_vfs;
677 int numa_node;
678 int oper_log_mgm_entry_size;
679 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
680 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
681 };
682
683 struct mlx4_eqe {
684 u8 reserved1;
685 u8 type;
686 u8 reserved2;
687 u8 subtype;
688 union {
689 u32 raw[6];
690 struct {
691 __be32 cqn;
692 } __packed comp;
693 struct {
694 u16 reserved1;
695 __be16 token;
696 u32 reserved2;
697 u8 reserved3[3];
698 u8 status;
699 __be64 out_param;
700 } __packed cmd;
701 struct {
702 __be32 qpn;
703 } __packed qp;
704 struct {
705 __be32 srqn;
706 } __packed srq;
707 struct {
708 __be32 cqn;
709 u32 reserved1;
710 u8 reserved2[3];
711 u8 syndrome;
712 } __packed cq_err;
713 struct {
714 u32 reserved1[2];
715 __be32 port;
716 } __packed port_change;
717 struct {
718 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
719 u32 reserved;
720 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
721 } __packed comm_channel_arm;
722 struct {
723 u8 port;
724 u8 reserved[3];
725 __be64 mac;
726 } __packed mac_update;
727 struct {
728 __be32 slave_id;
729 } __packed flr_event;
730 struct {
731 __be16 current_temperature;
732 __be16 warning_threshold;
733 } __packed warming;
734 struct {
735 u8 reserved[3];
736 u8 port;
737 union {
738 struct {
739 __be16 mstr_sm_lid;
740 __be16 port_lid;
741 __be32 changed_attr;
742 u8 reserved[3];
743 u8 mstr_sm_sl;
744 __be64 gid_prefix;
745 } __packed port_info;
746 struct {
747 __be32 block_ptr;
748 __be32 tbl_entries_mask;
749 } __packed tbl_change_info;
750 } params;
751 } __packed port_mgmt_change;
752 } event;
753 u8 slave_id;
754 u8 reserved3[2];
755 u8 owner;
756 } __packed;
757
758 struct mlx4_init_port_param {
759 int set_guid0;
760 int set_node_guid;
761 int set_si_guid;
762 u16 mtu;
763 int port_width_cap;
764 u16 vl_cap;
765 u16 max_gid;
766 u16 max_pkey;
767 u64 guid0;
768 u64 node_guid;
769 u64 si_guid;
770 };
771
772 #define mlx4_foreach_port(port, dev, type) \
773 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
774 if ((type) == (dev)->caps.port_mask[(port)])
775
776 #define mlx4_foreach_non_ib_transport_port(port, dev) \
777 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
778 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
779
780 #define mlx4_foreach_ib_transport_port(port, dev) \
781 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
782 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
783 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
784
785 #define MLX4_INVALID_SLAVE_ID 0xFF
786
787 void handle_port_mgmt_change_event(struct work_struct *work);
788
789 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
790 {
791 return dev->caps.function;
792 }
793
794 static inline int mlx4_is_master(struct mlx4_dev *dev)
795 {
796 return dev->flags & MLX4_FLAG_MASTER;
797 }
798
799 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
800 {
801 return dev->phys_caps.base_sqpn + 8 +
802 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
803 }
804
805 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
806 {
807 return (qpn < dev->phys_caps.base_sqpn + 8 +
808 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
809 }
810
811 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
812 {
813 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
814
815 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
816 return 1;
817
818 return 0;
819 }
820
821 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
822 {
823 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
824 }
825
826 static inline int mlx4_is_slave(struct mlx4_dev *dev)
827 {
828 return dev->flags & MLX4_FLAG_SLAVE;
829 }
830
831 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
832 struct mlx4_buf *buf);
833 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
834 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
835 {
836 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
837 return buf->direct.buf + offset;
838 else
839 return buf->page_list[offset >> PAGE_SHIFT].buf +
840 (offset & (PAGE_SIZE - 1));
841 }
842
843 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
844 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
845 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
846 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
847
848 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
849 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
850 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
851 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
852
853 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
854 struct mlx4_mtt *mtt);
855 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
856 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
857
858 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
859 int npages, int page_shift, struct mlx4_mr *mr);
860 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
861 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
862 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
863 struct mlx4_mw *mw);
864 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
865 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
866 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
867 int start_index, int npages, u64 *page_list);
868 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
869 struct mlx4_buf *buf);
870
871 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
872 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
873
874 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
875 int size, int max_direct);
876 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
877 int size);
878
879 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
880 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
881 unsigned vector, int collapsed, int timestamp_en);
882 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
883
884 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
885 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
886
887 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
888 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
889
890 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
891 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
892 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
893 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
894 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
895
896 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
897 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
898
899 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
900 int block_mcast_loopback, enum mlx4_protocol prot);
901 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
902 enum mlx4_protocol prot);
903 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
904 u8 port, int block_mcast_loopback,
905 enum mlx4_protocol protocol, u64 *reg_id);
906 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
907 enum mlx4_protocol protocol, u64 reg_id);
908
909 enum {
910 MLX4_DOMAIN_UVERBS = 0x1000,
911 MLX4_DOMAIN_ETHTOOL = 0x2000,
912 MLX4_DOMAIN_RFS = 0x3000,
913 MLX4_DOMAIN_NIC = 0x5000,
914 };
915
916 enum mlx4_net_trans_rule_id {
917 MLX4_NET_TRANS_RULE_ID_ETH = 0,
918 MLX4_NET_TRANS_RULE_ID_IB,
919 MLX4_NET_TRANS_RULE_ID_IPV6,
920 MLX4_NET_TRANS_RULE_ID_IPV4,
921 MLX4_NET_TRANS_RULE_ID_TCP,
922 MLX4_NET_TRANS_RULE_ID_UDP,
923 MLX4_NET_TRANS_RULE_ID_VXLAN,
924 MLX4_NET_TRANS_RULE_NUM, /* should be last */
925 };
926
927 extern const u16 __sw_id_hw[];
928
929 static inline int map_hw_to_sw_id(u16 header_id)
930 {
931
932 int i;
933 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
934 if (header_id == __sw_id_hw[i])
935 return i;
936 }
937 return -EINVAL;
938 }
939
940 enum mlx4_net_trans_promisc_mode {
941 MLX4_FS_REGULAR = 1,
942 MLX4_FS_ALL_DEFAULT,
943 MLX4_FS_MC_DEFAULT,
944 MLX4_FS_UC_SNIFFER,
945 MLX4_FS_MC_SNIFFER,
946 MLX4_FS_MODE_NUM, /* should be last */
947 };
948
949 struct mlx4_spec_eth {
950 u8 dst_mac[ETH_ALEN];
951 u8 dst_mac_msk[ETH_ALEN];
952 u8 src_mac[ETH_ALEN];
953 u8 src_mac_msk[ETH_ALEN];
954 u8 ether_type_enable;
955 __be16 ether_type;
956 __be16 vlan_id_msk;
957 __be16 vlan_id;
958 };
959
960 struct mlx4_spec_tcp_udp {
961 __be16 dst_port;
962 __be16 dst_port_msk;
963 __be16 src_port;
964 __be16 src_port_msk;
965 };
966
967 struct mlx4_spec_ipv4 {
968 __be32 dst_ip;
969 __be32 dst_ip_msk;
970 __be32 src_ip;
971 __be32 src_ip_msk;
972 };
973
974 struct mlx4_spec_ib {
975 __be32 l3_qpn;
976 __be32 qpn_msk;
977 u8 dst_gid[16];
978 u8 dst_gid_msk[16];
979 };
980
981 struct mlx4_spec_vxlan {
982 __be32 vni;
983 __be32 vni_mask;
984
985 };
986
987 struct mlx4_spec_list {
988 struct list_head list;
989 enum mlx4_net_trans_rule_id id;
990 union {
991 struct mlx4_spec_eth eth;
992 struct mlx4_spec_ib ib;
993 struct mlx4_spec_ipv4 ipv4;
994 struct mlx4_spec_tcp_udp tcp_udp;
995 struct mlx4_spec_vxlan vxlan;
996 };
997 };
998
999 enum mlx4_net_trans_hw_rule_queue {
1000 MLX4_NET_TRANS_Q_FIFO,
1001 MLX4_NET_TRANS_Q_LIFO,
1002 };
1003
1004 struct mlx4_net_trans_rule {
1005 struct list_head list;
1006 enum mlx4_net_trans_hw_rule_queue queue_mode;
1007 bool exclusive;
1008 bool allow_loopback;
1009 enum mlx4_net_trans_promisc_mode promisc_mode;
1010 u8 port;
1011 u16 priority;
1012 u32 qpn;
1013 };
1014
1015 struct mlx4_net_trans_rule_hw_ctrl {
1016 __be16 prio;
1017 u8 type;
1018 u8 flags;
1019 u8 rsvd1;
1020 u8 funcid;
1021 u8 vep;
1022 u8 port;
1023 __be32 qpn;
1024 __be32 rsvd2;
1025 };
1026
1027 struct mlx4_net_trans_rule_hw_ib {
1028 u8 size;
1029 u8 rsvd1;
1030 __be16 id;
1031 u32 rsvd2;
1032 __be32 l3_qpn;
1033 __be32 qpn_mask;
1034 u8 dst_gid[16];
1035 u8 dst_gid_msk[16];
1036 } __packed;
1037
1038 struct mlx4_net_trans_rule_hw_eth {
1039 u8 size;
1040 u8 rsvd;
1041 __be16 id;
1042 u8 rsvd1[6];
1043 u8 dst_mac[6];
1044 u16 rsvd2;
1045 u8 dst_mac_msk[6];
1046 u16 rsvd3;
1047 u8 src_mac[6];
1048 u16 rsvd4;
1049 u8 src_mac_msk[6];
1050 u8 rsvd5;
1051 u8 ether_type_enable;
1052 __be16 ether_type;
1053 __be16 vlan_tag_msk;
1054 __be16 vlan_tag;
1055 } __packed;
1056
1057 struct mlx4_net_trans_rule_hw_tcp_udp {
1058 u8 size;
1059 u8 rsvd;
1060 __be16 id;
1061 __be16 rsvd1[3];
1062 __be16 dst_port;
1063 __be16 rsvd2;
1064 __be16 dst_port_msk;
1065 __be16 rsvd3;
1066 __be16 src_port;
1067 __be16 rsvd4;
1068 __be16 src_port_msk;
1069 } __packed;
1070
1071 struct mlx4_net_trans_rule_hw_ipv4 {
1072 u8 size;
1073 u8 rsvd;
1074 __be16 id;
1075 __be32 rsvd1;
1076 __be32 dst_ip;
1077 __be32 dst_ip_msk;
1078 __be32 src_ip;
1079 __be32 src_ip_msk;
1080 } __packed;
1081
1082 struct mlx4_net_trans_rule_hw_vxlan {
1083 u8 size;
1084 u8 rsvd;
1085 __be16 id;
1086 __be32 rsvd1;
1087 __be32 vni;
1088 __be32 vni_mask;
1089 } __packed;
1090
1091 struct _rule_hw {
1092 union {
1093 struct {
1094 u8 size;
1095 u8 rsvd;
1096 __be16 id;
1097 };
1098 struct mlx4_net_trans_rule_hw_eth eth;
1099 struct mlx4_net_trans_rule_hw_ib ib;
1100 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1101 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1102 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1103 };
1104 };
1105
1106 enum {
1107 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1108 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1109 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1110 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1111 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1112 };
1113
1114
1115 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1116 enum mlx4_net_trans_promisc_mode mode);
1117 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1118 enum mlx4_net_trans_promisc_mode mode);
1119 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1120 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1121 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1122 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1123 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1124
1125 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1126 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1127 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1128 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1129 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1130 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1131 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1132 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1133 u8 promisc);
1134 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1135 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1136 u8 *pg, u16 *ratelimit);
1137 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering);
1138 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1139 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1140 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1141 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1142
1143 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1144 int npages, u64 iova, u32 *lkey, u32 *rkey);
1145 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1146 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1147 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1148 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1149 u32 *lkey, u32 *rkey);
1150 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1151 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1152 int mlx4_test_interrupts(struct mlx4_dev *dev);
1153 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1154 int *vector);
1155 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1156
1157 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1158 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1159 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1160
1161 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1162 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1163
1164 int mlx4_flow_attach(struct mlx4_dev *dev,
1165 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1166 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1167 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1168 enum mlx4_net_trans_promisc_mode flow_type);
1169 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1170 enum mlx4_net_trans_rule_id id);
1171 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1172
1173 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1174 int i, int val);
1175
1176 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1177
1178 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1179 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1180 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1181 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1182 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1183 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1184 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1185
1186 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1187 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1188
1189 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1190 int *slave_id);
1191 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1192 u8 *gid);
1193
1194 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1195 u32 max_range_qpn);
1196
1197 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1198
1199 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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