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net/mlx4_core: Port aggregation upper layer interface
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
51
52 #define MLX4_NUM_UP 8
53 #define MLX4_NUM_TC 8
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
58 */
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
62
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
65
66 enum {
67 MLX4_FLAG_MSI_X = 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
69 MLX4_FLAG_MASTER = 1 << 2,
70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
73 MLX4_FLAG_BONDED = 1 << 7
74 };
75
76 enum {
77 MLX4_PORT_CAP_IS_SM = 1 << 1,
78 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
79 };
80
81 enum {
82 MLX4_MAX_PORTS = 2,
83 MLX4_MAX_PORT_PKEYS = 128
84 };
85
86 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
87 * These qkeys must not be allowed for general use. This is a 64k range,
88 * and to test for violation, we use the mask (protect against future chg).
89 */
90 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
91 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
92
93 enum {
94 MLX4_BOARD_ID_LEN = 64
95 };
96
97 enum {
98 MLX4_MAX_NUM_PF = 16,
99 MLX4_MAX_NUM_VF = 126,
100 MLX4_MAX_NUM_VF_P_PORT = 64,
101 MLX4_MFUNC_MAX = 80,
102 MLX4_MAX_EQ_NUM = 1024,
103 MLX4_MFUNC_EQ_NUM = 4,
104 MLX4_MFUNC_MAX_EQES = 8,
105 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
106 };
107
108 /* Driver supports 3 diffrent device methods to manage traffic steering:
109 * -device managed - High level API for ib and eth flow steering. FW is
110 * managing flow steering tables.
111 * - B0 steering mode - Common low level API for ib and (if supported) eth.
112 * - A0 steering mode - Limited low level API for eth. In case of IB,
113 * B0 mode is in use.
114 */
115 enum {
116 MLX4_STEERING_MODE_A0,
117 MLX4_STEERING_MODE_B0,
118 MLX4_STEERING_MODE_DEVICE_MANAGED
119 };
120
121 enum {
122 MLX4_STEERING_DMFS_A0_DEFAULT,
123 MLX4_STEERING_DMFS_A0_DYNAMIC,
124 MLX4_STEERING_DMFS_A0_STATIC,
125 MLX4_STEERING_DMFS_A0_DISABLE,
126 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
127 };
128
129 static inline const char *mlx4_steering_mode_str(int steering_mode)
130 {
131 switch (steering_mode) {
132 case MLX4_STEERING_MODE_A0:
133 return "A0 steering";
134
135 case MLX4_STEERING_MODE_B0:
136 return "B0 steering";
137
138 case MLX4_STEERING_MODE_DEVICE_MANAGED:
139 return "Device managed flow steering";
140
141 default:
142 return "Unrecognize steering mode";
143 }
144 }
145
146 enum {
147 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
148 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
149 };
150
151 enum {
152 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
153 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
154 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
155 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
156 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
157 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
158 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
159 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
160 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
161 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
162 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
163 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
164 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
165 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
166 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
167 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
168 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
169 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
170 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
171 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
172 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
173 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
174 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
175 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
176 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
177 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
178 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
179 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
180 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
181 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
182 };
183
184 enum {
185 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
186 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
187 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
188 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
189 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
190 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
191 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
192 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
193 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
194 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
195 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
196 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
197 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
198 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
199 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
200 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
201 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
202 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
203 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
204 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
205 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
206 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21
207 };
208
209 enum {
210 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
211 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
212 };
213
214 enum {
215 MLX4_VF_CAP_FLAG_RESET = 1 << 0
216 };
217
218 /* bit enums for an 8-bit flags field indicating special use
219 * QPs which require special handling in qp_reserve_range.
220 * Currently, this only includes QPs used by the ETH interface,
221 * where we expect to use blueflame. These QPs must not have
222 * bits 6 and 7 set in their qp number.
223 *
224 * This enum may use only bits 0..7.
225 */
226 enum {
227 MLX4_RESERVE_A0_QP = 1 << 6,
228 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
229 };
230
231 enum {
232 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
233 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
234 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
235 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
236 };
237
238 enum {
239 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
240 };
241
242 enum {
243 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
244 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
245 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
246 };
247
248
249 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
250
251 enum {
252 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
253 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
254 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
255 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
256 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
257 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
258 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
259 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
260 };
261
262 enum {
263 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
264 };
265
266 enum mlx4_event {
267 MLX4_EVENT_TYPE_COMP = 0x00,
268 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
269 MLX4_EVENT_TYPE_COMM_EST = 0x02,
270 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
271 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
272 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
273 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
274 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
275 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
276 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
277 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
278 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
279 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
280 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
281 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
282 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
283 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
284 MLX4_EVENT_TYPE_CMD = 0x0a,
285 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
286 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
287 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
288 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
289 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
290 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
291 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
292 MLX4_EVENT_TYPE_NONE = 0xff,
293 };
294
295 enum {
296 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
297 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
298 };
299
300 enum {
301 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
302 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
303 };
304
305 enum {
306 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
307 };
308
309 enum slave_port_state {
310 SLAVE_PORT_DOWN = 0,
311 SLAVE_PENDING_UP,
312 SLAVE_PORT_UP,
313 };
314
315 enum slave_port_gen_event {
316 SLAVE_PORT_GEN_EVENT_DOWN = 0,
317 SLAVE_PORT_GEN_EVENT_UP,
318 SLAVE_PORT_GEN_EVENT_NONE,
319 };
320
321 enum slave_port_state_event {
322 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
323 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
324 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
325 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
326 };
327
328 enum {
329 MLX4_PERM_LOCAL_READ = 1 << 10,
330 MLX4_PERM_LOCAL_WRITE = 1 << 11,
331 MLX4_PERM_REMOTE_READ = 1 << 12,
332 MLX4_PERM_REMOTE_WRITE = 1 << 13,
333 MLX4_PERM_ATOMIC = 1 << 14,
334 MLX4_PERM_BIND_MW = 1 << 15,
335 MLX4_PERM_MASK = 0xFC00
336 };
337
338 enum {
339 MLX4_OPCODE_NOP = 0x00,
340 MLX4_OPCODE_SEND_INVAL = 0x01,
341 MLX4_OPCODE_RDMA_WRITE = 0x08,
342 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
343 MLX4_OPCODE_SEND = 0x0a,
344 MLX4_OPCODE_SEND_IMM = 0x0b,
345 MLX4_OPCODE_LSO = 0x0e,
346 MLX4_OPCODE_RDMA_READ = 0x10,
347 MLX4_OPCODE_ATOMIC_CS = 0x11,
348 MLX4_OPCODE_ATOMIC_FA = 0x12,
349 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
350 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
351 MLX4_OPCODE_BIND_MW = 0x18,
352 MLX4_OPCODE_FMR = 0x19,
353 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
354 MLX4_OPCODE_CONFIG_CMD = 0x1f,
355
356 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
357 MLX4_RECV_OPCODE_SEND = 0x01,
358 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
359 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
360
361 MLX4_CQE_OPCODE_ERROR = 0x1e,
362 MLX4_CQE_OPCODE_RESIZE = 0x16,
363 };
364
365 enum {
366 MLX4_STAT_RATE_OFFSET = 5
367 };
368
369 enum mlx4_protocol {
370 MLX4_PROT_IB_IPV6 = 0,
371 MLX4_PROT_ETH,
372 MLX4_PROT_IB_IPV4,
373 MLX4_PROT_FCOE
374 };
375
376 enum {
377 MLX4_MTT_FLAG_PRESENT = 1
378 };
379
380 enum mlx4_qp_region {
381 MLX4_QP_REGION_FW = 0,
382 MLX4_QP_REGION_RSS_RAW_ETH,
383 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
384 MLX4_QP_REGION_ETH_ADDR,
385 MLX4_QP_REGION_FC_ADDR,
386 MLX4_QP_REGION_FC_EXCH,
387 MLX4_NUM_QP_REGION
388 };
389
390 enum mlx4_port_type {
391 MLX4_PORT_TYPE_NONE = 0,
392 MLX4_PORT_TYPE_IB = 1,
393 MLX4_PORT_TYPE_ETH = 2,
394 MLX4_PORT_TYPE_AUTO = 3
395 };
396
397 enum mlx4_special_vlan_idx {
398 MLX4_NO_VLAN_IDX = 0,
399 MLX4_VLAN_MISS_IDX,
400 MLX4_VLAN_REGULAR
401 };
402
403 enum mlx4_steer_type {
404 MLX4_MC_STEER = 0,
405 MLX4_UC_STEER,
406 MLX4_NUM_STEERS
407 };
408
409 enum {
410 MLX4_NUM_FEXCH = 64 * 1024,
411 };
412
413 enum {
414 MLX4_MAX_FAST_REG_PAGES = 511,
415 };
416
417 enum {
418 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
419 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
420 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
421 };
422
423 /* Port mgmt change event handling */
424 enum {
425 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
426 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
427 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
428 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
429 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
430 };
431
432 enum {
433 MLX4_DEVICE_STATE_UP = 1 << 0,
434 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
435 };
436
437 enum {
438 MLX4_INTERFACE_STATE_UP = 1 << 0,
439 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
440 };
441
442 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
443 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
444
445 enum mlx4_module_id {
446 MLX4_MODULE_ID_SFP = 0x3,
447 MLX4_MODULE_ID_QSFP = 0xC,
448 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
449 MLX4_MODULE_ID_QSFP28 = 0x11,
450 };
451
452 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
453 {
454 return (major << 32) | (minor << 16) | subminor;
455 }
456
457 struct mlx4_phys_caps {
458 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
459 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
460 u32 num_phys_eqs;
461 u32 base_sqpn;
462 u32 base_proxy_sqpn;
463 u32 base_tunnel_sqpn;
464 };
465
466 struct mlx4_caps {
467 u64 fw_ver;
468 u32 function;
469 int num_ports;
470 int vl_cap[MLX4_MAX_PORTS + 1];
471 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
472 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
473 u64 def_mac[MLX4_MAX_PORTS + 1];
474 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
475 int gid_table_len[MLX4_MAX_PORTS + 1];
476 int pkey_table_len[MLX4_MAX_PORTS + 1];
477 int trans_type[MLX4_MAX_PORTS + 1];
478 int vendor_oui[MLX4_MAX_PORTS + 1];
479 int wavelength[MLX4_MAX_PORTS + 1];
480 u64 trans_code[MLX4_MAX_PORTS + 1];
481 int local_ca_ack_delay;
482 int num_uars;
483 u32 uar_page_size;
484 int bf_reg_size;
485 int bf_regs_per_page;
486 int max_sq_sg;
487 int max_rq_sg;
488 int num_qps;
489 int max_wqes;
490 int max_sq_desc_sz;
491 int max_rq_desc_sz;
492 int max_qp_init_rdma;
493 int max_qp_dest_rdma;
494 u32 *qp0_qkey;
495 u32 *qp0_proxy;
496 u32 *qp1_proxy;
497 u32 *qp0_tunnel;
498 u32 *qp1_tunnel;
499 int num_srqs;
500 int max_srq_wqes;
501 int max_srq_sge;
502 int reserved_srqs;
503 int num_cqs;
504 int max_cqes;
505 int reserved_cqs;
506 int num_sys_eqs;
507 int num_eqs;
508 int reserved_eqs;
509 int num_comp_vectors;
510 int comp_pool;
511 int num_mpts;
512 int max_fmr_maps;
513 int num_mtts;
514 int fmr_reserved_mtts;
515 int reserved_mtts;
516 int reserved_mrws;
517 int reserved_uars;
518 int num_mgms;
519 int num_amgms;
520 int reserved_mcgs;
521 int num_qp_per_mgm;
522 int steering_mode;
523 int dmfs_high_steer_mode;
524 int fs_log_max_ucast_qp_range_size;
525 int num_pds;
526 int reserved_pds;
527 int max_xrcds;
528 int reserved_xrcds;
529 int mtt_entry_sz;
530 u32 max_msg_sz;
531 u32 page_size_cap;
532 u64 flags;
533 u64 flags2;
534 u32 bmme_flags;
535 u32 reserved_lkey;
536 u16 stat_rate_support;
537 u8 port_width_cap[MLX4_MAX_PORTS + 1];
538 int max_gso_sz;
539 int max_rss_tbl_sz;
540 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
541 int reserved_qps;
542 int reserved_qps_base[MLX4_NUM_QP_REGION];
543 int log_num_macs;
544 int log_num_vlans;
545 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
546 u8 supported_type[MLX4_MAX_PORTS + 1];
547 u8 suggested_type[MLX4_MAX_PORTS + 1];
548 u8 default_sense[MLX4_MAX_PORTS + 1];
549 u32 port_mask[MLX4_MAX_PORTS + 1];
550 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
551 u32 max_counters;
552 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
553 u16 sqp_demux;
554 u32 eqe_size;
555 u32 cqe_size;
556 u8 eqe_factor;
557 u32 userspace_caps; /* userspace must be aware of these */
558 u32 function_caps; /* VFs must be aware of these */
559 u16 hca_core_clock;
560 u64 phys_port_id[MLX4_MAX_PORTS + 1];
561 int tunnel_offload_mode;
562 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
563 u8 alloc_res_qp_mask;
564 u32 dmfs_high_rate_qpn_base;
565 u32 dmfs_high_rate_qpn_range;
566 u32 vf_caps;
567 };
568
569 struct mlx4_buf_list {
570 void *buf;
571 dma_addr_t map;
572 };
573
574 struct mlx4_buf {
575 struct mlx4_buf_list direct;
576 struct mlx4_buf_list *page_list;
577 int nbufs;
578 int npages;
579 int page_shift;
580 };
581
582 struct mlx4_mtt {
583 u32 offset;
584 int order;
585 int page_shift;
586 };
587
588 enum {
589 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
590 };
591
592 struct mlx4_db_pgdir {
593 struct list_head list;
594 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
595 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
596 unsigned long *bits[2];
597 __be32 *db_page;
598 dma_addr_t db_dma;
599 };
600
601 struct mlx4_ib_user_db_page;
602
603 struct mlx4_db {
604 __be32 *db;
605 union {
606 struct mlx4_db_pgdir *pgdir;
607 struct mlx4_ib_user_db_page *user_page;
608 } u;
609 dma_addr_t dma;
610 int index;
611 int order;
612 };
613
614 struct mlx4_hwq_resources {
615 struct mlx4_db db;
616 struct mlx4_mtt mtt;
617 struct mlx4_buf buf;
618 };
619
620 struct mlx4_mr {
621 struct mlx4_mtt mtt;
622 u64 iova;
623 u64 size;
624 u32 key;
625 u32 pd;
626 u32 access;
627 int enabled;
628 };
629
630 enum mlx4_mw_type {
631 MLX4_MW_TYPE_1 = 1,
632 MLX4_MW_TYPE_2 = 2,
633 };
634
635 struct mlx4_mw {
636 u32 key;
637 u32 pd;
638 enum mlx4_mw_type type;
639 int enabled;
640 };
641
642 struct mlx4_fmr {
643 struct mlx4_mr mr;
644 struct mlx4_mpt_entry *mpt;
645 __be64 *mtts;
646 dma_addr_t dma_handle;
647 int max_pages;
648 int max_maps;
649 int maps;
650 u8 page_shift;
651 };
652
653 struct mlx4_uar {
654 unsigned long pfn;
655 int index;
656 struct list_head bf_list;
657 unsigned free_bf_bmap;
658 void __iomem *map;
659 void __iomem *bf_map;
660 };
661
662 struct mlx4_bf {
663 unsigned int offset;
664 int buf_size;
665 struct mlx4_uar *uar;
666 void __iomem *reg;
667 };
668
669 struct mlx4_cq {
670 void (*comp) (struct mlx4_cq *);
671 void (*event) (struct mlx4_cq *, enum mlx4_event);
672
673 struct mlx4_uar *uar;
674
675 u32 cons_index;
676
677 u16 irq;
678 __be32 *set_ci_db;
679 __be32 *arm_db;
680 int arm_sn;
681
682 int cqn;
683 unsigned vector;
684
685 atomic_t refcount;
686 struct completion free;
687 struct {
688 struct list_head list;
689 void (*comp)(struct mlx4_cq *);
690 void *priv;
691 } tasklet_ctx;
692 };
693
694 struct mlx4_qp {
695 void (*event) (struct mlx4_qp *, enum mlx4_event);
696
697 int qpn;
698
699 atomic_t refcount;
700 struct completion free;
701 };
702
703 struct mlx4_srq {
704 void (*event) (struct mlx4_srq *, enum mlx4_event);
705
706 int srqn;
707 int max;
708 int max_gs;
709 int wqe_shift;
710
711 atomic_t refcount;
712 struct completion free;
713 };
714
715 struct mlx4_av {
716 __be32 port_pd;
717 u8 reserved1;
718 u8 g_slid;
719 __be16 dlid;
720 u8 reserved2;
721 u8 gid_index;
722 u8 stat_rate;
723 u8 hop_limit;
724 __be32 sl_tclass_flowlabel;
725 u8 dgid[16];
726 };
727
728 struct mlx4_eth_av {
729 __be32 port_pd;
730 u8 reserved1;
731 u8 smac_idx;
732 u16 reserved2;
733 u8 reserved3;
734 u8 gid_index;
735 u8 stat_rate;
736 u8 hop_limit;
737 __be32 sl_tclass_flowlabel;
738 u8 dgid[16];
739 u8 s_mac[6];
740 u8 reserved4[2];
741 __be16 vlan;
742 u8 mac[ETH_ALEN];
743 };
744
745 union mlx4_ext_av {
746 struct mlx4_av ib;
747 struct mlx4_eth_av eth;
748 };
749
750 struct mlx4_counter {
751 u8 reserved1[3];
752 u8 counter_mode;
753 __be32 num_ifc;
754 u32 reserved2[2];
755 __be64 rx_frames;
756 __be64 rx_bytes;
757 __be64 tx_frames;
758 __be64 tx_bytes;
759 };
760
761 struct mlx4_quotas {
762 int qp;
763 int cq;
764 int srq;
765 int mpt;
766 int mtt;
767 int counter;
768 int xrcd;
769 };
770
771 struct mlx4_vf_dev {
772 u8 min_port;
773 u8 n_ports;
774 };
775
776 struct mlx4_dev_persistent {
777 struct pci_dev *pdev;
778 struct mlx4_dev *dev;
779 int nvfs[MLX4_MAX_PORTS + 1];
780 int num_vfs;
781 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
782 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
783 struct work_struct catas_work;
784 struct workqueue_struct *catas_wq;
785 struct mutex device_state_mutex; /* protect HW state */
786 u8 state;
787 struct mutex interface_state_mutex; /* protect SW state */
788 u8 interface_state;
789 };
790
791 struct mlx4_dev {
792 struct mlx4_dev_persistent *persist;
793 unsigned long flags;
794 unsigned long num_slaves;
795 struct mlx4_caps caps;
796 struct mlx4_phys_caps phys_caps;
797 struct mlx4_quotas quotas;
798 struct radix_tree_root qp_table_tree;
799 u8 rev_id;
800 char board_id[MLX4_BOARD_ID_LEN];
801 int numa_node;
802 int oper_log_mgm_entry_size;
803 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
804 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
805 struct mlx4_vf_dev *dev_vfs;
806 };
807
808 struct mlx4_eqe {
809 u8 reserved1;
810 u8 type;
811 u8 reserved2;
812 u8 subtype;
813 union {
814 u32 raw[6];
815 struct {
816 __be32 cqn;
817 } __packed comp;
818 struct {
819 u16 reserved1;
820 __be16 token;
821 u32 reserved2;
822 u8 reserved3[3];
823 u8 status;
824 __be64 out_param;
825 } __packed cmd;
826 struct {
827 __be32 qpn;
828 } __packed qp;
829 struct {
830 __be32 srqn;
831 } __packed srq;
832 struct {
833 __be32 cqn;
834 u32 reserved1;
835 u8 reserved2[3];
836 u8 syndrome;
837 } __packed cq_err;
838 struct {
839 u32 reserved1[2];
840 __be32 port;
841 } __packed port_change;
842 struct {
843 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
844 u32 reserved;
845 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
846 } __packed comm_channel_arm;
847 struct {
848 u8 port;
849 u8 reserved[3];
850 __be64 mac;
851 } __packed mac_update;
852 struct {
853 __be32 slave_id;
854 } __packed flr_event;
855 struct {
856 __be16 current_temperature;
857 __be16 warning_threshold;
858 } __packed warming;
859 struct {
860 u8 reserved[3];
861 u8 port;
862 union {
863 struct {
864 __be16 mstr_sm_lid;
865 __be16 port_lid;
866 __be32 changed_attr;
867 u8 reserved[3];
868 u8 mstr_sm_sl;
869 __be64 gid_prefix;
870 } __packed port_info;
871 struct {
872 __be32 block_ptr;
873 __be32 tbl_entries_mask;
874 } __packed tbl_change_info;
875 } params;
876 } __packed port_mgmt_change;
877 struct {
878 u8 reserved[3];
879 u8 port;
880 u32 reserved1[5];
881 } __packed bad_cable;
882 } event;
883 u8 slave_id;
884 u8 reserved3[2];
885 u8 owner;
886 } __packed;
887
888 struct mlx4_init_port_param {
889 int set_guid0;
890 int set_node_guid;
891 int set_si_guid;
892 u16 mtu;
893 int port_width_cap;
894 u16 vl_cap;
895 u16 max_gid;
896 u16 max_pkey;
897 u64 guid0;
898 u64 node_guid;
899 u64 si_guid;
900 };
901
902 #define MAD_IFC_DATA_SZ 192
903 /* MAD IFC Mailbox */
904 struct mlx4_mad_ifc {
905 u8 base_version;
906 u8 mgmt_class;
907 u8 class_version;
908 u8 method;
909 __be16 status;
910 __be16 class_specific;
911 __be64 tid;
912 __be16 attr_id;
913 __be16 resv;
914 __be32 attr_mod;
915 __be64 mkey;
916 __be16 dr_slid;
917 __be16 dr_dlid;
918 u8 reserved[28];
919 u8 data[MAD_IFC_DATA_SZ];
920 } __packed;
921
922 #define mlx4_foreach_port(port, dev, type) \
923 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
924 if ((type) == (dev)->caps.port_mask[(port)])
925
926 #define mlx4_foreach_non_ib_transport_port(port, dev) \
927 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
928 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
929
930 #define mlx4_foreach_ib_transport_port(port, dev) \
931 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
932 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
933 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
934
935 #define MLX4_INVALID_SLAVE_ID 0xFF
936
937 void handle_port_mgmt_change_event(struct work_struct *work);
938
939 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
940 {
941 return dev->caps.function;
942 }
943
944 static inline int mlx4_is_master(struct mlx4_dev *dev)
945 {
946 return dev->flags & MLX4_FLAG_MASTER;
947 }
948
949 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
950 {
951 return dev->phys_caps.base_sqpn + 8 +
952 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
953 }
954
955 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
956 {
957 return (qpn < dev->phys_caps.base_sqpn + 8 +
958 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
959 qpn >= dev->phys_caps.base_sqpn) ||
960 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
961 }
962
963 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
964 {
965 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
966
967 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
968 return 1;
969
970 return 0;
971 }
972
973 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
974 {
975 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
976 }
977
978 static inline int mlx4_is_slave(struct mlx4_dev *dev)
979 {
980 return dev->flags & MLX4_FLAG_SLAVE;
981 }
982
983 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
984 struct mlx4_buf *buf, gfp_t gfp);
985 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
986 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
987 {
988 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
989 return buf->direct.buf + offset;
990 else
991 return buf->page_list[offset >> PAGE_SHIFT].buf +
992 (offset & (PAGE_SIZE - 1));
993 }
994
995 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
996 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
997 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
998 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
999
1000 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1001 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1002 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1003 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1004
1005 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1006 struct mlx4_mtt *mtt);
1007 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1008 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1009
1010 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1011 int npages, int page_shift, struct mlx4_mr *mr);
1012 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1013 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1014 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1015 struct mlx4_mw *mw);
1016 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1017 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1018 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1019 int start_index, int npages, u64 *page_list);
1020 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1021 struct mlx4_buf *buf, gfp_t gfp);
1022
1023 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1024 gfp_t gfp);
1025 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1026
1027 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1028 int size, int max_direct);
1029 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1030 int size);
1031
1032 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1033 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1034 unsigned vector, int collapsed, int timestamp_en);
1035 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1036 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1037 int *base, u8 flags);
1038 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1039
1040 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1041 gfp_t gfp);
1042 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1043
1044 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1045 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1046 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1047 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1048 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1049
1050 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1051 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1052
1053 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1054 int block_mcast_loopback, enum mlx4_protocol prot);
1055 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1056 enum mlx4_protocol prot);
1057 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1058 u8 port, int block_mcast_loopback,
1059 enum mlx4_protocol protocol, u64 *reg_id);
1060 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1061 enum mlx4_protocol protocol, u64 reg_id);
1062
1063 enum {
1064 MLX4_DOMAIN_UVERBS = 0x1000,
1065 MLX4_DOMAIN_ETHTOOL = 0x2000,
1066 MLX4_DOMAIN_RFS = 0x3000,
1067 MLX4_DOMAIN_NIC = 0x5000,
1068 };
1069
1070 enum mlx4_net_trans_rule_id {
1071 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1072 MLX4_NET_TRANS_RULE_ID_IB,
1073 MLX4_NET_TRANS_RULE_ID_IPV6,
1074 MLX4_NET_TRANS_RULE_ID_IPV4,
1075 MLX4_NET_TRANS_RULE_ID_TCP,
1076 MLX4_NET_TRANS_RULE_ID_UDP,
1077 MLX4_NET_TRANS_RULE_ID_VXLAN,
1078 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1079 };
1080
1081 extern const u16 __sw_id_hw[];
1082
1083 static inline int map_hw_to_sw_id(u16 header_id)
1084 {
1085
1086 int i;
1087 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1088 if (header_id == __sw_id_hw[i])
1089 return i;
1090 }
1091 return -EINVAL;
1092 }
1093
1094 enum mlx4_net_trans_promisc_mode {
1095 MLX4_FS_REGULAR = 1,
1096 MLX4_FS_ALL_DEFAULT,
1097 MLX4_FS_MC_DEFAULT,
1098 MLX4_FS_UC_SNIFFER,
1099 MLX4_FS_MC_SNIFFER,
1100 MLX4_FS_MODE_NUM, /* should be last */
1101 };
1102
1103 struct mlx4_spec_eth {
1104 u8 dst_mac[ETH_ALEN];
1105 u8 dst_mac_msk[ETH_ALEN];
1106 u8 src_mac[ETH_ALEN];
1107 u8 src_mac_msk[ETH_ALEN];
1108 u8 ether_type_enable;
1109 __be16 ether_type;
1110 __be16 vlan_id_msk;
1111 __be16 vlan_id;
1112 };
1113
1114 struct mlx4_spec_tcp_udp {
1115 __be16 dst_port;
1116 __be16 dst_port_msk;
1117 __be16 src_port;
1118 __be16 src_port_msk;
1119 };
1120
1121 struct mlx4_spec_ipv4 {
1122 __be32 dst_ip;
1123 __be32 dst_ip_msk;
1124 __be32 src_ip;
1125 __be32 src_ip_msk;
1126 };
1127
1128 struct mlx4_spec_ib {
1129 __be32 l3_qpn;
1130 __be32 qpn_msk;
1131 u8 dst_gid[16];
1132 u8 dst_gid_msk[16];
1133 };
1134
1135 struct mlx4_spec_vxlan {
1136 __be32 vni;
1137 __be32 vni_mask;
1138
1139 };
1140
1141 struct mlx4_spec_list {
1142 struct list_head list;
1143 enum mlx4_net_trans_rule_id id;
1144 union {
1145 struct mlx4_spec_eth eth;
1146 struct mlx4_spec_ib ib;
1147 struct mlx4_spec_ipv4 ipv4;
1148 struct mlx4_spec_tcp_udp tcp_udp;
1149 struct mlx4_spec_vxlan vxlan;
1150 };
1151 };
1152
1153 enum mlx4_net_trans_hw_rule_queue {
1154 MLX4_NET_TRANS_Q_FIFO,
1155 MLX4_NET_TRANS_Q_LIFO,
1156 };
1157
1158 struct mlx4_net_trans_rule {
1159 struct list_head list;
1160 enum mlx4_net_trans_hw_rule_queue queue_mode;
1161 bool exclusive;
1162 bool allow_loopback;
1163 enum mlx4_net_trans_promisc_mode promisc_mode;
1164 u8 port;
1165 u16 priority;
1166 u32 qpn;
1167 };
1168
1169 struct mlx4_net_trans_rule_hw_ctrl {
1170 __be16 prio;
1171 u8 type;
1172 u8 flags;
1173 u8 rsvd1;
1174 u8 funcid;
1175 u8 vep;
1176 u8 port;
1177 __be32 qpn;
1178 __be32 rsvd2;
1179 };
1180
1181 struct mlx4_net_trans_rule_hw_ib {
1182 u8 size;
1183 u8 rsvd1;
1184 __be16 id;
1185 u32 rsvd2;
1186 __be32 l3_qpn;
1187 __be32 qpn_mask;
1188 u8 dst_gid[16];
1189 u8 dst_gid_msk[16];
1190 } __packed;
1191
1192 struct mlx4_net_trans_rule_hw_eth {
1193 u8 size;
1194 u8 rsvd;
1195 __be16 id;
1196 u8 rsvd1[6];
1197 u8 dst_mac[6];
1198 u16 rsvd2;
1199 u8 dst_mac_msk[6];
1200 u16 rsvd3;
1201 u8 src_mac[6];
1202 u16 rsvd4;
1203 u8 src_mac_msk[6];
1204 u8 rsvd5;
1205 u8 ether_type_enable;
1206 __be16 ether_type;
1207 __be16 vlan_tag_msk;
1208 __be16 vlan_tag;
1209 } __packed;
1210
1211 struct mlx4_net_trans_rule_hw_tcp_udp {
1212 u8 size;
1213 u8 rsvd;
1214 __be16 id;
1215 __be16 rsvd1[3];
1216 __be16 dst_port;
1217 __be16 rsvd2;
1218 __be16 dst_port_msk;
1219 __be16 rsvd3;
1220 __be16 src_port;
1221 __be16 rsvd4;
1222 __be16 src_port_msk;
1223 } __packed;
1224
1225 struct mlx4_net_trans_rule_hw_ipv4 {
1226 u8 size;
1227 u8 rsvd;
1228 __be16 id;
1229 __be32 rsvd1;
1230 __be32 dst_ip;
1231 __be32 dst_ip_msk;
1232 __be32 src_ip;
1233 __be32 src_ip_msk;
1234 } __packed;
1235
1236 struct mlx4_net_trans_rule_hw_vxlan {
1237 u8 size;
1238 u8 rsvd;
1239 __be16 id;
1240 __be32 rsvd1;
1241 __be32 vni;
1242 __be32 vni_mask;
1243 } __packed;
1244
1245 struct _rule_hw {
1246 union {
1247 struct {
1248 u8 size;
1249 u8 rsvd;
1250 __be16 id;
1251 };
1252 struct mlx4_net_trans_rule_hw_eth eth;
1253 struct mlx4_net_trans_rule_hw_ib ib;
1254 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1255 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1256 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1257 };
1258 };
1259
1260 enum {
1261 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1262 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1263 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1264 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1265 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1266 };
1267
1268
1269 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1270 enum mlx4_net_trans_promisc_mode mode);
1271 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1272 enum mlx4_net_trans_promisc_mode mode);
1273 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1274 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1275 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1276 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1277 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1278
1279 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1280 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1281 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1282 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1283 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1284 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1285 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1286 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1287 u8 promisc);
1288 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1289 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1290 u8 *pg, u16 *ratelimit);
1291 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1292 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1293 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1294 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1295 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1296
1297 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1298 int npages, u64 iova, u32 *lkey, u32 *rkey);
1299 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1300 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1301 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1302 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1303 u32 *lkey, u32 *rkey);
1304 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1305 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1306 int mlx4_test_interrupts(struct mlx4_dev *dev);
1307 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1308 int *vector);
1309 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1310
1311 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1312
1313 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1314 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1315 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1316
1317 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1318 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1319
1320 int mlx4_flow_attach(struct mlx4_dev *dev,
1321 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1322 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1323 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1324 enum mlx4_net_trans_promisc_mode flow_type);
1325 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1326 enum mlx4_net_trans_rule_id id);
1327 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1328
1329 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1330 int port, int qpn, u16 prio, u64 *reg_id);
1331
1332 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1333 int i, int val);
1334
1335 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1336
1337 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1338 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1339 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1340 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1341 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1342 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1343 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1344
1345 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1346 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1347
1348 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1349 int *slave_id);
1350 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1351 u8 *gid);
1352
1353 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1354 u32 max_range_qpn);
1355
1356 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1357
1358 struct mlx4_active_ports {
1359 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1360 };
1361 /* Returns a bitmap of the physical ports which are assigned to slave */
1362 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1363
1364 /* Returns the physical port that represents the virtual port of the slave, */
1365 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1366 /* mapping is returned. */
1367 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1368
1369 struct mlx4_slaves_pport {
1370 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1371 };
1372 /* Returns a bitmap of all slaves that are assigned to port. */
1373 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1374 int port);
1375
1376 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1377 /* the ports that are set in crit_ports. */
1378 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1379 struct mlx4_dev *dev,
1380 const struct mlx4_active_ports *crit_ports);
1381
1382 /* Returns the slave's virtual port that represents the physical port. */
1383 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1384
1385 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1386
1387 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1388 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1389 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1390 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1391 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1392 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1393 int enable);
1394 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1395 struct mlx4_mpt_entry ***mpt_entry);
1396 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1397 struct mlx4_mpt_entry **mpt_entry);
1398 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1399 u32 pdn);
1400 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1401 struct mlx4_mpt_entry *mpt_entry,
1402 u32 access);
1403 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1404 struct mlx4_mpt_entry **mpt_entry);
1405 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1406 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1407 u64 iova, u64 size, int npages,
1408 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1409
1410 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1411 u16 offset, u16 size, u8 *data);
1412
1413 /* Returns true if running in low memory profile (kdump kernel) */
1414 static inline bool mlx4_low_memory_profile(void)
1415 {
1416 return is_kdump_kernel();
1417 }
1418
1419 /* ACCESS REG commands */
1420 enum mlx4_access_reg_method {
1421 MLX4_ACCESS_REG_QUERY = 0x1,
1422 MLX4_ACCESS_REG_WRITE = 0x2,
1423 };
1424
1425 /* ACCESS PTYS Reg command */
1426 enum mlx4_ptys_proto {
1427 MLX4_PTYS_IB = 1<<0,
1428 MLX4_PTYS_EN = 1<<2,
1429 };
1430
1431 struct mlx4_ptys_reg {
1432 u8 resrvd1;
1433 u8 local_port;
1434 u8 resrvd2;
1435 u8 proto_mask;
1436 __be32 resrvd3[2];
1437 __be32 eth_proto_cap;
1438 __be16 ib_width_cap;
1439 __be16 ib_speed_cap;
1440 __be32 resrvd4;
1441 __be32 eth_proto_admin;
1442 __be16 ib_width_admin;
1443 __be16 ib_speed_admin;
1444 __be32 resrvd5;
1445 __be32 eth_proto_oper;
1446 __be16 ib_width_oper;
1447 __be16 ib_speed_oper;
1448 __be32 resrvd6;
1449 __be32 eth_proto_lp_adv;
1450 } __packed;
1451
1452 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1453 enum mlx4_access_reg_method method,
1454 struct mlx4_ptys_reg *ptys_reg);
1455
1456 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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