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net/mlx4_core: Deprecate use_prio module parameter
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41
42 #include <linux/atomic.h>
43
44 #include <linux/clocksource.h>
45
46 #define MAX_MSIX_P_PORT 17
47 #define MAX_MSIX 64
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
50
51 #define MLX4_ROCE_MAX_GIDS 128
52 #define MLX4_ROCE_PF_GIDS 16
53
54 enum {
55 MLX4_FLAG_MSI_X = 1 << 0,
56 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
57 MLX4_FLAG_MASTER = 1 << 2,
58 MLX4_FLAG_SLAVE = 1 << 3,
59 MLX4_FLAG_SRIOV = 1 << 4,
60 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
61 };
62
63 enum {
64 MLX4_PORT_CAP_IS_SM = 1 << 1,
65 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
66 };
67
68 enum {
69 MLX4_MAX_PORTS = 2,
70 MLX4_MAX_PORT_PKEYS = 128
71 };
72
73 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
74 * These qkeys must not be allowed for general use. This is a 64k range,
75 * and to test for violation, we use the mask (protect against future chg).
76 */
77 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
78 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
79
80 enum {
81 MLX4_BOARD_ID_LEN = 64
82 };
83
84 enum {
85 MLX4_MAX_NUM_PF = 16,
86 MLX4_MAX_NUM_VF = 64,
87 MLX4_MAX_NUM_VF_P_PORT = 64,
88 MLX4_MFUNC_MAX = 80,
89 MLX4_MAX_EQ_NUM = 1024,
90 MLX4_MFUNC_EQ_NUM = 4,
91 MLX4_MFUNC_MAX_EQES = 8,
92 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
93 };
94
95 /* Driver supports 3 diffrent device methods to manage traffic steering:
96 * -device managed - High level API for ib and eth flow steering. FW is
97 * managing flow steering tables.
98 * - B0 steering mode - Common low level API for ib and (if supported) eth.
99 * - A0 steering mode - Limited low level API for eth. In case of IB,
100 * B0 mode is in use.
101 */
102 enum {
103 MLX4_STEERING_MODE_A0,
104 MLX4_STEERING_MODE_B0,
105 MLX4_STEERING_MODE_DEVICE_MANAGED
106 };
107
108 static inline const char *mlx4_steering_mode_str(int steering_mode)
109 {
110 switch (steering_mode) {
111 case MLX4_STEERING_MODE_A0:
112 return "A0 steering";
113
114 case MLX4_STEERING_MODE_B0:
115 return "B0 steering";
116
117 case MLX4_STEERING_MODE_DEVICE_MANAGED:
118 return "Device managed flow steering";
119
120 default:
121 return "Unrecognize steering mode";
122 }
123 }
124
125 enum {
126 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
127 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
128 };
129
130 enum {
131 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
132 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
133 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
134 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
135 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
136 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
137 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
138 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
139 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
140 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
141 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
142 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
143 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
144 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
145 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
146 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
147 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
148 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
149 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
150 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
151 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
152 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
153 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
154 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
155 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
156 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
157 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
158 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
159 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
160 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
161 };
162
163 enum {
164 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
165 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
166 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
167 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
168 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
169 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
170 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
171 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
172 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
173 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
174 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
175 };
176
177 enum {
178 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
179 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
180 };
181
182 enum {
183 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
184 };
185
186 enum {
187 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
188 };
189
190
191 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
192
193 enum {
194 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
195 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
196 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
197 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
198 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
199 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
200 };
201
202 enum mlx4_event {
203 MLX4_EVENT_TYPE_COMP = 0x00,
204 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
205 MLX4_EVENT_TYPE_COMM_EST = 0x02,
206 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
207 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
208 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
209 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
210 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
211 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
212 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
213 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
214 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
215 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
216 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
217 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
218 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
219 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
220 MLX4_EVENT_TYPE_CMD = 0x0a,
221 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
222 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
223 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
224 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
225 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
226 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
227 MLX4_EVENT_TYPE_NONE = 0xff,
228 };
229
230 enum {
231 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
232 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
233 };
234
235 enum {
236 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
237 };
238
239 enum slave_port_state {
240 SLAVE_PORT_DOWN = 0,
241 SLAVE_PENDING_UP,
242 SLAVE_PORT_UP,
243 };
244
245 enum slave_port_gen_event {
246 SLAVE_PORT_GEN_EVENT_DOWN = 0,
247 SLAVE_PORT_GEN_EVENT_UP,
248 SLAVE_PORT_GEN_EVENT_NONE,
249 };
250
251 enum slave_port_state_event {
252 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
253 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
254 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
255 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
256 };
257
258 enum {
259 MLX4_PERM_LOCAL_READ = 1 << 10,
260 MLX4_PERM_LOCAL_WRITE = 1 << 11,
261 MLX4_PERM_REMOTE_READ = 1 << 12,
262 MLX4_PERM_REMOTE_WRITE = 1 << 13,
263 MLX4_PERM_ATOMIC = 1 << 14,
264 MLX4_PERM_BIND_MW = 1 << 15,
265 };
266
267 enum {
268 MLX4_OPCODE_NOP = 0x00,
269 MLX4_OPCODE_SEND_INVAL = 0x01,
270 MLX4_OPCODE_RDMA_WRITE = 0x08,
271 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
272 MLX4_OPCODE_SEND = 0x0a,
273 MLX4_OPCODE_SEND_IMM = 0x0b,
274 MLX4_OPCODE_LSO = 0x0e,
275 MLX4_OPCODE_RDMA_READ = 0x10,
276 MLX4_OPCODE_ATOMIC_CS = 0x11,
277 MLX4_OPCODE_ATOMIC_FA = 0x12,
278 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
279 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
280 MLX4_OPCODE_BIND_MW = 0x18,
281 MLX4_OPCODE_FMR = 0x19,
282 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
283 MLX4_OPCODE_CONFIG_CMD = 0x1f,
284
285 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
286 MLX4_RECV_OPCODE_SEND = 0x01,
287 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
288 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
289
290 MLX4_CQE_OPCODE_ERROR = 0x1e,
291 MLX4_CQE_OPCODE_RESIZE = 0x16,
292 };
293
294 enum {
295 MLX4_STAT_RATE_OFFSET = 5
296 };
297
298 enum mlx4_protocol {
299 MLX4_PROT_IB_IPV6 = 0,
300 MLX4_PROT_ETH,
301 MLX4_PROT_IB_IPV4,
302 MLX4_PROT_FCOE
303 };
304
305 enum {
306 MLX4_MTT_FLAG_PRESENT = 1
307 };
308
309 enum mlx4_qp_region {
310 MLX4_QP_REGION_FW = 0,
311 MLX4_QP_REGION_ETH_ADDR,
312 MLX4_QP_REGION_FC_ADDR,
313 MLX4_QP_REGION_FC_EXCH,
314 MLX4_NUM_QP_REGION
315 };
316
317 enum mlx4_port_type {
318 MLX4_PORT_TYPE_NONE = 0,
319 MLX4_PORT_TYPE_IB = 1,
320 MLX4_PORT_TYPE_ETH = 2,
321 MLX4_PORT_TYPE_AUTO = 3
322 };
323
324 enum mlx4_special_vlan_idx {
325 MLX4_NO_VLAN_IDX = 0,
326 MLX4_VLAN_MISS_IDX,
327 MLX4_VLAN_REGULAR
328 };
329
330 enum mlx4_steer_type {
331 MLX4_MC_STEER = 0,
332 MLX4_UC_STEER,
333 MLX4_NUM_STEERS
334 };
335
336 enum {
337 MLX4_NUM_FEXCH = 64 * 1024,
338 };
339
340 enum {
341 MLX4_MAX_FAST_REG_PAGES = 511,
342 };
343
344 enum {
345 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
346 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
347 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
348 };
349
350 /* Port mgmt change event handling */
351 enum {
352 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
353 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
354 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
355 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
356 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
357 };
358
359 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
360 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
361
362 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
363 {
364 return (major << 32) | (minor << 16) | subminor;
365 }
366
367 struct mlx4_phys_caps {
368 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
369 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
370 u32 num_phys_eqs;
371 u32 base_sqpn;
372 u32 base_proxy_sqpn;
373 u32 base_tunnel_sqpn;
374 };
375
376 struct mlx4_caps {
377 u64 fw_ver;
378 u32 function;
379 int num_ports;
380 int vl_cap[MLX4_MAX_PORTS + 1];
381 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
382 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
383 u64 def_mac[MLX4_MAX_PORTS + 1];
384 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
385 int gid_table_len[MLX4_MAX_PORTS + 1];
386 int pkey_table_len[MLX4_MAX_PORTS + 1];
387 int trans_type[MLX4_MAX_PORTS + 1];
388 int vendor_oui[MLX4_MAX_PORTS + 1];
389 int wavelength[MLX4_MAX_PORTS + 1];
390 u64 trans_code[MLX4_MAX_PORTS + 1];
391 int local_ca_ack_delay;
392 int num_uars;
393 u32 uar_page_size;
394 int bf_reg_size;
395 int bf_regs_per_page;
396 int max_sq_sg;
397 int max_rq_sg;
398 int num_qps;
399 int max_wqes;
400 int max_sq_desc_sz;
401 int max_rq_desc_sz;
402 int max_qp_init_rdma;
403 int max_qp_dest_rdma;
404 u32 *qp0_proxy;
405 u32 *qp1_proxy;
406 u32 *qp0_tunnel;
407 u32 *qp1_tunnel;
408 int num_srqs;
409 int max_srq_wqes;
410 int max_srq_sge;
411 int reserved_srqs;
412 int num_cqs;
413 int max_cqes;
414 int reserved_cqs;
415 int num_eqs;
416 int reserved_eqs;
417 int num_comp_vectors;
418 int comp_pool;
419 int num_mpts;
420 int max_fmr_maps;
421 int num_mtts;
422 int fmr_reserved_mtts;
423 int reserved_mtts;
424 int reserved_mrws;
425 int reserved_uars;
426 int num_mgms;
427 int num_amgms;
428 int reserved_mcgs;
429 int num_qp_per_mgm;
430 int steering_mode;
431 int fs_log_max_ucast_qp_range_size;
432 int num_pds;
433 int reserved_pds;
434 int max_xrcds;
435 int reserved_xrcds;
436 int mtt_entry_sz;
437 u32 max_msg_sz;
438 u32 page_size_cap;
439 u64 flags;
440 u64 flags2;
441 u32 bmme_flags;
442 u32 reserved_lkey;
443 u16 stat_rate_support;
444 u8 port_width_cap[MLX4_MAX_PORTS + 1];
445 int max_gso_sz;
446 int max_rss_tbl_sz;
447 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
448 int reserved_qps;
449 int reserved_qps_base[MLX4_NUM_QP_REGION];
450 int log_num_macs;
451 int log_num_vlans;
452 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
453 u8 supported_type[MLX4_MAX_PORTS + 1];
454 u8 suggested_type[MLX4_MAX_PORTS + 1];
455 u8 default_sense[MLX4_MAX_PORTS + 1];
456 u32 port_mask[MLX4_MAX_PORTS + 1];
457 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
458 u32 max_counters;
459 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
460 u16 sqp_demux;
461 u32 eqe_size;
462 u32 cqe_size;
463 u8 eqe_factor;
464 u32 userspace_caps; /* userspace must be aware of these */
465 u32 function_caps; /* VFs must be aware of these */
466 u16 hca_core_clock;
467 u64 phys_port_id[MLX4_MAX_PORTS + 1];
468 int tunnel_offload_mode;
469 };
470
471 struct mlx4_buf_list {
472 void *buf;
473 dma_addr_t map;
474 };
475
476 struct mlx4_buf {
477 struct mlx4_buf_list direct;
478 struct mlx4_buf_list *page_list;
479 int nbufs;
480 int npages;
481 int page_shift;
482 };
483
484 struct mlx4_mtt {
485 u32 offset;
486 int order;
487 int page_shift;
488 };
489
490 enum {
491 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
492 };
493
494 struct mlx4_db_pgdir {
495 struct list_head list;
496 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
497 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
498 unsigned long *bits[2];
499 __be32 *db_page;
500 dma_addr_t db_dma;
501 };
502
503 struct mlx4_ib_user_db_page;
504
505 struct mlx4_db {
506 __be32 *db;
507 union {
508 struct mlx4_db_pgdir *pgdir;
509 struct mlx4_ib_user_db_page *user_page;
510 } u;
511 dma_addr_t dma;
512 int index;
513 int order;
514 };
515
516 struct mlx4_hwq_resources {
517 struct mlx4_db db;
518 struct mlx4_mtt mtt;
519 struct mlx4_buf buf;
520 };
521
522 struct mlx4_mr {
523 struct mlx4_mtt mtt;
524 u64 iova;
525 u64 size;
526 u32 key;
527 u32 pd;
528 u32 access;
529 int enabled;
530 };
531
532 enum mlx4_mw_type {
533 MLX4_MW_TYPE_1 = 1,
534 MLX4_MW_TYPE_2 = 2,
535 };
536
537 struct mlx4_mw {
538 u32 key;
539 u32 pd;
540 enum mlx4_mw_type type;
541 int enabled;
542 };
543
544 struct mlx4_fmr {
545 struct mlx4_mr mr;
546 struct mlx4_mpt_entry *mpt;
547 __be64 *mtts;
548 dma_addr_t dma_handle;
549 int max_pages;
550 int max_maps;
551 int maps;
552 u8 page_shift;
553 };
554
555 struct mlx4_uar {
556 unsigned long pfn;
557 int index;
558 struct list_head bf_list;
559 unsigned free_bf_bmap;
560 void __iomem *map;
561 void __iomem *bf_map;
562 };
563
564 struct mlx4_bf {
565 unsigned long offset;
566 int buf_size;
567 struct mlx4_uar *uar;
568 void __iomem *reg;
569 };
570
571 struct mlx4_cq {
572 void (*comp) (struct mlx4_cq *);
573 void (*event) (struct mlx4_cq *, enum mlx4_event);
574
575 struct mlx4_uar *uar;
576
577 u32 cons_index;
578
579 u16 irq;
580 bool irq_affinity_change;
581
582 __be32 *set_ci_db;
583 __be32 *arm_db;
584 int arm_sn;
585
586 int cqn;
587 unsigned vector;
588
589 atomic_t refcount;
590 struct completion free;
591 };
592
593 struct mlx4_qp {
594 void (*event) (struct mlx4_qp *, enum mlx4_event);
595
596 int qpn;
597
598 atomic_t refcount;
599 struct completion free;
600 };
601
602 struct mlx4_srq {
603 void (*event) (struct mlx4_srq *, enum mlx4_event);
604
605 int srqn;
606 int max;
607 int max_gs;
608 int wqe_shift;
609
610 atomic_t refcount;
611 struct completion free;
612 };
613
614 struct mlx4_av {
615 __be32 port_pd;
616 u8 reserved1;
617 u8 g_slid;
618 __be16 dlid;
619 u8 reserved2;
620 u8 gid_index;
621 u8 stat_rate;
622 u8 hop_limit;
623 __be32 sl_tclass_flowlabel;
624 u8 dgid[16];
625 };
626
627 struct mlx4_eth_av {
628 __be32 port_pd;
629 u8 reserved1;
630 u8 smac_idx;
631 u16 reserved2;
632 u8 reserved3;
633 u8 gid_index;
634 u8 stat_rate;
635 u8 hop_limit;
636 __be32 sl_tclass_flowlabel;
637 u8 dgid[16];
638 u8 s_mac[6];
639 u8 reserved4[2];
640 __be16 vlan;
641 u8 mac[ETH_ALEN];
642 };
643
644 union mlx4_ext_av {
645 struct mlx4_av ib;
646 struct mlx4_eth_av eth;
647 };
648
649 struct mlx4_counter {
650 u8 reserved1[3];
651 u8 counter_mode;
652 __be32 num_ifc;
653 u32 reserved2[2];
654 __be64 rx_frames;
655 __be64 rx_bytes;
656 __be64 tx_frames;
657 __be64 tx_bytes;
658 };
659
660 struct mlx4_quotas {
661 int qp;
662 int cq;
663 int srq;
664 int mpt;
665 int mtt;
666 int counter;
667 int xrcd;
668 };
669
670 struct mlx4_vf_dev {
671 u8 min_port;
672 u8 n_ports;
673 };
674
675 struct mlx4_dev {
676 struct pci_dev *pdev;
677 unsigned long flags;
678 unsigned long num_slaves;
679 struct mlx4_caps caps;
680 struct mlx4_phys_caps phys_caps;
681 struct mlx4_quotas quotas;
682 struct radix_tree_root qp_table_tree;
683 u8 rev_id;
684 char board_id[MLX4_BOARD_ID_LEN];
685 int num_vfs;
686 int numa_node;
687 int oper_log_mgm_entry_size;
688 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
689 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
690 struct mlx4_vf_dev *dev_vfs;
691 };
692
693 struct mlx4_eqe {
694 u8 reserved1;
695 u8 type;
696 u8 reserved2;
697 u8 subtype;
698 union {
699 u32 raw[6];
700 struct {
701 __be32 cqn;
702 } __packed comp;
703 struct {
704 u16 reserved1;
705 __be16 token;
706 u32 reserved2;
707 u8 reserved3[3];
708 u8 status;
709 __be64 out_param;
710 } __packed cmd;
711 struct {
712 __be32 qpn;
713 } __packed qp;
714 struct {
715 __be32 srqn;
716 } __packed srq;
717 struct {
718 __be32 cqn;
719 u32 reserved1;
720 u8 reserved2[3];
721 u8 syndrome;
722 } __packed cq_err;
723 struct {
724 u32 reserved1[2];
725 __be32 port;
726 } __packed port_change;
727 struct {
728 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
729 u32 reserved;
730 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
731 } __packed comm_channel_arm;
732 struct {
733 u8 port;
734 u8 reserved[3];
735 __be64 mac;
736 } __packed mac_update;
737 struct {
738 __be32 slave_id;
739 } __packed flr_event;
740 struct {
741 __be16 current_temperature;
742 __be16 warning_threshold;
743 } __packed warming;
744 struct {
745 u8 reserved[3];
746 u8 port;
747 union {
748 struct {
749 __be16 mstr_sm_lid;
750 __be16 port_lid;
751 __be32 changed_attr;
752 u8 reserved[3];
753 u8 mstr_sm_sl;
754 __be64 gid_prefix;
755 } __packed port_info;
756 struct {
757 __be32 block_ptr;
758 __be32 tbl_entries_mask;
759 } __packed tbl_change_info;
760 } params;
761 } __packed port_mgmt_change;
762 } event;
763 u8 slave_id;
764 u8 reserved3[2];
765 u8 owner;
766 } __packed;
767
768 struct mlx4_init_port_param {
769 int set_guid0;
770 int set_node_guid;
771 int set_si_guid;
772 u16 mtu;
773 int port_width_cap;
774 u16 vl_cap;
775 u16 max_gid;
776 u16 max_pkey;
777 u64 guid0;
778 u64 node_guid;
779 u64 si_guid;
780 };
781
782 #define mlx4_foreach_port(port, dev, type) \
783 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
784 if ((type) == (dev)->caps.port_mask[(port)])
785
786 #define mlx4_foreach_non_ib_transport_port(port, dev) \
787 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
788 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
789
790 #define mlx4_foreach_ib_transport_port(port, dev) \
791 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
792 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
793 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
794
795 #define MLX4_INVALID_SLAVE_ID 0xFF
796
797 void handle_port_mgmt_change_event(struct work_struct *work);
798
799 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
800 {
801 return dev->caps.function;
802 }
803
804 static inline int mlx4_is_master(struct mlx4_dev *dev)
805 {
806 return dev->flags & MLX4_FLAG_MASTER;
807 }
808
809 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
810 {
811 return dev->phys_caps.base_sqpn + 8 +
812 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
813 }
814
815 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
816 {
817 return (qpn < dev->phys_caps.base_sqpn + 8 +
818 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
819 }
820
821 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
822 {
823 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
824
825 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
826 return 1;
827
828 return 0;
829 }
830
831 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
832 {
833 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
834 }
835
836 static inline int mlx4_is_slave(struct mlx4_dev *dev)
837 {
838 return dev->flags & MLX4_FLAG_SLAVE;
839 }
840
841 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
842 struct mlx4_buf *buf);
843 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
844 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
845 {
846 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
847 return buf->direct.buf + offset;
848 else
849 return buf->page_list[offset >> PAGE_SHIFT].buf +
850 (offset & (PAGE_SIZE - 1));
851 }
852
853 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
854 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
855 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
856 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
857
858 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
859 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
860 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
861 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
862
863 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
864 struct mlx4_mtt *mtt);
865 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
866 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
867
868 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
869 int npages, int page_shift, struct mlx4_mr *mr);
870 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
871 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
872 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
873 struct mlx4_mw *mw);
874 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
875 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
876 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
877 int start_index, int npages, u64 *page_list);
878 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
879 struct mlx4_buf *buf);
880
881 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
882 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
883
884 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
885 int size, int max_direct);
886 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
887 int size);
888
889 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
890 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
891 unsigned vector, int collapsed, int timestamp_en);
892 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
893
894 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
895 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
896
897 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
898 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
899
900 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
901 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
902 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
903 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
904 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
905
906 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
907 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
908
909 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
910 int block_mcast_loopback, enum mlx4_protocol prot);
911 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
912 enum mlx4_protocol prot);
913 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
914 u8 port, int block_mcast_loopback,
915 enum mlx4_protocol protocol, u64 *reg_id);
916 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
917 enum mlx4_protocol protocol, u64 reg_id);
918
919 enum {
920 MLX4_DOMAIN_UVERBS = 0x1000,
921 MLX4_DOMAIN_ETHTOOL = 0x2000,
922 MLX4_DOMAIN_RFS = 0x3000,
923 MLX4_DOMAIN_NIC = 0x5000,
924 };
925
926 enum mlx4_net_trans_rule_id {
927 MLX4_NET_TRANS_RULE_ID_ETH = 0,
928 MLX4_NET_TRANS_RULE_ID_IB,
929 MLX4_NET_TRANS_RULE_ID_IPV6,
930 MLX4_NET_TRANS_RULE_ID_IPV4,
931 MLX4_NET_TRANS_RULE_ID_TCP,
932 MLX4_NET_TRANS_RULE_ID_UDP,
933 MLX4_NET_TRANS_RULE_ID_VXLAN,
934 MLX4_NET_TRANS_RULE_NUM, /* should be last */
935 };
936
937 extern const u16 __sw_id_hw[];
938
939 static inline int map_hw_to_sw_id(u16 header_id)
940 {
941
942 int i;
943 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
944 if (header_id == __sw_id_hw[i])
945 return i;
946 }
947 return -EINVAL;
948 }
949
950 enum mlx4_net_trans_promisc_mode {
951 MLX4_FS_REGULAR = 1,
952 MLX4_FS_ALL_DEFAULT,
953 MLX4_FS_MC_DEFAULT,
954 MLX4_FS_UC_SNIFFER,
955 MLX4_FS_MC_SNIFFER,
956 MLX4_FS_MODE_NUM, /* should be last */
957 };
958
959 struct mlx4_spec_eth {
960 u8 dst_mac[ETH_ALEN];
961 u8 dst_mac_msk[ETH_ALEN];
962 u8 src_mac[ETH_ALEN];
963 u8 src_mac_msk[ETH_ALEN];
964 u8 ether_type_enable;
965 __be16 ether_type;
966 __be16 vlan_id_msk;
967 __be16 vlan_id;
968 };
969
970 struct mlx4_spec_tcp_udp {
971 __be16 dst_port;
972 __be16 dst_port_msk;
973 __be16 src_port;
974 __be16 src_port_msk;
975 };
976
977 struct mlx4_spec_ipv4 {
978 __be32 dst_ip;
979 __be32 dst_ip_msk;
980 __be32 src_ip;
981 __be32 src_ip_msk;
982 };
983
984 struct mlx4_spec_ib {
985 __be32 l3_qpn;
986 __be32 qpn_msk;
987 u8 dst_gid[16];
988 u8 dst_gid_msk[16];
989 };
990
991 struct mlx4_spec_vxlan {
992 __be32 vni;
993 __be32 vni_mask;
994
995 };
996
997 struct mlx4_spec_list {
998 struct list_head list;
999 enum mlx4_net_trans_rule_id id;
1000 union {
1001 struct mlx4_spec_eth eth;
1002 struct mlx4_spec_ib ib;
1003 struct mlx4_spec_ipv4 ipv4;
1004 struct mlx4_spec_tcp_udp tcp_udp;
1005 struct mlx4_spec_vxlan vxlan;
1006 };
1007 };
1008
1009 enum mlx4_net_trans_hw_rule_queue {
1010 MLX4_NET_TRANS_Q_FIFO,
1011 MLX4_NET_TRANS_Q_LIFO,
1012 };
1013
1014 struct mlx4_net_trans_rule {
1015 struct list_head list;
1016 enum mlx4_net_trans_hw_rule_queue queue_mode;
1017 bool exclusive;
1018 bool allow_loopback;
1019 enum mlx4_net_trans_promisc_mode promisc_mode;
1020 u8 port;
1021 u16 priority;
1022 u32 qpn;
1023 };
1024
1025 struct mlx4_net_trans_rule_hw_ctrl {
1026 __be16 prio;
1027 u8 type;
1028 u8 flags;
1029 u8 rsvd1;
1030 u8 funcid;
1031 u8 vep;
1032 u8 port;
1033 __be32 qpn;
1034 __be32 rsvd2;
1035 };
1036
1037 struct mlx4_net_trans_rule_hw_ib {
1038 u8 size;
1039 u8 rsvd1;
1040 __be16 id;
1041 u32 rsvd2;
1042 __be32 l3_qpn;
1043 __be32 qpn_mask;
1044 u8 dst_gid[16];
1045 u8 dst_gid_msk[16];
1046 } __packed;
1047
1048 struct mlx4_net_trans_rule_hw_eth {
1049 u8 size;
1050 u8 rsvd;
1051 __be16 id;
1052 u8 rsvd1[6];
1053 u8 dst_mac[6];
1054 u16 rsvd2;
1055 u8 dst_mac_msk[6];
1056 u16 rsvd3;
1057 u8 src_mac[6];
1058 u16 rsvd4;
1059 u8 src_mac_msk[6];
1060 u8 rsvd5;
1061 u8 ether_type_enable;
1062 __be16 ether_type;
1063 __be16 vlan_tag_msk;
1064 __be16 vlan_tag;
1065 } __packed;
1066
1067 struct mlx4_net_trans_rule_hw_tcp_udp {
1068 u8 size;
1069 u8 rsvd;
1070 __be16 id;
1071 __be16 rsvd1[3];
1072 __be16 dst_port;
1073 __be16 rsvd2;
1074 __be16 dst_port_msk;
1075 __be16 rsvd3;
1076 __be16 src_port;
1077 __be16 rsvd4;
1078 __be16 src_port_msk;
1079 } __packed;
1080
1081 struct mlx4_net_trans_rule_hw_ipv4 {
1082 u8 size;
1083 u8 rsvd;
1084 __be16 id;
1085 __be32 rsvd1;
1086 __be32 dst_ip;
1087 __be32 dst_ip_msk;
1088 __be32 src_ip;
1089 __be32 src_ip_msk;
1090 } __packed;
1091
1092 struct mlx4_net_trans_rule_hw_vxlan {
1093 u8 size;
1094 u8 rsvd;
1095 __be16 id;
1096 __be32 rsvd1;
1097 __be32 vni;
1098 __be32 vni_mask;
1099 } __packed;
1100
1101 struct _rule_hw {
1102 union {
1103 struct {
1104 u8 size;
1105 u8 rsvd;
1106 __be16 id;
1107 };
1108 struct mlx4_net_trans_rule_hw_eth eth;
1109 struct mlx4_net_trans_rule_hw_ib ib;
1110 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1111 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1112 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1113 };
1114 };
1115
1116 enum {
1117 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1118 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1119 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1120 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1121 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1122 };
1123
1124
1125 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1126 enum mlx4_net_trans_promisc_mode mode);
1127 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1128 enum mlx4_net_trans_promisc_mode mode);
1129 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1130 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1131 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1132 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1133 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1134
1135 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1136 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1137 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1138 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1139 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1140 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1141 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1142 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1143 u8 promisc);
1144 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1145 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1146 u8 *pg, u16 *ratelimit);
1147 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1148 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1149 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1150 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1151 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1152
1153 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1154 int npages, u64 iova, u32 *lkey, u32 *rkey);
1155 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1156 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1157 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1158 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1159 u32 *lkey, u32 *rkey);
1160 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1161 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1162 int mlx4_test_interrupts(struct mlx4_dev *dev);
1163 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1164 int *vector);
1165 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1166
1167 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1168 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1169 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1170
1171 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1172 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1173
1174 int mlx4_flow_attach(struct mlx4_dev *dev,
1175 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1176 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1177 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1178 enum mlx4_net_trans_promisc_mode flow_type);
1179 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1180 enum mlx4_net_trans_rule_id id);
1181 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1182
1183 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1184 int i, int val);
1185
1186 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1187
1188 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1189 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1190 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1191 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1192 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1193 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1194 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1195
1196 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1197 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1198
1199 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1200 int *slave_id);
1201 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1202 u8 *gid);
1203
1204 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1205 u32 max_range_qpn);
1206
1207 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1208
1209 struct mlx4_active_ports {
1210 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1211 };
1212 /* Returns a bitmap of the physical ports which are assigned to slave */
1213 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1214
1215 /* Returns the physical port that represents the virtual port of the slave, */
1216 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1217 /* mapping is returned. */
1218 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1219
1220 struct mlx4_slaves_pport {
1221 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1222 };
1223 /* Returns a bitmap of all slaves that are assigned to port. */
1224 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1225 int port);
1226
1227 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1228 /* the ports that are set in crit_ports. */
1229 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1230 struct mlx4_dev *dev,
1231 const struct mlx4_active_ports *crit_ports);
1232
1233 /* Returns the slave's virtual port that represents the physical port. */
1234 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1235
1236 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1237
1238 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1239 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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