projects / deliverable / linux.git / blob
? search:


d9afd99dde397d0d05e59e365d6ed7edf672a6a5
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
51
52 #define MLX4_NUM_UP 8
53 #define MLX4_NUM_TC 8
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
58 */
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
62
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
65
66 enum {
67 MLX4_FLAG_MSI_X = 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
69 MLX4_FLAG_MASTER = 1 << 2,
70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
73 };
74
75 enum {
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
78 };
79
80 enum {
81 MLX4_MAX_PORTS = 2,
82 MLX4_MAX_PORT_PKEYS = 128
83 };
84
85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
86 * These qkeys must not be allowed for general use. This is a 64k range,
87 * and to test for violation, we use the mask (protect against future chg).
88 */
89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
91
92 enum {
93 MLX4_BOARD_ID_LEN = 64
94 };
95
96 enum {
97 MLX4_MAX_NUM_PF = 16,
98 MLX4_MAX_NUM_VF = 126,
99 MLX4_MAX_NUM_VF_P_PORT = 64,
100 MLX4_MFUNC_MAX = 80,
101 MLX4_MAX_EQ_NUM = 1024,
102 MLX4_MFUNC_EQ_NUM = 4,
103 MLX4_MFUNC_MAX_EQES = 8,
104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
105 };
106
107 /* Driver supports 3 diffrent device methods to manage traffic steering:
108 * -device managed - High level API for ib and eth flow steering. FW is
109 * managing flow steering tables.
110 * - B0 steering mode - Common low level API for ib and (if supported) eth.
111 * - A0 steering mode - Limited low level API for eth. In case of IB,
112 * B0 mode is in use.
113 */
114 enum {
115 MLX4_STEERING_MODE_A0,
116 MLX4_STEERING_MODE_B0,
117 MLX4_STEERING_MODE_DEVICE_MANAGED
118 };
119
120 enum {
121 MLX4_STEERING_DMFS_A0_DEFAULT,
122 MLX4_STEERING_DMFS_A0_DYNAMIC,
123 MLX4_STEERING_DMFS_A0_STATIC,
124 MLX4_STEERING_DMFS_A0_DISABLE,
125 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
126 };
127
128 static inline const char *mlx4_steering_mode_str(int steering_mode)
129 {
130 switch (steering_mode) {
131 case MLX4_STEERING_MODE_A0:
132 return "A0 steering";
133
134 case MLX4_STEERING_MODE_B0:
135 return "B0 steering";
136
137 case MLX4_STEERING_MODE_DEVICE_MANAGED:
138 return "Device managed flow steering";
139
140 default:
141 return "Unrecognize steering mode";
142 }
143 }
144
145 enum {
146 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
147 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
148 };
149
150 enum {
151 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
152 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
153 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
154 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
155 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
156 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
157 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
158 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
159 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
160 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
161 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
162 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
163 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
164 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
165 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
166 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
167 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
168 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
169 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
170 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
171 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
172 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
173 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
174 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
175 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
176 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
177 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
178 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
179 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
180 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
181 };
182
183 enum {
184 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
185 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
186 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
187 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
188 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
190 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
191 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
192 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
193 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
194 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
195 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
196 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
197 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
198 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
199 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
201 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
202 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
203 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
204 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
205 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21
206 };
207
208 enum {
209 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
210 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
211 };
212
213 enum {
214 MLX4_VF_CAP_FLAG_RESET = 1 << 0
215 };
216
217 /* bit enums for an 8-bit flags field indicating special use
218 * QPs which require special handling in qp_reserve_range.
219 * Currently, this only includes QPs used by the ETH interface,
220 * where we expect to use blueflame. These QPs must not have
221 * bits 6 and 7 set in their qp number.
222 *
223 * This enum may use only bits 0..7.
224 */
225 enum {
226 MLX4_RESERVE_A0_QP = 1 << 6,
227 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
228 };
229
230 enum {
231 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
232 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
233 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
234 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
235 };
236
237 enum {
238 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
239 };
240
241 enum {
242 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
243 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
244 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
245 };
246
247
248 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
249
250 enum {
251 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
252 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
253 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
254 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
255 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
256 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
257 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
258 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
259 };
260
261 enum {
262 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
263 };
264
265 enum mlx4_event {
266 MLX4_EVENT_TYPE_COMP = 0x00,
267 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
268 MLX4_EVENT_TYPE_COMM_EST = 0x02,
269 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
270 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
271 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
272 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
273 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
274 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
275 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
276 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
277 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
278 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
279 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
280 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
281 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
282 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
283 MLX4_EVENT_TYPE_CMD = 0x0a,
284 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
285 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
286 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
287 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
288 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
289 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
290 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
291 MLX4_EVENT_TYPE_NONE = 0xff,
292 };
293
294 enum {
295 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
296 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
297 };
298
299 enum {
300 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
301 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
302 };
303
304 enum {
305 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
306 };
307
308 enum slave_port_state {
309 SLAVE_PORT_DOWN = 0,
310 SLAVE_PENDING_UP,
311 SLAVE_PORT_UP,
312 };
313
314 enum slave_port_gen_event {
315 SLAVE_PORT_GEN_EVENT_DOWN = 0,
316 SLAVE_PORT_GEN_EVENT_UP,
317 SLAVE_PORT_GEN_EVENT_NONE,
318 };
319
320 enum slave_port_state_event {
321 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
322 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
323 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
324 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
325 };
326
327 enum {
328 MLX4_PERM_LOCAL_READ = 1 << 10,
329 MLX4_PERM_LOCAL_WRITE = 1 << 11,
330 MLX4_PERM_REMOTE_READ = 1 << 12,
331 MLX4_PERM_REMOTE_WRITE = 1 << 13,
332 MLX4_PERM_ATOMIC = 1 << 14,
333 MLX4_PERM_BIND_MW = 1 << 15,
334 MLX4_PERM_MASK = 0xFC00
335 };
336
337 enum {
338 MLX4_OPCODE_NOP = 0x00,
339 MLX4_OPCODE_SEND_INVAL = 0x01,
340 MLX4_OPCODE_RDMA_WRITE = 0x08,
341 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
342 MLX4_OPCODE_SEND = 0x0a,
343 MLX4_OPCODE_SEND_IMM = 0x0b,
344 MLX4_OPCODE_LSO = 0x0e,
345 MLX4_OPCODE_RDMA_READ = 0x10,
346 MLX4_OPCODE_ATOMIC_CS = 0x11,
347 MLX4_OPCODE_ATOMIC_FA = 0x12,
348 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
349 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
350 MLX4_OPCODE_BIND_MW = 0x18,
351 MLX4_OPCODE_FMR = 0x19,
352 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
353 MLX4_OPCODE_CONFIG_CMD = 0x1f,
354
355 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
356 MLX4_RECV_OPCODE_SEND = 0x01,
357 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
358 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
359
360 MLX4_CQE_OPCODE_ERROR = 0x1e,
361 MLX4_CQE_OPCODE_RESIZE = 0x16,
362 };
363
364 enum {
365 MLX4_STAT_RATE_OFFSET = 5
366 };
367
368 enum mlx4_protocol {
369 MLX4_PROT_IB_IPV6 = 0,
370 MLX4_PROT_ETH,
371 MLX4_PROT_IB_IPV4,
372 MLX4_PROT_FCOE
373 };
374
375 enum {
376 MLX4_MTT_FLAG_PRESENT = 1
377 };
378
379 enum mlx4_qp_region {
380 MLX4_QP_REGION_FW = 0,
381 MLX4_QP_REGION_RSS_RAW_ETH,
382 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
383 MLX4_QP_REGION_ETH_ADDR,
384 MLX4_QP_REGION_FC_ADDR,
385 MLX4_QP_REGION_FC_EXCH,
386 MLX4_NUM_QP_REGION
387 };
388
389 enum mlx4_port_type {
390 MLX4_PORT_TYPE_NONE = 0,
391 MLX4_PORT_TYPE_IB = 1,
392 MLX4_PORT_TYPE_ETH = 2,
393 MLX4_PORT_TYPE_AUTO = 3
394 };
395
396 enum mlx4_special_vlan_idx {
397 MLX4_NO_VLAN_IDX = 0,
398 MLX4_VLAN_MISS_IDX,
399 MLX4_VLAN_REGULAR
400 };
401
402 enum mlx4_steer_type {
403 MLX4_MC_STEER = 0,
404 MLX4_UC_STEER,
405 MLX4_NUM_STEERS
406 };
407
408 enum {
409 MLX4_NUM_FEXCH = 64 * 1024,
410 };
411
412 enum {
413 MLX4_MAX_FAST_REG_PAGES = 511,
414 };
415
416 enum {
417 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
418 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
419 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
420 };
421
422 /* Port mgmt change event handling */
423 enum {
424 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
425 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
426 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
427 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
428 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
429 };
430
431 enum {
432 MLX4_DEVICE_STATE_UP = 1 << 0,
433 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
434 };
435
436 enum {
437 MLX4_INTERFACE_STATE_UP = 1 << 0,
438 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
439 };
440
441 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
442 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
443
444 enum mlx4_module_id {
445 MLX4_MODULE_ID_SFP = 0x3,
446 MLX4_MODULE_ID_QSFP = 0xC,
447 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
448 MLX4_MODULE_ID_QSFP28 = 0x11,
449 };
450
451 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
452 {
453 return (major << 32) | (minor << 16) | subminor;
454 }
455
456 struct mlx4_phys_caps {
457 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
458 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
459 u32 num_phys_eqs;
460 u32 base_sqpn;
461 u32 base_proxy_sqpn;
462 u32 base_tunnel_sqpn;
463 };
464
465 struct mlx4_caps {
466 u64 fw_ver;
467 u32 function;
468 int num_ports;
469 int vl_cap[MLX4_MAX_PORTS + 1];
470 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
471 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
472 u64 def_mac[MLX4_MAX_PORTS + 1];
473 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
474 int gid_table_len[MLX4_MAX_PORTS + 1];
475 int pkey_table_len[MLX4_MAX_PORTS + 1];
476 int trans_type[MLX4_MAX_PORTS + 1];
477 int vendor_oui[MLX4_MAX_PORTS + 1];
478 int wavelength[MLX4_MAX_PORTS + 1];
479 u64 trans_code[MLX4_MAX_PORTS + 1];
480 int local_ca_ack_delay;
481 int num_uars;
482 u32 uar_page_size;
483 int bf_reg_size;
484 int bf_regs_per_page;
485 int max_sq_sg;
486 int max_rq_sg;
487 int num_qps;
488 int max_wqes;
489 int max_sq_desc_sz;
490 int max_rq_desc_sz;
491 int max_qp_init_rdma;
492 int max_qp_dest_rdma;
493 u32 *qp0_qkey;
494 u32 *qp0_proxy;
495 u32 *qp1_proxy;
496 u32 *qp0_tunnel;
497 u32 *qp1_tunnel;
498 int num_srqs;
499 int max_srq_wqes;
500 int max_srq_sge;
501 int reserved_srqs;
502 int num_cqs;
503 int max_cqes;
504 int reserved_cqs;
505 int num_sys_eqs;
506 int num_eqs;
507 int reserved_eqs;
508 int num_comp_vectors;
509 int comp_pool;
510 int num_mpts;
511 int max_fmr_maps;
512 int num_mtts;
513 int fmr_reserved_mtts;
514 int reserved_mtts;
515 int reserved_mrws;
516 int reserved_uars;
517 int num_mgms;
518 int num_amgms;
519 int reserved_mcgs;
520 int num_qp_per_mgm;
521 int steering_mode;
522 int dmfs_high_steer_mode;
523 int fs_log_max_ucast_qp_range_size;
524 int num_pds;
525 int reserved_pds;
526 int max_xrcds;
527 int reserved_xrcds;
528 int mtt_entry_sz;
529 u32 max_msg_sz;
530 u32 page_size_cap;
531 u64 flags;
532 u64 flags2;
533 u32 bmme_flags;
534 u32 reserved_lkey;
535 u16 stat_rate_support;
536 u8 port_width_cap[MLX4_MAX_PORTS + 1];
537 int max_gso_sz;
538 int max_rss_tbl_sz;
539 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
540 int reserved_qps;
541 int reserved_qps_base[MLX4_NUM_QP_REGION];
542 int log_num_macs;
543 int log_num_vlans;
544 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
545 u8 supported_type[MLX4_MAX_PORTS + 1];
546 u8 suggested_type[MLX4_MAX_PORTS + 1];
547 u8 default_sense[MLX4_MAX_PORTS + 1];
548 u32 port_mask[MLX4_MAX_PORTS + 1];
549 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
550 u32 max_counters;
551 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
552 u16 sqp_demux;
553 u32 eqe_size;
554 u32 cqe_size;
555 u8 eqe_factor;
556 u32 userspace_caps; /* userspace must be aware of these */
557 u32 function_caps; /* VFs must be aware of these */
558 u16 hca_core_clock;
559 u64 phys_port_id[MLX4_MAX_PORTS + 1];
560 int tunnel_offload_mode;
561 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
562 u8 alloc_res_qp_mask;
563 u32 dmfs_high_rate_qpn_base;
564 u32 dmfs_high_rate_qpn_range;
565 u32 vf_caps;
566 };
567
568 struct mlx4_buf_list {
569 void *buf;
570 dma_addr_t map;
571 };
572
573 struct mlx4_buf {
574 struct mlx4_buf_list direct;
575 struct mlx4_buf_list *page_list;
576 int nbufs;
577 int npages;
578 int page_shift;
579 };
580
581 struct mlx4_mtt {
582 u32 offset;
583 int order;
584 int page_shift;
585 };
586
587 enum {
588 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
589 };
590
591 struct mlx4_db_pgdir {
592 struct list_head list;
593 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
594 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
595 unsigned long *bits[2];
596 __be32 *db_page;
597 dma_addr_t db_dma;
598 };
599
600 struct mlx4_ib_user_db_page;
601
602 struct mlx4_db {
603 __be32 *db;
604 union {
605 struct mlx4_db_pgdir *pgdir;
606 struct mlx4_ib_user_db_page *user_page;
607 } u;
608 dma_addr_t dma;
609 int index;
610 int order;
611 };
612
613 struct mlx4_hwq_resources {
614 struct mlx4_db db;
615 struct mlx4_mtt mtt;
616 struct mlx4_buf buf;
617 };
618
619 struct mlx4_mr {
620 struct mlx4_mtt mtt;
621 u64 iova;
622 u64 size;
623 u32 key;
624 u32 pd;
625 u32 access;
626 int enabled;
627 };
628
629 enum mlx4_mw_type {
630 MLX4_MW_TYPE_1 = 1,
631 MLX4_MW_TYPE_2 = 2,
632 };
633
634 struct mlx4_mw {
635 u32 key;
636 u32 pd;
637 enum mlx4_mw_type type;
638 int enabled;
639 };
640
641 struct mlx4_fmr {
642 struct mlx4_mr mr;
643 struct mlx4_mpt_entry *mpt;
644 __be64 *mtts;
645 dma_addr_t dma_handle;
646 int max_pages;
647 int max_maps;
648 int maps;
649 u8 page_shift;
650 };
651
652 struct mlx4_uar {
653 unsigned long pfn;
654 int index;
655 struct list_head bf_list;
656 unsigned free_bf_bmap;
657 void __iomem *map;
658 void __iomem *bf_map;
659 };
660
661 struct mlx4_bf {
662 unsigned int offset;
663 int buf_size;
664 struct mlx4_uar *uar;
665 void __iomem *reg;
666 };
667
668 struct mlx4_cq {
669 void (*comp) (struct mlx4_cq *);
670 void (*event) (struct mlx4_cq *, enum mlx4_event);
671
672 struct mlx4_uar *uar;
673
674 u32 cons_index;
675
676 u16 irq;
677 __be32 *set_ci_db;
678 __be32 *arm_db;
679 int arm_sn;
680
681 int cqn;
682 unsigned vector;
683
684 atomic_t refcount;
685 struct completion free;
686 struct {
687 struct list_head list;
688 void (*comp)(struct mlx4_cq *);
689 void *priv;
690 } tasklet_ctx;
691 };
692
693 struct mlx4_qp {
694 void (*event) (struct mlx4_qp *, enum mlx4_event);
695
696 int qpn;
697
698 atomic_t refcount;
699 struct completion free;
700 };
701
702 struct mlx4_srq {
703 void (*event) (struct mlx4_srq *, enum mlx4_event);
704
705 int srqn;
706 int max;
707 int max_gs;
708 int wqe_shift;
709
710 atomic_t refcount;
711 struct completion free;
712 };
713
714 struct mlx4_av {
715 __be32 port_pd;
716 u8 reserved1;
717 u8 g_slid;
718 __be16 dlid;
719 u8 reserved2;
720 u8 gid_index;
721 u8 stat_rate;
722 u8 hop_limit;
723 __be32 sl_tclass_flowlabel;
724 u8 dgid[16];
725 };
726
727 struct mlx4_eth_av {
728 __be32 port_pd;
729 u8 reserved1;
730 u8 smac_idx;
731 u16 reserved2;
732 u8 reserved3;
733 u8 gid_index;
734 u8 stat_rate;
735 u8 hop_limit;
736 __be32 sl_tclass_flowlabel;
737 u8 dgid[16];
738 u8 s_mac[6];
739 u8 reserved4[2];
740 __be16 vlan;
741 u8 mac[ETH_ALEN];
742 };
743
744 union mlx4_ext_av {
745 struct mlx4_av ib;
746 struct mlx4_eth_av eth;
747 };
748
749 struct mlx4_counter {
750 u8 reserved1[3];
751 u8 counter_mode;
752 __be32 num_ifc;
753 u32 reserved2[2];
754 __be64 rx_frames;
755 __be64 rx_bytes;
756 __be64 tx_frames;
757 __be64 tx_bytes;
758 };
759
760 struct mlx4_quotas {
761 int qp;
762 int cq;
763 int srq;
764 int mpt;
765 int mtt;
766 int counter;
767 int xrcd;
768 };
769
770 struct mlx4_vf_dev {
771 u8 min_port;
772 u8 n_ports;
773 };
774
775 struct mlx4_dev_persistent {
776 struct pci_dev *pdev;
777 struct mlx4_dev *dev;
778 int nvfs[MLX4_MAX_PORTS + 1];
779 int num_vfs;
780 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
781 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
782 struct work_struct catas_work;
783 struct workqueue_struct *catas_wq;
784 struct mutex device_state_mutex; /* protect HW state */
785 u8 state;
786 struct mutex interface_state_mutex; /* protect SW state */
787 u8 interface_state;
788 };
789
790 struct mlx4_dev {
791 struct mlx4_dev_persistent *persist;
792 unsigned long flags;
793 unsigned long num_slaves;
794 struct mlx4_caps caps;
795 struct mlx4_phys_caps phys_caps;
796 struct mlx4_quotas quotas;
797 struct radix_tree_root qp_table_tree;
798 u8 rev_id;
799 char board_id[MLX4_BOARD_ID_LEN];
800 int numa_node;
801 int oper_log_mgm_entry_size;
802 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
803 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
804 struct mlx4_vf_dev *dev_vfs;
805 };
806
807 struct mlx4_eqe {
808 u8 reserved1;
809 u8 type;
810 u8 reserved2;
811 u8 subtype;
812 union {
813 u32 raw[6];
814 struct {
815 __be32 cqn;
816 } __packed comp;
817 struct {
818 u16 reserved1;
819 __be16 token;
820 u32 reserved2;
821 u8 reserved3[3];
822 u8 status;
823 __be64 out_param;
824 } __packed cmd;
825 struct {
826 __be32 qpn;
827 } __packed qp;
828 struct {
829 __be32 srqn;
830 } __packed srq;
831 struct {
832 __be32 cqn;
833 u32 reserved1;
834 u8 reserved2[3];
835 u8 syndrome;
836 } __packed cq_err;
837 struct {
838 u32 reserved1[2];
839 __be32 port;
840 } __packed port_change;
841 struct {
842 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
843 u32 reserved;
844 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
845 } __packed comm_channel_arm;
846 struct {
847 u8 port;
848 u8 reserved[3];
849 __be64 mac;
850 } __packed mac_update;
851 struct {
852 __be32 slave_id;
853 } __packed flr_event;
854 struct {
855 __be16 current_temperature;
856 __be16 warning_threshold;
857 } __packed warming;
858 struct {
859 u8 reserved[3];
860 u8 port;
861 union {
862 struct {
863 __be16 mstr_sm_lid;
864 __be16 port_lid;
865 __be32 changed_attr;
866 u8 reserved[3];
867 u8 mstr_sm_sl;
868 __be64 gid_prefix;
869 } __packed port_info;
870 struct {
871 __be32 block_ptr;
872 __be32 tbl_entries_mask;
873 } __packed tbl_change_info;
874 } params;
875 } __packed port_mgmt_change;
876 struct {
877 u8 reserved[3];
878 u8 port;
879 u32 reserved1[5];
880 } __packed bad_cable;
881 } event;
882 u8 slave_id;
883 u8 reserved3[2];
884 u8 owner;
885 } __packed;
886
887 struct mlx4_init_port_param {
888 int set_guid0;
889 int set_node_guid;
890 int set_si_guid;
891 u16 mtu;
892 int port_width_cap;
893 u16 vl_cap;
894 u16 max_gid;
895 u16 max_pkey;
896 u64 guid0;
897 u64 node_guid;
898 u64 si_guid;
899 };
900
901 #define MAD_IFC_DATA_SZ 192
902 /* MAD IFC Mailbox */
903 struct mlx4_mad_ifc {
904 u8 base_version;
905 u8 mgmt_class;
906 u8 class_version;
907 u8 method;
908 __be16 status;
909 __be16 class_specific;
910 __be64 tid;
911 __be16 attr_id;
912 __be16 resv;
913 __be32 attr_mod;
914 __be64 mkey;
915 __be16 dr_slid;
916 __be16 dr_dlid;
917 u8 reserved[28];
918 u8 data[MAD_IFC_DATA_SZ];
919 } __packed;
920
921 #define mlx4_foreach_port(port, dev, type) \
922 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
923 if ((type) == (dev)->caps.port_mask[(port)])
924
925 #define mlx4_foreach_non_ib_transport_port(port, dev) \
926 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
927 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
928
929 #define mlx4_foreach_ib_transport_port(port, dev) \
930 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
931 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
932 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
933
934 #define MLX4_INVALID_SLAVE_ID 0xFF
935
936 void handle_port_mgmt_change_event(struct work_struct *work);
937
938 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
939 {
940 return dev->caps.function;
941 }
942
943 static inline int mlx4_is_master(struct mlx4_dev *dev)
944 {
945 return dev->flags & MLX4_FLAG_MASTER;
946 }
947
948 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
949 {
950 return dev->phys_caps.base_sqpn + 8 +
951 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
952 }
953
954 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
955 {
956 return (qpn < dev->phys_caps.base_sqpn + 8 +
957 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
958 qpn >= dev->phys_caps.base_sqpn) ||
959 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
960 }
961
962 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
963 {
964 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
965
966 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
967 return 1;
968
969 return 0;
970 }
971
972 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
973 {
974 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
975 }
976
977 static inline int mlx4_is_slave(struct mlx4_dev *dev)
978 {
979 return dev->flags & MLX4_FLAG_SLAVE;
980 }
981
982 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
983 struct mlx4_buf *buf, gfp_t gfp);
984 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
985 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
986 {
987 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
988 return buf->direct.buf + offset;
989 else
990 return buf->page_list[offset >> PAGE_SHIFT].buf +
991 (offset & (PAGE_SIZE - 1));
992 }
993
994 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
995 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
996 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
997 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
998
999 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1000 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1001 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1002 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1003
1004 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1005 struct mlx4_mtt *mtt);
1006 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1007 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1008
1009 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1010 int npages, int page_shift, struct mlx4_mr *mr);
1011 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1012 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1013 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1014 struct mlx4_mw *mw);
1015 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1016 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1017 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1018 int start_index, int npages, u64 *page_list);
1019 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1020 struct mlx4_buf *buf, gfp_t gfp);
1021
1022 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1023 gfp_t gfp);
1024 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1025
1026 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1027 int size, int max_direct);
1028 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1029 int size);
1030
1031 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1032 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1033 unsigned vector, int collapsed, int timestamp_en);
1034 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1035 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1036 int *base, u8 flags);
1037 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1038
1039 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1040 gfp_t gfp);
1041 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1042
1043 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1044 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1045 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1046 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1047 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1048
1049 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1050 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1051
1052 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1053 int block_mcast_loopback, enum mlx4_protocol prot);
1054 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1055 enum mlx4_protocol prot);
1056 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1057 u8 port, int block_mcast_loopback,
1058 enum mlx4_protocol protocol, u64 *reg_id);
1059 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1060 enum mlx4_protocol protocol, u64 reg_id);
1061
1062 enum {
1063 MLX4_DOMAIN_UVERBS = 0x1000,
1064 MLX4_DOMAIN_ETHTOOL = 0x2000,
1065 MLX4_DOMAIN_RFS = 0x3000,
1066 MLX4_DOMAIN_NIC = 0x5000,
1067 };
1068
1069 enum mlx4_net_trans_rule_id {
1070 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1071 MLX4_NET_TRANS_RULE_ID_IB,
1072 MLX4_NET_TRANS_RULE_ID_IPV6,
1073 MLX4_NET_TRANS_RULE_ID_IPV4,
1074 MLX4_NET_TRANS_RULE_ID_TCP,
1075 MLX4_NET_TRANS_RULE_ID_UDP,
1076 MLX4_NET_TRANS_RULE_ID_VXLAN,
1077 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1078 };
1079
1080 extern const u16 __sw_id_hw[];
1081
1082 static inline int map_hw_to_sw_id(u16 header_id)
1083 {
1084
1085 int i;
1086 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1087 if (header_id == __sw_id_hw[i])
1088 return i;
1089 }
1090 return -EINVAL;
1091 }
1092
1093 enum mlx4_net_trans_promisc_mode {
1094 MLX4_FS_REGULAR = 1,
1095 MLX4_FS_ALL_DEFAULT,
1096 MLX4_FS_MC_DEFAULT,
1097 MLX4_FS_UC_SNIFFER,
1098 MLX4_FS_MC_SNIFFER,
1099 MLX4_FS_MODE_NUM, /* should be last */
1100 };
1101
1102 struct mlx4_spec_eth {
1103 u8 dst_mac[ETH_ALEN];
1104 u8 dst_mac_msk[ETH_ALEN];
1105 u8 src_mac[ETH_ALEN];
1106 u8 src_mac_msk[ETH_ALEN];
1107 u8 ether_type_enable;
1108 __be16 ether_type;
1109 __be16 vlan_id_msk;
1110 __be16 vlan_id;
1111 };
1112
1113 struct mlx4_spec_tcp_udp {
1114 __be16 dst_port;
1115 __be16 dst_port_msk;
1116 __be16 src_port;
1117 __be16 src_port_msk;
1118 };
1119
1120 struct mlx4_spec_ipv4 {
1121 __be32 dst_ip;
1122 __be32 dst_ip_msk;
1123 __be32 src_ip;
1124 __be32 src_ip_msk;
1125 };
1126
1127 struct mlx4_spec_ib {
1128 __be32 l3_qpn;
1129 __be32 qpn_msk;
1130 u8 dst_gid[16];
1131 u8 dst_gid_msk[16];
1132 };
1133
1134 struct mlx4_spec_vxlan {
1135 __be32 vni;
1136 __be32 vni_mask;
1137
1138 };
1139
1140 struct mlx4_spec_list {
1141 struct list_head list;
1142 enum mlx4_net_trans_rule_id id;
1143 union {
1144 struct mlx4_spec_eth eth;
1145 struct mlx4_spec_ib ib;
1146 struct mlx4_spec_ipv4 ipv4;
1147 struct mlx4_spec_tcp_udp tcp_udp;
1148 struct mlx4_spec_vxlan vxlan;
1149 };
1150 };
1151
1152 enum mlx4_net_trans_hw_rule_queue {
1153 MLX4_NET_TRANS_Q_FIFO,
1154 MLX4_NET_TRANS_Q_LIFO,
1155 };
1156
1157 struct mlx4_net_trans_rule {
1158 struct list_head list;
1159 enum mlx4_net_trans_hw_rule_queue queue_mode;
1160 bool exclusive;
1161 bool allow_loopback;
1162 enum mlx4_net_trans_promisc_mode promisc_mode;
1163 u8 port;
1164 u16 priority;
1165 u32 qpn;
1166 };
1167
1168 struct mlx4_net_trans_rule_hw_ctrl {
1169 __be16 prio;
1170 u8 type;
1171 u8 flags;
1172 u8 rsvd1;
1173 u8 funcid;
1174 u8 vep;
1175 u8 port;
1176 __be32 qpn;
1177 __be32 rsvd2;
1178 };
1179
1180 struct mlx4_net_trans_rule_hw_ib {
1181 u8 size;
1182 u8 rsvd1;
1183 __be16 id;
1184 u32 rsvd2;
1185 __be32 l3_qpn;
1186 __be32 qpn_mask;
1187 u8 dst_gid[16];
1188 u8 dst_gid_msk[16];
1189 } __packed;
1190
1191 struct mlx4_net_trans_rule_hw_eth {
1192 u8 size;
1193 u8 rsvd;
1194 __be16 id;
1195 u8 rsvd1[6];
1196 u8 dst_mac[6];
1197 u16 rsvd2;
1198 u8 dst_mac_msk[6];
1199 u16 rsvd3;
1200 u8 src_mac[6];
1201 u16 rsvd4;
1202 u8 src_mac_msk[6];
1203 u8 rsvd5;
1204 u8 ether_type_enable;
1205 __be16 ether_type;
1206 __be16 vlan_tag_msk;
1207 __be16 vlan_tag;
1208 } __packed;
1209
1210 struct mlx4_net_trans_rule_hw_tcp_udp {
1211 u8 size;
1212 u8 rsvd;
1213 __be16 id;
1214 __be16 rsvd1[3];
1215 __be16 dst_port;
1216 __be16 rsvd2;
1217 __be16 dst_port_msk;
1218 __be16 rsvd3;
1219 __be16 src_port;
1220 __be16 rsvd4;
1221 __be16 src_port_msk;
1222 } __packed;
1223
1224 struct mlx4_net_trans_rule_hw_ipv4 {
1225 u8 size;
1226 u8 rsvd;
1227 __be16 id;
1228 __be32 rsvd1;
1229 __be32 dst_ip;
1230 __be32 dst_ip_msk;
1231 __be32 src_ip;
1232 __be32 src_ip_msk;
1233 } __packed;
1234
1235 struct mlx4_net_trans_rule_hw_vxlan {
1236 u8 size;
1237 u8 rsvd;
1238 __be16 id;
1239 __be32 rsvd1;
1240 __be32 vni;
1241 __be32 vni_mask;
1242 } __packed;
1243
1244 struct _rule_hw {
1245 union {
1246 struct {
1247 u8 size;
1248 u8 rsvd;
1249 __be16 id;
1250 };
1251 struct mlx4_net_trans_rule_hw_eth eth;
1252 struct mlx4_net_trans_rule_hw_ib ib;
1253 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1254 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1255 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1256 };
1257 };
1258
1259 enum {
1260 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1261 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1262 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1263 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1264 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1265 };
1266
1267
1268 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1269 enum mlx4_net_trans_promisc_mode mode);
1270 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1271 enum mlx4_net_trans_promisc_mode mode);
1272 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1273 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1274 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1275 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1276 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1277
1278 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1279 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1280 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1281 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1282 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1283 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1284 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1285 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1286 u8 promisc);
1287 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1288 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1289 u8 *pg, u16 *ratelimit);
1290 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1291 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1292 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1293 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1294 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1295
1296 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1297 int npages, u64 iova, u32 *lkey, u32 *rkey);
1298 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1299 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1300 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1301 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1302 u32 *lkey, u32 *rkey);
1303 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1304 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1305 int mlx4_test_interrupts(struct mlx4_dev *dev);
1306 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1307 int *vector);
1308 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1309
1310 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1311
1312 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1313 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1314 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1315
1316 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1317 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1318
1319 int mlx4_flow_attach(struct mlx4_dev *dev,
1320 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1321 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1322 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1323 enum mlx4_net_trans_promisc_mode flow_type);
1324 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1325 enum mlx4_net_trans_rule_id id);
1326 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1327
1328 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1329 int port, int qpn, u16 prio, u64 *reg_id);
1330
1331 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1332 int i, int val);
1333
1334 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1335
1336 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1337 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1338 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1339 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1340 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1341 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1342 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1343
1344 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1345 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1346
1347 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1348 int *slave_id);
1349 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1350 u8 *gid);
1351
1352 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1353 u32 max_range_qpn);
1354
1355 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1356
1357 struct mlx4_active_ports {
1358 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1359 };
1360 /* Returns a bitmap of the physical ports which are assigned to slave */
1361 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1362
1363 /* Returns the physical port that represents the virtual port of the slave, */
1364 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1365 /* mapping is returned. */
1366 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1367
1368 struct mlx4_slaves_pport {
1369 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1370 };
1371 /* Returns a bitmap of all slaves that are assigned to port. */
1372 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1373 int port);
1374
1375 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1376 /* the ports that are set in crit_ports. */
1377 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1378 struct mlx4_dev *dev,
1379 const struct mlx4_active_ports *crit_ports);
1380
1381 /* Returns the slave's virtual port that represents the physical port. */
1382 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1383
1384 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1385
1386 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1387 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1388 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1389 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1390 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1391 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1392 int enable);
1393 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1394 struct mlx4_mpt_entry ***mpt_entry);
1395 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1396 struct mlx4_mpt_entry **mpt_entry);
1397 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1398 u32 pdn);
1399 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1400 struct mlx4_mpt_entry *mpt_entry,
1401 u32 access);
1402 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1403 struct mlx4_mpt_entry **mpt_entry);
1404 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1405 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1406 u64 iova, u64 size, int npages,
1407 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1408
1409 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1410 u16 offset, u16 size, u8 *data);
1411
1412 /* Returns true if running in low memory profile (kdump kernel) */
1413 static inline bool mlx4_low_memory_profile(void)
1414 {
1415 return is_kdump_kernel();
1416 }
1417
1418 /* ACCESS REG commands */
1419 enum mlx4_access_reg_method {
1420 MLX4_ACCESS_REG_QUERY = 0x1,
1421 MLX4_ACCESS_REG_WRITE = 0x2,
1422 };
1423
1424 /* ACCESS PTYS Reg command */
1425 enum mlx4_ptys_proto {
1426 MLX4_PTYS_IB = 1<<0,
1427 MLX4_PTYS_EN = 1<<2,
1428 };
1429
1430 struct mlx4_ptys_reg {
1431 u8 resrvd1;
1432 u8 local_port;
1433 u8 resrvd2;
1434 u8 proto_mask;
1435 __be32 resrvd3[2];
1436 __be32 eth_proto_cap;
1437 __be16 ib_width_cap;
1438 __be16 ib_speed_cap;
1439 __be32 resrvd4;
1440 __be32 eth_proto_admin;
1441 __be16 ib_width_admin;
1442 __be16 ib_speed_admin;
1443 __be32 resrvd5;
1444 __be32 eth_proto_oper;
1445 __be16 ib_width_oper;
1446 __be16 ib_speed_oper;
1447 __be32 resrvd6;
1448 __be32 eth_proto_lp_adv;
1449 } __packed;
1450
1451 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1452 enum mlx4_access_reg_method method,
1453 struct mlx4_ptys_reg *ptys_reg);
1454
1455 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
This page took 0.068077 seconds and 4 git commands to generate.