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mlx4_core: Propagate MR deregistration failures to caller
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
40
41 #include <linux/atomic.h>
42
43 #define MAX_MSIX_P_PORT 17
44 #define MAX_MSIX 64
45 #define MSIX_LEGACY_SZ 4
46 #define MIN_MSIX_P_PORT 5
47
48 enum {
49 MLX4_FLAG_MSI_X = 1 << 0,
50 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
51 MLX4_FLAG_MASTER = 1 << 2,
52 MLX4_FLAG_SLAVE = 1 << 3,
53 MLX4_FLAG_SRIOV = 1 << 4,
54 };
55
56 enum {
57 MLX4_PORT_CAP_IS_SM = 1 << 1,
58 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
59 };
60
61 enum {
62 MLX4_MAX_PORTS = 2,
63 MLX4_MAX_PORT_PKEYS = 128
64 };
65
66 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
67 * These qkeys must not be allowed for general use. This is a 64k range,
68 * and to test for violation, we use the mask (protect against future chg).
69 */
70 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
71 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
72
73 enum {
74 MLX4_BOARD_ID_LEN = 64
75 };
76
77 enum {
78 MLX4_MAX_NUM_PF = 16,
79 MLX4_MAX_NUM_VF = 64,
80 MLX4_MFUNC_MAX = 80,
81 MLX4_MAX_EQ_NUM = 1024,
82 MLX4_MFUNC_EQ_NUM = 4,
83 MLX4_MFUNC_MAX_EQES = 8,
84 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
85 };
86
87 /* Driver supports 3 diffrent device methods to manage traffic steering:
88 * -device managed - High level API for ib and eth flow steering. FW is
89 * managing flow steering tables.
90 * - B0 steering mode - Common low level API for ib and (if supported) eth.
91 * - A0 steering mode - Limited low level API for eth. In case of IB,
92 * B0 mode is in use.
93 */
94 enum {
95 MLX4_STEERING_MODE_A0,
96 MLX4_STEERING_MODE_B0,
97 MLX4_STEERING_MODE_DEVICE_MANAGED
98 };
99
100 static inline const char *mlx4_steering_mode_str(int steering_mode)
101 {
102 switch (steering_mode) {
103 case MLX4_STEERING_MODE_A0:
104 return "A0 steering";
105
106 case MLX4_STEERING_MODE_B0:
107 return "B0 steering";
108
109 case MLX4_STEERING_MODE_DEVICE_MANAGED:
110 return "Device managed flow steering";
111
112 default:
113 return "Unrecognize steering mode";
114 }
115 }
116
117 enum {
118 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
119 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
120 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
121 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
122 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
123 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
124 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
125 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
126 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
127 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
128 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
129 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
130 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
131 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
132 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
133 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
134 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
135 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
136 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
137 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
138 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
139 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
140 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
141 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
142 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
143 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
144 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
145 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
146 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
147 };
148
149 enum {
150 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
151 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
152 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
153 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3
154 };
155
156 enum {
157 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
158 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
159 };
160
161 enum {
162 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
163 };
164
165 enum {
166 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
167 };
168
169
170 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
171
172 enum {
173 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
174 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
175 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
176 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
177 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
178 };
179
180 enum mlx4_event {
181 MLX4_EVENT_TYPE_COMP = 0x00,
182 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
183 MLX4_EVENT_TYPE_COMM_EST = 0x02,
184 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
185 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
186 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
187 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
188 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
189 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
190 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
191 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
192 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
193 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
194 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
195 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
196 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
197 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
198 MLX4_EVENT_TYPE_CMD = 0x0a,
199 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
200 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
201 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
202 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
203 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
204 MLX4_EVENT_TYPE_NONE = 0xff,
205 };
206
207 enum {
208 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
209 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
210 };
211
212 enum {
213 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
214 };
215
216 enum slave_port_state {
217 SLAVE_PORT_DOWN = 0,
218 SLAVE_PENDING_UP,
219 SLAVE_PORT_UP,
220 };
221
222 enum slave_port_gen_event {
223 SLAVE_PORT_GEN_EVENT_DOWN = 0,
224 SLAVE_PORT_GEN_EVENT_UP,
225 SLAVE_PORT_GEN_EVENT_NONE,
226 };
227
228 enum slave_port_state_event {
229 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
230 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
231 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
232 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
233 };
234
235 enum {
236 MLX4_PERM_LOCAL_READ = 1 << 10,
237 MLX4_PERM_LOCAL_WRITE = 1 << 11,
238 MLX4_PERM_REMOTE_READ = 1 << 12,
239 MLX4_PERM_REMOTE_WRITE = 1 << 13,
240 MLX4_PERM_ATOMIC = 1 << 14
241 };
242
243 enum {
244 MLX4_OPCODE_NOP = 0x00,
245 MLX4_OPCODE_SEND_INVAL = 0x01,
246 MLX4_OPCODE_RDMA_WRITE = 0x08,
247 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
248 MLX4_OPCODE_SEND = 0x0a,
249 MLX4_OPCODE_SEND_IMM = 0x0b,
250 MLX4_OPCODE_LSO = 0x0e,
251 MLX4_OPCODE_RDMA_READ = 0x10,
252 MLX4_OPCODE_ATOMIC_CS = 0x11,
253 MLX4_OPCODE_ATOMIC_FA = 0x12,
254 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
255 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
256 MLX4_OPCODE_BIND_MW = 0x18,
257 MLX4_OPCODE_FMR = 0x19,
258 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
259 MLX4_OPCODE_CONFIG_CMD = 0x1f,
260
261 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
262 MLX4_RECV_OPCODE_SEND = 0x01,
263 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
264 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
265
266 MLX4_CQE_OPCODE_ERROR = 0x1e,
267 MLX4_CQE_OPCODE_RESIZE = 0x16,
268 };
269
270 enum {
271 MLX4_STAT_RATE_OFFSET = 5
272 };
273
274 enum mlx4_protocol {
275 MLX4_PROT_IB_IPV6 = 0,
276 MLX4_PROT_ETH,
277 MLX4_PROT_IB_IPV4,
278 MLX4_PROT_FCOE
279 };
280
281 enum {
282 MLX4_MTT_FLAG_PRESENT = 1
283 };
284
285 enum mlx4_qp_region {
286 MLX4_QP_REGION_FW = 0,
287 MLX4_QP_REGION_ETH_ADDR,
288 MLX4_QP_REGION_FC_ADDR,
289 MLX4_QP_REGION_FC_EXCH,
290 MLX4_NUM_QP_REGION
291 };
292
293 enum mlx4_port_type {
294 MLX4_PORT_TYPE_NONE = 0,
295 MLX4_PORT_TYPE_IB = 1,
296 MLX4_PORT_TYPE_ETH = 2,
297 MLX4_PORT_TYPE_AUTO = 3
298 };
299
300 enum mlx4_special_vlan_idx {
301 MLX4_NO_VLAN_IDX = 0,
302 MLX4_VLAN_MISS_IDX,
303 MLX4_VLAN_REGULAR
304 };
305
306 enum mlx4_steer_type {
307 MLX4_MC_STEER = 0,
308 MLX4_UC_STEER,
309 MLX4_NUM_STEERS
310 };
311
312 enum {
313 MLX4_NUM_FEXCH = 64 * 1024,
314 };
315
316 enum {
317 MLX4_MAX_FAST_REG_PAGES = 511,
318 };
319
320 enum {
321 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
322 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
323 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
324 };
325
326 /* Port mgmt change event handling */
327 enum {
328 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
329 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
330 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
331 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
332 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
333 };
334
335 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
336 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
337
338 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
339 {
340 return (major << 32) | (minor << 16) | subminor;
341 }
342
343 struct mlx4_phys_caps {
344 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
345 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
346 u32 num_phys_eqs;
347 u32 base_sqpn;
348 u32 base_proxy_sqpn;
349 u32 base_tunnel_sqpn;
350 };
351
352 struct mlx4_caps {
353 u64 fw_ver;
354 u32 function;
355 int num_ports;
356 int vl_cap[MLX4_MAX_PORTS + 1];
357 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
358 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
359 u64 def_mac[MLX4_MAX_PORTS + 1];
360 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
361 int gid_table_len[MLX4_MAX_PORTS + 1];
362 int pkey_table_len[MLX4_MAX_PORTS + 1];
363 int trans_type[MLX4_MAX_PORTS + 1];
364 int vendor_oui[MLX4_MAX_PORTS + 1];
365 int wavelength[MLX4_MAX_PORTS + 1];
366 u64 trans_code[MLX4_MAX_PORTS + 1];
367 int local_ca_ack_delay;
368 int num_uars;
369 u32 uar_page_size;
370 int bf_reg_size;
371 int bf_regs_per_page;
372 int max_sq_sg;
373 int max_rq_sg;
374 int num_qps;
375 int max_wqes;
376 int max_sq_desc_sz;
377 int max_rq_desc_sz;
378 int max_qp_init_rdma;
379 int max_qp_dest_rdma;
380 u32 *qp0_proxy;
381 u32 *qp1_proxy;
382 u32 *qp0_tunnel;
383 u32 *qp1_tunnel;
384 int num_srqs;
385 int max_srq_wqes;
386 int max_srq_sge;
387 int reserved_srqs;
388 int num_cqs;
389 int max_cqes;
390 int reserved_cqs;
391 int num_eqs;
392 int reserved_eqs;
393 int num_comp_vectors;
394 int comp_pool;
395 int num_mpts;
396 int max_fmr_maps;
397 int num_mtts;
398 int fmr_reserved_mtts;
399 int reserved_mtts;
400 int reserved_mrws;
401 int reserved_uars;
402 int num_mgms;
403 int num_amgms;
404 int reserved_mcgs;
405 int num_qp_per_mgm;
406 int steering_mode;
407 int fs_log_max_ucast_qp_range_size;
408 int num_pds;
409 int reserved_pds;
410 int max_xrcds;
411 int reserved_xrcds;
412 int mtt_entry_sz;
413 u32 max_msg_sz;
414 u32 page_size_cap;
415 u64 flags;
416 u64 flags2;
417 u32 bmme_flags;
418 u32 reserved_lkey;
419 u16 stat_rate_support;
420 u8 port_width_cap[MLX4_MAX_PORTS + 1];
421 int max_gso_sz;
422 int max_rss_tbl_sz;
423 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
424 int reserved_qps;
425 int reserved_qps_base[MLX4_NUM_QP_REGION];
426 int log_num_macs;
427 int log_num_vlans;
428 int log_num_prios;
429 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
430 u8 supported_type[MLX4_MAX_PORTS + 1];
431 u8 suggested_type[MLX4_MAX_PORTS + 1];
432 u8 default_sense[MLX4_MAX_PORTS + 1];
433 u32 port_mask[MLX4_MAX_PORTS + 1];
434 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
435 u32 max_counters;
436 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
437 u16 sqp_demux;
438 u32 eqe_size;
439 u32 cqe_size;
440 u8 eqe_factor;
441 u32 userspace_caps; /* userspace must be aware of these */
442 u32 function_caps; /* VFs must be aware of these */
443 };
444
445 struct mlx4_buf_list {
446 void *buf;
447 dma_addr_t map;
448 };
449
450 struct mlx4_buf {
451 struct mlx4_buf_list direct;
452 struct mlx4_buf_list *page_list;
453 int nbufs;
454 int npages;
455 int page_shift;
456 };
457
458 struct mlx4_mtt {
459 u32 offset;
460 int order;
461 int page_shift;
462 };
463
464 enum {
465 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
466 };
467
468 struct mlx4_db_pgdir {
469 struct list_head list;
470 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
471 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
472 unsigned long *bits[2];
473 __be32 *db_page;
474 dma_addr_t db_dma;
475 };
476
477 struct mlx4_ib_user_db_page;
478
479 struct mlx4_db {
480 __be32 *db;
481 union {
482 struct mlx4_db_pgdir *pgdir;
483 struct mlx4_ib_user_db_page *user_page;
484 } u;
485 dma_addr_t dma;
486 int index;
487 int order;
488 };
489
490 struct mlx4_hwq_resources {
491 struct mlx4_db db;
492 struct mlx4_mtt mtt;
493 struct mlx4_buf buf;
494 };
495
496 struct mlx4_mr {
497 struct mlx4_mtt mtt;
498 u64 iova;
499 u64 size;
500 u32 key;
501 u32 pd;
502 u32 access;
503 int enabled;
504 };
505
506 struct mlx4_fmr {
507 struct mlx4_mr mr;
508 struct mlx4_mpt_entry *mpt;
509 __be64 *mtts;
510 dma_addr_t dma_handle;
511 int max_pages;
512 int max_maps;
513 int maps;
514 u8 page_shift;
515 };
516
517 struct mlx4_uar {
518 unsigned long pfn;
519 int index;
520 struct list_head bf_list;
521 unsigned free_bf_bmap;
522 void __iomem *map;
523 void __iomem *bf_map;
524 };
525
526 struct mlx4_bf {
527 unsigned long offset;
528 int buf_size;
529 struct mlx4_uar *uar;
530 void __iomem *reg;
531 };
532
533 struct mlx4_cq {
534 void (*comp) (struct mlx4_cq *);
535 void (*event) (struct mlx4_cq *, enum mlx4_event);
536
537 struct mlx4_uar *uar;
538
539 u32 cons_index;
540
541 __be32 *set_ci_db;
542 __be32 *arm_db;
543 int arm_sn;
544
545 int cqn;
546 unsigned vector;
547
548 atomic_t refcount;
549 struct completion free;
550 };
551
552 struct mlx4_qp {
553 void (*event) (struct mlx4_qp *, enum mlx4_event);
554
555 int qpn;
556
557 atomic_t refcount;
558 struct completion free;
559 };
560
561 struct mlx4_srq {
562 void (*event) (struct mlx4_srq *, enum mlx4_event);
563
564 int srqn;
565 int max;
566 int max_gs;
567 int wqe_shift;
568
569 atomic_t refcount;
570 struct completion free;
571 };
572
573 struct mlx4_av {
574 __be32 port_pd;
575 u8 reserved1;
576 u8 g_slid;
577 __be16 dlid;
578 u8 reserved2;
579 u8 gid_index;
580 u8 stat_rate;
581 u8 hop_limit;
582 __be32 sl_tclass_flowlabel;
583 u8 dgid[16];
584 };
585
586 struct mlx4_eth_av {
587 __be32 port_pd;
588 u8 reserved1;
589 u8 smac_idx;
590 u16 reserved2;
591 u8 reserved3;
592 u8 gid_index;
593 u8 stat_rate;
594 u8 hop_limit;
595 __be32 sl_tclass_flowlabel;
596 u8 dgid[16];
597 u32 reserved4[2];
598 __be16 vlan;
599 u8 mac[6];
600 };
601
602 union mlx4_ext_av {
603 struct mlx4_av ib;
604 struct mlx4_eth_av eth;
605 };
606
607 struct mlx4_counter {
608 u8 reserved1[3];
609 u8 counter_mode;
610 __be32 num_ifc;
611 u32 reserved2[2];
612 __be64 rx_frames;
613 __be64 rx_bytes;
614 __be64 tx_frames;
615 __be64 tx_bytes;
616 };
617
618 struct mlx4_dev {
619 struct pci_dev *pdev;
620 unsigned long flags;
621 unsigned long num_slaves;
622 struct mlx4_caps caps;
623 struct mlx4_phys_caps phys_caps;
624 struct radix_tree_root qp_table_tree;
625 u8 rev_id;
626 char board_id[MLX4_BOARD_ID_LEN];
627 int num_vfs;
628 int oper_log_mgm_entry_size;
629 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
630 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
631 };
632
633 struct mlx4_eqe {
634 u8 reserved1;
635 u8 type;
636 u8 reserved2;
637 u8 subtype;
638 union {
639 u32 raw[6];
640 struct {
641 __be32 cqn;
642 } __packed comp;
643 struct {
644 u16 reserved1;
645 __be16 token;
646 u32 reserved2;
647 u8 reserved3[3];
648 u8 status;
649 __be64 out_param;
650 } __packed cmd;
651 struct {
652 __be32 qpn;
653 } __packed qp;
654 struct {
655 __be32 srqn;
656 } __packed srq;
657 struct {
658 __be32 cqn;
659 u32 reserved1;
660 u8 reserved2[3];
661 u8 syndrome;
662 } __packed cq_err;
663 struct {
664 u32 reserved1[2];
665 __be32 port;
666 } __packed port_change;
667 struct {
668 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
669 u32 reserved;
670 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
671 } __packed comm_channel_arm;
672 struct {
673 u8 port;
674 u8 reserved[3];
675 __be64 mac;
676 } __packed mac_update;
677 struct {
678 __be32 slave_id;
679 } __packed flr_event;
680 struct {
681 __be16 current_temperature;
682 __be16 warning_threshold;
683 } __packed warming;
684 struct {
685 u8 reserved[3];
686 u8 port;
687 union {
688 struct {
689 __be16 mstr_sm_lid;
690 __be16 port_lid;
691 __be32 changed_attr;
692 u8 reserved[3];
693 u8 mstr_sm_sl;
694 __be64 gid_prefix;
695 } __packed port_info;
696 struct {
697 __be32 block_ptr;
698 __be32 tbl_entries_mask;
699 } __packed tbl_change_info;
700 } params;
701 } __packed port_mgmt_change;
702 } event;
703 u8 slave_id;
704 u8 reserved3[2];
705 u8 owner;
706 } __packed;
707
708 struct mlx4_init_port_param {
709 int set_guid0;
710 int set_node_guid;
711 int set_si_guid;
712 u16 mtu;
713 int port_width_cap;
714 u16 vl_cap;
715 u16 max_gid;
716 u16 max_pkey;
717 u64 guid0;
718 u64 node_guid;
719 u64 si_guid;
720 };
721
722 #define mlx4_foreach_port(port, dev, type) \
723 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
724 if ((type) == (dev)->caps.port_mask[(port)])
725
726 #define mlx4_foreach_non_ib_transport_port(port, dev) \
727 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
728 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
729
730 #define mlx4_foreach_ib_transport_port(port, dev) \
731 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
732 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
733 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
734
735 #define MLX4_INVALID_SLAVE_ID 0xFF
736
737 void handle_port_mgmt_change_event(struct work_struct *work);
738
739 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
740 {
741 return dev->caps.function;
742 }
743
744 static inline int mlx4_is_master(struct mlx4_dev *dev)
745 {
746 return dev->flags & MLX4_FLAG_MASTER;
747 }
748
749 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
750 {
751 return (qpn < dev->phys_caps.base_sqpn + 8 +
752 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
753 }
754
755 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
756 {
757 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
758
759 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
760 return 1;
761
762 return 0;
763 }
764
765 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
766 {
767 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
768 }
769
770 static inline int mlx4_is_slave(struct mlx4_dev *dev)
771 {
772 return dev->flags & MLX4_FLAG_SLAVE;
773 }
774
775 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
776 struct mlx4_buf *buf);
777 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
778 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
779 {
780 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
781 return buf->direct.buf + offset;
782 else
783 return buf->page_list[offset >> PAGE_SHIFT].buf +
784 (offset & (PAGE_SIZE - 1));
785 }
786
787 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
788 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
789 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
790 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
791
792 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
793 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
794 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
795 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
796
797 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
798 struct mlx4_mtt *mtt);
799 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
800 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
801
802 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
803 int npages, int page_shift, struct mlx4_mr *mr);
804 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
805 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
806 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
807 int start_index, int npages, u64 *page_list);
808 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
809 struct mlx4_buf *buf);
810
811 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
812 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
813
814 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
815 int size, int max_direct);
816 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
817 int size);
818
819 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
820 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
821 unsigned vector, int collapsed);
822 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
823
824 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
825 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
826
827 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
828 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
829
830 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
831 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
832 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
833 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
834 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
835
836 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
837 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
838
839 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
840 int block_mcast_loopback, enum mlx4_protocol prot);
841 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
842 enum mlx4_protocol prot);
843 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
844 u8 port, int block_mcast_loopback,
845 enum mlx4_protocol protocol, u64 *reg_id);
846 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
847 enum mlx4_protocol protocol, u64 reg_id);
848
849 enum {
850 MLX4_DOMAIN_UVERBS = 0x1000,
851 MLX4_DOMAIN_ETHTOOL = 0x2000,
852 MLX4_DOMAIN_RFS = 0x3000,
853 MLX4_DOMAIN_NIC = 0x5000,
854 };
855
856 enum mlx4_net_trans_rule_id {
857 MLX4_NET_TRANS_RULE_ID_ETH = 0,
858 MLX4_NET_TRANS_RULE_ID_IB,
859 MLX4_NET_TRANS_RULE_ID_IPV6,
860 MLX4_NET_TRANS_RULE_ID_IPV4,
861 MLX4_NET_TRANS_RULE_ID_TCP,
862 MLX4_NET_TRANS_RULE_ID_UDP,
863 MLX4_NET_TRANS_RULE_NUM, /* should be last */
864 };
865
866 extern const u16 __sw_id_hw[];
867
868 static inline int map_hw_to_sw_id(u16 header_id)
869 {
870
871 int i;
872 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
873 if (header_id == __sw_id_hw[i])
874 return i;
875 }
876 return -EINVAL;
877 }
878
879 enum mlx4_net_trans_promisc_mode {
880 MLX4_FS_PROMISC_NONE = 0,
881 MLX4_FS_PROMISC_UPLINK,
882 /* For future use. Not implemented yet */
883 MLX4_FS_PROMISC_FUNCTION_PORT,
884 MLX4_FS_PROMISC_ALL_MULTI,
885 };
886
887 struct mlx4_spec_eth {
888 u8 dst_mac[6];
889 u8 dst_mac_msk[6];
890 u8 src_mac[6];
891 u8 src_mac_msk[6];
892 u8 ether_type_enable;
893 __be16 ether_type;
894 __be16 vlan_id_msk;
895 __be16 vlan_id;
896 };
897
898 struct mlx4_spec_tcp_udp {
899 __be16 dst_port;
900 __be16 dst_port_msk;
901 __be16 src_port;
902 __be16 src_port_msk;
903 };
904
905 struct mlx4_spec_ipv4 {
906 __be32 dst_ip;
907 __be32 dst_ip_msk;
908 __be32 src_ip;
909 __be32 src_ip_msk;
910 };
911
912 struct mlx4_spec_ib {
913 __be32 r_qpn;
914 __be32 qpn_msk;
915 u8 dst_gid[16];
916 u8 dst_gid_msk[16];
917 };
918
919 struct mlx4_spec_list {
920 struct list_head list;
921 enum mlx4_net_trans_rule_id id;
922 union {
923 struct mlx4_spec_eth eth;
924 struct mlx4_spec_ib ib;
925 struct mlx4_spec_ipv4 ipv4;
926 struct mlx4_spec_tcp_udp tcp_udp;
927 };
928 };
929
930 enum mlx4_net_trans_hw_rule_queue {
931 MLX4_NET_TRANS_Q_FIFO,
932 MLX4_NET_TRANS_Q_LIFO,
933 };
934
935 struct mlx4_net_trans_rule {
936 struct list_head list;
937 enum mlx4_net_trans_hw_rule_queue queue_mode;
938 bool exclusive;
939 bool allow_loopback;
940 enum mlx4_net_trans_promisc_mode promisc_mode;
941 u8 port;
942 u16 priority;
943 u32 qpn;
944 };
945
946 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
947 enum mlx4_net_trans_promisc_mode mode);
948 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
949 enum mlx4_net_trans_promisc_mode mode);
950 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
951 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
952 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
953 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
954 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
955
956 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
957 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
958 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
959 int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
960 void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
961 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
962 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
963 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
964 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
965 u8 promisc);
966 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
967 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
968 u8 *pg, u16 *ratelimit);
969 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
970 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
971 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
972
973 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
974 int npages, u64 iova, u32 *lkey, u32 *rkey);
975 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
976 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
977 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
978 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
979 u32 *lkey, u32 *rkey);
980 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
981 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
982 int mlx4_test_interrupts(struct mlx4_dev *dev);
983 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
984 int *vector);
985 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
986
987 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
988 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
989
990 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
991 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
992
993 int mlx4_flow_attach(struct mlx4_dev *dev,
994 struct mlx4_net_trans_rule *rule, u64 *reg_id);
995 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
996
997 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
998 int i, int val);
999
1000 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1001
1002 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1003 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1004 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1005 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1006 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1007 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1008 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1009
1010 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1011 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1012
1013 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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