projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
net/mlx4_core: Add helper to query counters
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MIN_MSIX_P_PORT 5
50 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
51 (dev_cap).num_ports * MIN_MSIX_P_PORT)
52
53 #define MLX4_MAX_100M_UNITS_VAL 255 /*
54 * work around: can't set values
55 * greater then this value when
56 * using 100 Mbps units.
57 */
58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
60 #define MLX4_RATELIMIT_DEFAULT 0x00ff
61
62 #define MLX4_ROCE_MAX_GIDS 128
63 #define MLX4_ROCE_PF_GIDS 16
64
65 enum {
66 MLX4_FLAG_MSI_X = 1 << 0,
67 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
68 MLX4_FLAG_MASTER = 1 << 2,
69 MLX4_FLAG_SLAVE = 1 << 3,
70 MLX4_FLAG_SRIOV = 1 << 4,
71 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
72 MLX4_FLAG_BONDED = 1 << 7
73 };
74
75 enum {
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
78 };
79
80 enum {
81 MLX4_MAX_PORTS = 2,
82 MLX4_MAX_PORT_PKEYS = 128
83 };
84
85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
86 * These qkeys must not be allowed for general use. This is a 64k range,
87 * and to test for violation, we use the mask (protect against future chg).
88 */
89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
91
92 enum {
93 MLX4_BOARD_ID_LEN = 64
94 };
95
96 enum {
97 MLX4_MAX_NUM_PF = 16,
98 MLX4_MAX_NUM_VF = 126,
99 MLX4_MAX_NUM_VF_P_PORT = 64,
100 MLX4_MFUNC_MAX = 128,
101 MLX4_MAX_EQ_NUM = 1024,
102 MLX4_MFUNC_EQ_NUM = 4,
103 MLX4_MFUNC_MAX_EQES = 8,
104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
105 };
106
107 /* Driver supports 3 diffrent device methods to manage traffic steering:
108 * -device managed - High level API for ib and eth flow steering. FW is
109 * managing flow steering tables.
110 * - B0 steering mode - Common low level API for ib and (if supported) eth.
111 * - A0 steering mode - Limited low level API for eth. In case of IB,
112 * B0 mode is in use.
113 */
114 enum {
115 MLX4_STEERING_MODE_A0,
116 MLX4_STEERING_MODE_B0,
117 MLX4_STEERING_MODE_DEVICE_MANAGED
118 };
119
120 enum {
121 MLX4_STEERING_DMFS_A0_DEFAULT,
122 MLX4_STEERING_DMFS_A0_DYNAMIC,
123 MLX4_STEERING_DMFS_A0_STATIC,
124 MLX4_STEERING_DMFS_A0_DISABLE,
125 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
126 };
127
128 static inline const char *mlx4_steering_mode_str(int steering_mode)
129 {
130 switch (steering_mode) {
131 case MLX4_STEERING_MODE_A0:
132 return "A0 steering";
133
134 case MLX4_STEERING_MODE_B0:
135 return "B0 steering";
136
137 case MLX4_STEERING_MODE_DEVICE_MANAGED:
138 return "Device managed flow steering";
139
140 default:
141 return "Unrecognize steering mode";
142 }
143 }
144
145 enum {
146 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
147 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
148 };
149
150 enum {
151 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
152 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
153 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
154 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
155 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
156 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
157 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
158 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
159 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
160 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
161 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
162 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
163 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
164 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
165 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
166 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
167 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
168 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
169 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
170 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
171 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
172 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
173 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
174 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
175 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
176 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
177 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
178 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
179 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
180 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
181 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
182 };
183
184 enum {
185 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
186 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
187 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
188 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
189 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
190 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
191 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
192 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
193 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
194 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
195 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
196 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
197 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
198 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
199 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
200 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
201 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
202 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
203 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
204 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
205 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
206 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
207 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
208 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
209 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
210 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
211 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
212 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
213 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
214 };
215
216 enum {
217 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
218 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
219 };
220
221 enum {
222 MLX4_VF_CAP_FLAG_RESET = 1 << 0
223 };
224
225 /* bit enums for an 8-bit flags field indicating special use
226 * QPs which require special handling in qp_reserve_range.
227 * Currently, this only includes QPs used by the ETH interface,
228 * where we expect to use blueflame. These QPs must not have
229 * bits 6 and 7 set in their qp number.
230 *
231 * This enum may use only bits 0..7.
232 */
233 enum {
234 MLX4_RESERVE_A0_QP = 1 << 6,
235 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
236 };
237
238 enum {
239 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
240 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
241 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
242 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
243 };
244
245 enum {
246 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
247 };
248
249 enum {
250 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
251 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
252 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
253 };
254
255
256 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
257
258 enum {
259 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
260 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
261 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
262 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
263 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
264 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
265 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
266 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
267 };
268
269 enum {
270 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
271 };
272
273 enum mlx4_event {
274 MLX4_EVENT_TYPE_COMP = 0x00,
275 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
276 MLX4_EVENT_TYPE_COMM_EST = 0x02,
277 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
278 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
279 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
280 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
281 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
282 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
283 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
284 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
285 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
286 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
287 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
288 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
289 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
290 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
291 MLX4_EVENT_TYPE_CMD = 0x0a,
292 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
293 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
294 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
295 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
296 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
297 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
298 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
299 MLX4_EVENT_TYPE_NONE = 0xff,
300 };
301
302 enum {
303 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
304 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
305 };
306
307 enum {
308 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
309 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
310 };
311
312 enum {
313 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
314 };
315
316 enum slave_port_state {
317 SLAVE_PORT_DOWN = 0,
318 SLAVE_PENDING_UP,
319 SLAVE_PORT_UP,
320 };
321
322 enum slave_port_gen_event {
323 SLAVE_PORT_GEN_EVENT_DOWN = 0,
324 SLAVE_PORT_GEN_EVENT_UP,
325 SLAVE_PORT_GEN_EVENT_NONE,
326 };
327
328 enum slave_port_state_event {
329 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
330 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
331 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
332 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
333 };
334
335 enum {
336 MLX4_PERM_LOCAL_READ = 1 << 10,
337 MLX4_PERM_LOCAL_WRITE = 1 << 11,
338 MLX4_PERM_REMOTE_READ = 1 << 12,
339 MLX4_PERM_REMOTE_WRITE = 1 << 13,
340 MLX4_PERM_ATOMIC = 1 << 14,
341 MLX4_PERM_BIND_MW = 1 << 15,
342 MLX4_PERM_MASK = 0xFC00
343 };
344
345 enum {
346 MLX4_OPCODE_NOP = 0x00,
347 MLX4_OPCODE_SEND_INVAL = 0x01,
348 MLX4_OPCODE_RDMA_WRITE = 0x08,
349 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
350 MLX4_OPCODE_SEND = 0x0a,
351 MLX4_OPCODE_SEND_IMM = 0x0b,
352 MLX4_OPCODE_LSO = 0x0e,
353 MLX4_OPCODE_RDMA_READ = 0x10,
354 MLX4_OPCODE_ATOMIC_CS = 0x11,
355 MLX4_OPCODE_ATOMIC_FA = 0x12,
356 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
357 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
358 MLX4_OPCODE_BIND_MW = 0x18,
359 MLX4_OPCODE_FMR = 0x19,
360 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
361 MLX4_OPCODE_CONFIG_CMD = 0x1f,
362
363 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
364 MLX4_RECV_OPCODE_SEND = 0x01,
365 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
366 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
367
368 MLX4_CQE_OPCODE_ERROR = 0x1e,
369 MLX4_CQE_OPCODE_RESIZE = 0x16,
370 };
371
372 enum {
373 MLX4_STAT_RATE_OFFSET = 5
374 };
375
376 enum mlx4_protocol {
377 MLX4_PROT_IB_IPV6 = 0,
378 MLX4_PROT_ETH,
379 MLX4_PROT_IB_IPV4,
380 MLX4_PROT_FCOE
381 };
382
383 enum {
384 MLX4_MTT_FLAG_PRESENT = 1
385 };
386
387 enum mlx4_qp_region {
388 MLX4_QP_REGION_FW = 0,
389 MLX4_QP_REGION_RSS_RAW_ETH,
390 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
391 MLX4_QP_REGION_ETH_ADDR,
392 MLX4_QP_REGION_FC_ADDR,
393 MLX4_QP_REGION_FC_EXCH,
394 MLX4_NUM_QP_REGION
395 };
396
397 enum mlx4_port_type {
398 MLX4_PORT_TYPE_NONE = 0,
399 MLX4_PORT_TYPE_IB = 1,
400 MLX4_PORT_TYPE_ETH = 2,
401 MLX4_PORT_TYPE_AUTO = 3
402 };
403
404 enum mlx4_special_vlan_idx {
405 MLX4_NO_VLAN_IDX = 0,
406 MLX4_VLAN_MISS_IDX,
407 MLX4_VLAN_REGULAR
408 };
409
410 enum mlx4_steer_type {
411 MLX4_MC_STEER = 0,
412 MLX4_UC_STEER,
413 MLX4_NUM_STEERS
414 };
415
416 enum {
417 MLX4_NUM_FEXCH = 64 * 1024,
418 };
419
420 enum {
421 MLX4_MAX_FAST_REG_PAGES = 511,
422 };
423
424 enum {
425 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
426 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
427 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
428 };
429
430 /* Port mgmt change event handling */
431 enum {
432 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
433 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
434 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
435 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
436 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
437 };
438
439 enum {
440 MLX4_DEVICE_STATE_UP = 1 << 0,
441 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
442 };
443
444 enum {
445 MLX4_INTERFACE_STATE_UP = 1 << 0,
446 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
447 };
448
449 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
450 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
451
452 enum mlx4_module_id {
453 MLX4_MODULE_ID_SFP = 0x3,
454 MLX4_MODULE_ID_QSFP = 0xC,
455 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
456 MLX4_MODULE_ID_QSFP28 = 0x11,
457 };
458
459 enum { /* rl */
460 MLX4_QP_RATE_LIMIT_NONE = 0,
461 MLX4_QP_RATE_LIMIT_KBS = 1,
462 MLX4_QP_RATE_LIMIT_MBS = 2,
463 MLX4_QP_RATE_LIMIT_GBS = 3
464 };
465
466 struct mlx4_rate_limit_caps {
467 u16 num_rates; /* Number of different rates */
468 u8 min_unit;
469 u16 min_val;
470 u8 max_unit;
471 u16 max_val;
472 };
473
474 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
475 {
476 return (major << 32) | (minor << 16) | subminor;
477 }
478
479 struct mlx4_phys_caps {
480 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
481 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
482 u32 num_phys_eqs;
483 u32 base_sqpn;
484 u32 base_proxy_sqpn;
485 u32 base_tunnel_sqpn;
486 };
487
488 struct mlx4_caps {
489 u64 fw_ver;
490 u32 function;
491 int num_ports;
492 int vl_cap[MLX4_MAX_PORTS + 1];
493 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
494 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
495 u64 def_mac[MLX4_MAX_PORTS + 1];
496 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
497 int gid_table_len[MLX4_MAX_PORTS + 1];
498 int pkey_table_len[MLX4_MAX_PORTS + 1];
499 int trans_type[MLX4_MAX_PORTS + 1];
500 int vendor_oui[MLX4_MAX_PORTS + 1];
501 int wavelength[MLX4_MAX_PORTS + 1];
502 u64 trans_code[MLX4_MAX_PORTS + 1];
503 int local_ca_ack_delay;
504 int num_uars;
505 u32 uar_page_size;
506 int bf_reg_size;
507 int bf_regs_per_page;
508 int max_sq_sg;
509 int max_rq_sg;
510 int num_qps;
511 int max_wqes;
512 int max_sq_desc_sz;
513 int max_rq_desc_sz;
514 int max_qp_init_rdma;
515 int max_qp_dest_rdma;
516 u32 *qp0_qkey;
517 u32 *qp0_proxy;
518 u32 *qp1_proxy;
519 u32 *qp0_tunnel;
520 u32 *qp1_tunnel;
521 int num_srqs;
522 int max_srq_wqes;
523 int max_srq_sge;
524 int reserved_srqs;
525 int num_cqs;
526 int max_cqes;
527 int reserved_cqs;
528 int num_sys_eqs;
529 int num_eqs;
530 int reserved_eqs;
531 int num_comp_vectors;
532 int num_mpts;
533 int max_fmr_maps;
534 int num_mtts;
535 int fmr_reserved_mtts;
536 int reserved_mtts;
537 int reserved_mrws;
538 int reserved_uars;
539 int num_mgms;
540 int num_amgms;
541 int reserved_mcgs;
542 int num_qp_per_mgm;
543 int steering_mode;
544 int dmfs_high_steer_mode;
545 int fs_log_max_ucast_qp_range_size;
546 int num_pds;
547 int reserved_pds;
548 int max_xrcds;
549 int reserved_xrcds;
550 int mtt_entry_sz;
551 u32 max_msg_sz;
552 u32 page_size_cap;
553 u64 flags;
554 u64 flags2;
555 u32 bmme_flags;
556 u32 reserved_lkey;
557 u16 stat_rate_support;
558 u8 port_width_cap[MLX4_MAX_PORTS + 1];
559 int max_gso_sz;
560 int max_rss_tbl_sz;
561 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
562 int reserved_qps;
563 int reserved_qps_base[MLX4_NUM_QP_REGION];
564 int log_num_macs;
565 int log_num_vlans;
566 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
567 u8 supported_type[MLX4_MAX_PORTS + 1];
568 u8 suggested_type[MLX4_MAX_PORTS + 1];
569 u8 default_sense[MLX4_MAX_PORTS + 1];
570 u32 port_mask[MLX4_MAX_PORTS + 1];
571 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
572 u32 max_counters;
573 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
574 u16 sqp_demux;
575 u32 eqe_size;
576 u32 cqe_size;
577 u8 eqe_factor;
578 u32 userspace_caps; /* userspace must be aware of these */
579 u32 function_caps; /* VFs must be aware of these */
580 u16 hca_core_clock;
581 u64 phys_port_id[MLX4_MAX_PORTS + 1];
582 int tunnel_offload_mode;
583 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
584 u8 alloc_res_qp_mask;
585 u32 dmfs_high_rate_qpn_base;
586 u32 dmfs_high_rate_qpn_range;
587 u32 vf_caps;
588 struct mlx4_rate_limit_caps rl_caps;
589 };
590
591 struct mlx4_buf_list {
592 void *buf;
593 dma_addr_t map;
594 };
595
596 struct mlx4_buf {
597 struct mlx4_buf_list direct;
598 struct mlx4_buf_list *page_list;
599 int nbufs;
600 int npages;
601 int page_shift;
602 };
603
604 struct mlx4_mtt {
605 u32 offset;
606 int order;
607 int page_shift;
608 };
609
610 enum {
611 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
612 };
613
614 struct mlx4_db_pgdir {
615 struct list_head list;
616 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
617 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
618 unsigned long *bits[2];
619 __be32 *db_page;
620 dma_addr_t db_dma;
621 };
622
623 struct mlx4_ib_user_db_page;
624
625 struct mlx4_db {
626 __be32 *db;
627 union {
628 struct mlx4_db_pgdir *pgdir;
629 struct mlx4_ib_user_db_page *user_page;
630 } u;
631 dma_addr_t dma;
632 int index;
633 int order;
634 };
635
636 struct mlx4_hwq_resources {
637 struct mlx4_db db;
638 struct mlx4_mtt mtt;
639 struct mlx4_buf buf;
640 };
641
642 struct mlx4_mr {
643 struct mlx4_mtt mtt;
644 u64 iova;
645 u64 size;
646 u32 key;
647 u32 pd;
648 u32 access;
649 int enabled;
650 };
651
652 enum mlx4_mw_type {
653 MLX4_MW_TYPE_1 = 1,
654 MLX4_MW_TYPE_2 = 2,
655 };
656
657 struct mlx4_mw {
658 u32 key;
659 u32 pd;
660 enum mlx4_mw_type type;
661 int enabled;
662 };
663
664 struct mlx4_fmr {
665 struct mlx4_mr mr;
666 struct mlx4_mpt_entry *mpt;
667 __be64 *mtts;
668 dma_addr_t dma_handle;
669 int max_pages;
670 int max_maps;
671 int maps;
672 u8 page_shift;
673 };
674
675 struct mlx4_uar {
676 unsigned long pfn;
677 int index;
678 struct list_head bf_list;
679 unsigned free_bf_bmap;
680 void __iomem *map;
681 void __iomem *bf_map;
682 };
683
684 struct mlx4_bf {
685 unsigned int offset;
686 int buf_size;
687 struct mlx4_uar *uar;
688 void __iomem *reg;
689 };
690
691 struct mlx4_cq {
692 void (*comp) (struct mlx4_cq *);
693 void (*event) (struct mlx4_cq *, enum mlx4_event);
694
695 struct mlx4_uar *uar;
696
697 u32 cons_index;
698
699 u16 irq;
700 __be32 *set_ci_db;
701 __be32 *arm_db;
702 int arm_sn;
703
704 int cqn;
705 unsigned vector;
706
707 atomic_t refcount;
708 struct completion free;
709 struct {
710 struct list_head list;
711 void (*comp)(struct mlx4_cq *);
712 void *priv;
713 } tasklet_ctx;
714 int reset_notify_added;
715 struct list_head reset_notify;
716 };
717
718 struct mlx4_qp {
719 void (*event) (struct mlx4_qp *, enum mlx4_event);
720
721 int qpn;
722
723 atomic_t refcount;
724 struct completion free;
725 };
726
727 struct mlx4_srq {
728 void (*event) (struct mlx4_srq *, enum mlx4_event);
729
730 int srqn;
731 int max;
732 int max_gs;
733 int wqe_shift;
734
735 atomic_t refcount;
736 struct completion free;
737 };
738
739 struct mlx4_av {
740 __be32 port_pd;
741 u8 reserved1;
742 u8 g_slid;
743 __be16 dlid;
744 u8 reserved2;
745 u8 gid_index;
746 u8 stat_rate;
747 u8 hop_limit;
748 __be32 sl_tclass_flowlabel;
749 u8 dgid[16];
750 };
751
752 struct mlx4_eth_av {
753 __be32 port_pd;
754 u8 reserved1;
755 u8 smac_idx;
756 u16 reserved2;
757 u8 reserved3;
758 u8 gid_index;
759 u8 stat_rate;
760 u8 hop_limit;
761 __be32 sl_tclass_flowlabel;
762 u8 dgid[16];
763 u8 s_mac[6];
764 u8 reserved4[2];
765 __be16 vlan;
766 u8 mac[ETH_ALEN];
767 };
768
769 union mlx4_ext_av {
770 struct mlx4_av ib;
771 struct mlx4_eth_av eth;
772 };
773
774 /* Counters should be saturate once they reach their maximum value */
775 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
776 if ((value) > U32_MAX) \
777 counter = cpu_to_be32(U32_MAX); \
778 else \
779 counter = cpu_to_be32(value); \
780 } while (0)
781
782 struct mlx4_counter {
783 u8 reserved1[3];
784 u8 counter_mode;
785 __be32 num_ifc;
786 u32 reserved2[2];
787 __be64 rx_frames;
788 __be64 rx_bytes;
789 __be64 tx_frames;
790 __be64 tx_bytes;
791 };
792
793 struct mlx4_quotas {
794 int qp;
795 int cq;
796 int srq;
797 int mpt;
798 int mtt;
799 int counter;
800 int xrcd;
801 };
802
803 struct mlx4_vf_dev {
804 u8 min_port;
805 u8 n_ports;
806 };
807
808 struct mlx4_dev_persistent {
809 struct pci_dev *pdev;
810 struct mlx4_dev *dev;
811 int nvfs[MLX4_MAX_PORTS + 1];
812 int num_vfs;
813 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
814 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
815 struct work_struct catas_work;
816 struct workqueue_struct *catas_wq;
817 struct mutex device_state_mutex; /* protect HW state */
818 u8 state;
819 struct mutex interface_state_mutex; /* protect SW state */
820 u8 interface_state;
821 };
822
823 struct mlx4_dev {
824 struct mlx4_dev_persistent *persist;
825 unsigned long flags;
826 unsigned long num_slaves;
827 struct mlx4_caps caps;
828 struct mlx4_phys_caps phys_caps;
829 struct mlx4_quotas quotas;
830 struct radix_tree_root qp_table_tree;
831 u8 rev_id;
832 char board_id[MLX4_BOARD_ID_LEN];
833 int numa_node;
834 int oper_log_mgm_entry_size;
835 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
836 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
837 struct mlx4_vf_dev *dev_vfs;
838 };
839
840 struct mlx4_eqe {
841 u8 reserved1;
842 u8 type;
843 u8 reserved2;
844 u8 subtype;
845 union {
846 u32 raw[6];
847 struct {
848 __be32 cqn;
849 } __packed comp;
850 struct {
851 u16 reserved1;
852 __be16 token;
853 u32 reserved2;
854 u8 reserved3[3];
855 u8 status;
856 __be64 out_param;
857 } __packed cmd;
858 struct {
859 __be32 qpn;
860 } __packed qp;
861 struct {
862 __be32 srqn;
863 } __packed srq;
864 struct {
865 __be32 cqn;
866 u32 reserved1;
867 u8 reserved2[3];
868 u8 syndrome;
869 } __packed cq_err;
870 struct {
871 u32 reserved1[2];
872 __be32 port;
873 } __packed port_change;
874 struct {
875 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
876 u32 reserved;
877 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
878 } __packed comm_channel_arm;
879 struct {
880 u8 port;
881 u8 reserved[3];
882 __be64 mac;
883 } __packed mac_update;
884 struct {
885 __be32 slave_id;
886 } __packed flr_event;
887 struct {
888 __be16 current_temperature;
889 __be16 warning_threshold;
890 } __packed warming;
891 struct {
892 u8 reserved[3];
893 u8 port;
894 union {
895 struct {
896 __be16 mstr_sm_lid;
897 __be16 port_lid;
898 __be32 changed_attr;
899 u8 reserved[3];
900 u8 mstr_sm_sl;
901 __be64 gid_prefix;
902 } __packed port_info;
903 struct {
904 __be32 block_ptr;
905 __be32 tbl_entries_mask;
906 } __packed tbl_change_info;
907 } params;
908 } __packed port_mgmt_change;
909 struct {
910 u8 reserved[3];
911 u8 port;
912 u32 reserved1[5];
913 } __packed bad_cable;
914 } event;
915 u8 slave_id;
916 u8 reserved3[2];
917 u8 owner;
918 } __packed;
919
920 struct mlx4_init_port_param {
921 int set_guid0;
922 int set_node_guid;
923 int set_si_guid;
924 u16 mtu;
925 int port_width_cap;
926 u16 vl_cap;
927 u16 max_gid;
928 u16 max_pkey;
929 u64 guid0;
930 u64 node_guid;
931 u64 si_guid;
932 };
933
934 #define MAD_IFC_DATA_SZ 192
935 /* MAD IFC Mailbox */
936 struct mlx4_mad_ifc {
937 u8 base_version;
938 u8 mgmt_class;
939 u8 class_version;
940 u8 method;
941 __be16 status;
942 __be16 class_specific;
943 __be64 tid;
944 __be16 attr_id;
945 __be16 resv;
946 __be32 attr_mod;
947 __be64 mkey;
948 __be16 dr_slid;
949 __be16 dr_dlid;
950 u8 reserved[28];
951 u8 data[MAD_IFC_DATA_SZ];
952 } __packed;
953
954 #define mlx4_foreach_port(port, dev, type) \
955 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
956 if ((type) == (dev)->caps.port_mask[(port)])
957
958 #define mlx4_foreach_non_ib_transport_port(port, dev) \
959 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
960 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
961
962 #define mlx4_foreach_ib_transport_port(port, dev) \
963 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
964 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
965 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
966
967 #define MLX4_INVALID_SLAVE_ID 0xFF
968 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
969
970 void handle_port_mgmt_change_event(struct work_struct *work);
971
972 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
973 {
974 return dev->caps.function;
975 }
976
977 static inline int mlx4_is_master(struct mlx4_dev *dev)
978 {
979 return dev->flags & MLX4_FLAG_MASTER;
980 }
981
982 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
983 {
984 return dev->phys_caps.base_sqpn + 8 +
985 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
986 }
987
988 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
989 {
990 return (qpn < dev->phys_caps.base_sqpn + 8 +
991 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
992 qpn >= dev->phys_caps.base_sqpn) ||
993 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
994 }
995
996 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
997 {
998 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
999
1000 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1001 return 1;
1002
1003 return 0;
1004 }
1005
1006 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1007 {
1008 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1009 }
1010
1011 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1012 {
1013 return dev->flags & MLX4_FLAG_SLAVE;
1014 }
1015
1016 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1017 {
1018 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1019 }
1020
1021 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1022 struct mlx4_buf *buf, gfp_t gfp);
1023 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1024 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1025 {
1026 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
1027 return buf->direct.buf + offset;
1028 else
1029 return buf->page_list[offset >> PAGE_SHIFT].buf +
1030 (offset & (PAGE_SIZE - 1));
1031 }
1032
1033 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1034 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1035 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1036 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1037
1038 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1039 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1040 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1041 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1042
1043 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1044 struct mlx4_mtt *mtt);
1045 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1046 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1047
1048 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1049 int npages, int page_shift, struct mlx4_mr *mr);
1050 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1051 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1052 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1053 struct mlx4_mw *mw);
1054 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1055 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1056 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1057 int start_index, int npages, u64 *page_list);
1058 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1059 struct mlx4_buf *buf, gfp_t gfp);
1060
1061 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1062 gfp_t gfp);
1063 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1064
1065 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1066 int size, int max_direct);
1067 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1068 int size);
1069
1070 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1071 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1072 unsigned vector, int collapsed, int timestamp_en);
1073 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1074 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1075 int *base, u8 flags);
1076 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1077
1078 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1079 gfp_t gfp);
1080 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1081
1082 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1083 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1084 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1085 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1086 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1087
1088 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1089 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1090
1091 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1092 int block_mcast_loopback, enum mlx4_protocol prot);
1093 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1094 enum mlx4_protocol prot);
1095 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1096 u8 port, int block_mcast_loopback,
1097 enum mlx4_protocol protocol, u64 *reg_id);
1098 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1099 enum mlx4_protocol protocol, u64 reg_id);
1100
1101 enum {
1102 MLX4_DOMAIN_UVERBS = 0x1000,
1103 MLX4_DOMAIN_ETHTOOL = 0x2000,
1104 MLX4_DOMAIN_RFS = 0x3000,
1105 MLX4_DOMAIN_NIC = 0x5000,
1106 };
1107
1108 enum mlx4_net_trans_rule_id {
1109 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1110 MLX4_NET_TRANS_RULE_ID_IB,
1111 MLX4_NET_TRANS_RULE_ID_IPV6,
1112 MLX4_NET_TRANS_RULE_ID_IPV4,
1113 MLX4_NET_TRANS_RULE_ID_TCP,
1114 MLX4_NET_TRANS_RULE_ID_UDP,
1115 MLX4_NET_TRANS_RULE_ID_VXLAN,
1116 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1117 };
1118
1119 extern const u16 __sw_id_hw[];
1120
1121 static inline int map_hw_to_sw_id(u16 header_id)
1122 {
1123
1124 int i;
1125 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1126 if (header_id == __sw_id_hw[i])
1127 return i;
1128 }
1129 return -EINVAL;
1130 }
1131
1132 enum mlx4_net_trans_promisc_mode {
1133 MLX4_FS_REGULAR = 1,
1134 MLX4_FS_ALL_DEFAULT,
1135 MLX4_FS_MC_DEFAULT,
1136 MLX4_FS_UC_SNIFFER,
1137 MLX4_FS_MC_SNIFFER,
1138 MLX4_FS_MODE_NUM, /* should be last */
1139 };
1140
1141 struct mlx4_spec_eth {
1142 u8 dst_mac[ETH_ALEN];
1143 u8 dst_mac_msk[ETH_ALEN];
1144 u8 src_mac[ETH_ALEN];
1145 u8 src_mac_msk[ETH_ALEN];
1146 u8 ether_type_enable;
1147 __be16 ether_type;
1148 __be16 vlan_id_msk;
1149 __be16 vlan_id;
1150 };
1151
1152 struct mlx4_spec_tcp_udp {
1153 __be16 dst_port;
1154 __be16 dst_port_msk;
1155 __be16 src_port;
1156 __be16 src_port_msk;
1157 };
1158
1159 struct mlx4_spec_ipv4 {
1160 __be32 dst_ip;
1161 __be32 dst_ip_msk;
1162 __be32 src_ip;
1163 __be32 src_ip_msk;
1164 };
1165
1166 struct mlx4_spec_ib {
1167 __be32 l3_qpn;
1168 __be32 qpn_msk;
1169 u8 dst_gid[16];
1170 u8 dst_gid_msk[16];
1171 };
1172
1173 struct mlx4_spec_vxlan {
1174 __be32 vni;
1175 __be32 vni_mask;
1176
1177 };
1178
1179 struct mlx4_spec_list {
1180 struct list_head list;
1181 enum mlx4_net_trans_rule_id id;
1182 union {
1183 struct mlx4_spec_eth eth;
1184 struct mlx4_spec_ib ib;
1185 struct mlx4_spec_ipv4 ipv4;
1186 struct mlx4_spec_tcp_udp tcp_udp;
1187 struct mlx4_spec_vxlan vxlan;
1188 };
1189 };
1190
1191 enum mlx4_net_trans_hw_rule_queue {
1192 MLX4_NET_TRANS_Q_FIFO,
1193 MLX4_NET_TRANS_Q_LIFO,
1194 };
1195
1196 struct mlx4_net_trans_rule {
1197 struct list_head list;
1198 enum mlx4_net_trans_hw_rule_queue queue_mode;
1199 bool exclusive;
1200 bool allow_loopback;
1201 enum mlx4_net_trans_promisc_mode promisc_mode;
1202 u8 port;
1203 u16 priority;
1204 u32 qpn;
1205 };
1206
1207 struct mlx4_net_trans_rule_hw_ctrl {
1208 __be16 prio;
1209 u8 type;
1210 u8 flags;
1211 u8 rsvd1;
1212 u8 funcid;
1213 u8 vep;
1214 u8 port;
1215 __be32 qpn;
1216 __be32 rsvd2;
1217 };
1218
1219 struct mlx4_net_trans_rule_hw_ib {
1220 u8 size;
1221 u8 rsvd1;
1222 __be16 id;
1223 u32 rsvd2;
1224 __be32 l3_qpn;
1225 __be32 qpn_mask;
1226 u8 dst_gid[16];
1227 u8 dst_gid_msk[16];
1228 } __packed;
1229
1230 struct mlx4_net_trans_rule_hw_eth {
1231 u8 size;
1232 u8 rsvd;
1233 __be16 id;
1234 u8 rsvd1[6];
1235 u8 dst_mac[6];
1236 u16 rsvd2;
1237 u8 dst_mac_msk[6];
1238 u16 rsvd3;
1239 u8 src_mac[6];
1240 u16 rsvd4;
1241 u8 src_mac_msk[6];
1242 u8 rsvd5;
1243 u8 ether_type_enable;
1244 __be16 ether_type;
1245 __be16 vlan_tag_msk;
1246 __be16 vlan_tag;
1247 } __packed;
1248
1249 struct mlx4_net_trans_rule_hw_tcp_udp {
1250 u8 size;
1251 u8 rsvd;
1252 __be16 id;
1253 __be16 rsvd1[3];
1254 __be16 dst_port;
1255 __be16 rsvd2;
1256 __be16 dst_port_msk;
1257 __be16 rsvd3;
1258 __be16 src_port;
1259 __be16 rsvd4;
1260 __be16 src_port_msk;
1261 } __packed;
1262
1263 struct mlx4_net_trans_rule_hw_ipv4 {
1264 u8 size;
1265 u8 rsvd;
1266 __be16 id;
1267 __be32 rsvd1;
1268 __be32 dst_ip;
1269 __be32 dst_ip_msk;
1270 __be32 src_ip;
1271 __be32 src_ip_msk;
1272 } __packed;
1273
1274 struct mlx4_net_trans_rule_hw_vxlan {
1275 u8 size;
1276 u8 rsvd;
1277 __be16 id;
1278 __be32 rsvd1;
1279 __be32 vni;
1280 __be32 vni_mask;
1281 } __packed;
1282
1283 struct _rule_hw {
1284 union {
1285 struct {
1286 u8 size;
1287 u8 rsvd;
1288 __be16 id;
1289 };
1290 struct mlx4_net_trans_rule_hw_eth eth;
1291 struct mlx4_net_trans_rule_hw_ib ib;
1292 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1293 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1294 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1295 };
1296 };
1297
1298 enum {
1299 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1300 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1301 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1302 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1303 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1304 };
1305
1306
1307 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1308 enum mlx4_net_trans_promisc_mode mode);
1309 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1310 enum mlx4_net_trans_promisc_mode mode);
1311 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1312 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1313 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1314 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1315 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1316
1317 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1318 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1319 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1320 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1321 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1322 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1323 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1324 u8 promisc);
1325 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1326 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1327 u8 ignore_fcs_value);
1328 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1329 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1330 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1331 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1332 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1333
1334 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1335 int npages, u64 iova, u32 *lkey, u32 *rkey);
1336 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1337 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1338 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1339 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1340 u32 *lkey, u32 *rkey);
1341 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1342 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1343 int mlx4_test_interrupts(struct mlx4_dev *dev);
1344 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1345 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1346 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1347 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1348 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1349
1350 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1351 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1352
1353 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1354 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1355 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1356
1357 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1358 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1359 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1360
1361 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1362 int port);
1363 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1364 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1365 int mlx4_flow_attach(struct mlx4_dev *dev,
1366 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1367 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1368 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1369 enum mlx4_net_trans_promisc_mode flow_type);
1370 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1371 enum mlx4_net_trans_rule_id id);
1372 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1373
1374 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1375 int port, int qpn, u16 prio, u64 *reg_id);
1376
1377 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1378 int i, int val);
1379
1380 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1381
1382 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1383 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1384 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1385 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1386 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1387 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1388 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1389
1390 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1391 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1392
1393 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1394 int *slave_id);
1395 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1396 u8 *gid);
1397
1398 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1399 u32 max_range_qpn);
1400
1401 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1402
1403 struct mlx4_active_ports {
1404 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1405 };
1406 /* Returns a bitmap of the physical ports which are assigned to slave */
1407 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1408
1409 /* Returns the physical port that represents the virtual port of the slave, */
1410 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1411 /* mapping is returned. */
1412 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1413
1414 struct mlx4_slaves_pport {
1415 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1416 };
1417 /* Returns a bitmap of all slaves that are assigned to port. */
1418 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1419 int port);
1420
1421 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1422 /* the ports that are set in crit_ports. */
1423 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1424 struct mlx4_dev *dev,
1425 const struct mlx4_active_ports *crit_ports);
1426
1427 /* Returns the slave's virtual port that represents the physical port. */
1428 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1429
1430 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1431
1432 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1433 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1434 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1435 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1436 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1437 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1438 int enable);
1439 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1440 struct mlx4_mpt_entry ***mpt_entry);
1441 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1442 struct mlx4_mpt_entry **mpt_entry);
1443 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1444 u32 pdn);
1445 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1446 struct mlx4_mpt_entry *mpt_entry,
1447 u32 access);
1448 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1449 struct mlx4_mpt_entry **mpt_entry);
1450 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1451 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1452 u64 iova, u64 size, int npages,
1453 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1454
1455 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1456 u16 offset, u16 size, u8 *data);
1457
1458 /* Returns true if running in low memory profile (kdump kernel) */
1459 static inline bool mlx4_low_memory_profile(void)
1460 {
1461 return is_kdump_kernel();
1462 }
1463
1464 /* ACCESS REG commands */
1465 enum mlx4_access_reg_method {
1466 MLX4_ACCESS_REG_QUERY = 0x1,
1467 MLX4_ACCESS_REG_WRITE = 0x2,
1468 };
1469
1470 /* ACCESS PTYS Reg command */
1471 enum mlx4_ptys_proto {
1472 MLX4_PTYS_IB = 1<<0,
1473 MLX4_PTYS_EN = 1<<2,
1474 };
1475
1476 struct mlx4_ptys_reg {
1477 u8 resrvd1;
1478 u8 local_port;
1479 u8 resrvd2;
1480 u8 proto_mask;
1481 __be32 resrvd3[2];
1482 __be32 eth_proto_cap;
1483 __be16 ib_width_cap;
1484 __be16 ib_speed_cap;
1485 __be32 resrvd4;
1486 __be32 eth_proto_admin;
1487 __be16 ib_width_admin;
1488 __be16 ib_speed_admin;
1489 __be32 resrvd5;
1490 __be32 eth_proto_oper;
1491 __be16 ib_width_oper;
1492 __be16 ib_speed_oper;
1493 __be32 resrvd6;
1494 __be32 eth_proto_lp_adv;
1495 } __packed;
1496
1497 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1498 enum mlx4_access_reg_method method,
1499 struct mlx4_ptys_reg *ptys_reg);
1500
1501 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
This page took 0.071841 seconds and 5 git commands to generate.