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net/mlx4: New file for QoS related firmware commands
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
51
52 #define MLX4_MAX_100M_UNITS_VAL 255 /*
53 * work around: can't set values
54 * greater then this value when
55 * using 100 Mbps units.
56 */
57 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
58 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
59 #define MLX4_RATELIMIT_DEFAULT 0x00ff
60
61 #define MLX4_ROCE_MAX_GIDS 128
62 #define MLX4_ROCE_PF_GIDS 16
63
64 enum {
65 MLX4_FLAG_MSI_X = 1 << 0,
66 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
67 MLX4_FLAG_MASTER = 1 << 2,
68 MLX4_FLAG_SLAVE = 1 << 3,
69 MLX4_FLAG_SRIOV = 1 << 4,
70 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
71 MLX4_FLAG_BONDED = 1 << 7
72 };
73
74 enum {
75 MLX4_PORT_CAP_IS_SM = 1 << 1,
76 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
77 };
78
79 enum {
80 MLX4_MAX_PORTS = 2,
81 MLX4_MAX_PORT_PKEYS = 128
82 };
83
84 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
85 * These qkeys must not be allowed for general use. This is a 64k range,
86 * and to test for violation, we use the mask (protect against future chg).
87 */
88 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
89 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
90
91 enum {
92 MLX4_BOARD_ID_LEN = 64
93 };
94
95 enum {
96 MLX4_MAX_NUM_PF = 16,
97 MLX4_MAX_NUM_VF = 126,
98 MLX4_MAX_NUM_VF_P_PORT = 64,
99 MLX4_MFUNC_MAX = 128,
100 MLX4_MAX_EQ_NUM = 1024,
101 MLX4_MFUNC_EQ_NUM = 4,
102 MLX4_MFUNC_MAX_EQES = 8,
103 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
104 };
105
106 /* Driver supports 3 diffrent device methods to manage traffic steering:
107 * -device managed - High level API for ib and eth flow steering. FW is
108 * managing flow steering tables.
109 * - B0 steering mode - Common low level API for ib and (if supported) eth.
110 * - A0 steering mode - Limited low level API for eth. In case of IB,
111 * B0 mode is in use.
112 */
113 enum {
114 MLX4_STEERING_MODE_A0,
115 MLX4_STEERING_MODE_B0,
116 MLX4_STEERING_MODE_DEVICE_MANAGED
117 };
118
119 enum {
120 MLX4_STEERING_DMFS_A0_DEFAULT,
121 MLX4_STEERING_DMFS_A0_DYNAMIC,
122 MLX4_STEERING_DMFS_A0_STATIC,
123 MLX4_STEERING_DMFS_A0_DISABLE,
124 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
125 };
126
127 static inline const char *mlx4_steering_mode_str(int steering_mode)
128 {
129 switch (steering_mode) {
130 case MLX4_STEERING_MODE_A0:
131 return "A0 steering";
132
133 case MLX4_STEERING_MODE_B0:
134 return "B0 steering";
135
136 case MLX4_STEERING_MODE_DEVICE_MANAGED:
137 return "Device managed flow steering";
138
139 default:
140 return "Unrecognize steering mode";
141 }
142 }
143
144 enum {
145 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
146 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
147 };
148
149 enum {
150 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
151 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
152 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
153 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
154 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
155 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
156 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
157 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
158 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
159 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
160 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
161 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
162 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
163 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
164 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
165 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
166 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
167 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
168 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
169 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
170 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
171 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
172 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
173 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
174 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
175 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
176 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
177 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
178 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
179 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
180 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
181 };
182
183 enum {
184 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
185 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
186 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
187 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
188 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
190 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
191 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
192 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
193 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
194 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
195 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
196 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
197 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
198 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
199 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
201 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
202 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
203 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
204 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
205 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
206 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
207 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
208 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24
209 };
210
211 enum {
212 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
213 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
214 };
215
216 enum {
217 MLX4_VF_CAP_FLAG_RESET = 1 << 0
218 };
219
220 /* bit enums for an 8-bit flags field indicating special use
221 * QPs which require special handling in qp_reserve_range.
222 * Currently, this only includes QPs used by the ETH interface,
223 * where we expect to use blueflame. These QPs must not have
224 * bits 6 and 7 set in their qp number.
225 *
226 * This enum may use only bits 0..7.
227 */
228 enum {
229 MLX4_RESERVE_A0_QP = 1 << 6,
230 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
231 };
232
233 enum {
234 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
235 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
236 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
237 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
238 };
239
240 enum {
241 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
242 };
243
244 enum {
245 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
246 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
247 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
248 };
249
250
251 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
252
253 enum {
254 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
255 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
256 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
257 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
258 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
259 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
260 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
261 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
262 };
263
264 enum {
265 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
266 };
267
268 enum mlx4_event {
269 MLX4_EVENT_TYPE_COMP = 0x00,
270 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
271 MLX4_EVENT_TYPE_COMM_EST = 0x02,
272 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
273 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
274 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
275 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
276 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
277 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
278 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
279 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
280 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
281 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
282 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
283 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
284 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
285 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
286 MLX4_EVENT_TYPE_CMD = 0x0a,
287 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
288 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
289 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
290 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
291 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
292 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
293 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
294 MLX4_EVENT_TYPE_NONE = 0xff,
295 };
296
297 enum {
298 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
299 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
300 };
301
302 enum {
303 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
304 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
305 };
306
307 enum {
308 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
309 };
310
311 enum slave_port_state {
312 SLAVE_PORT_DOWN = 0,
313 SLAVE_PENDING_UP,
314 SLAVE_PORT_UP,
315 };
316
317 enum slave_port_gen_event {
318 SLAVE_PORT_GEN_EVENT_DOWN = 0,
319 SLAVE_PORT_GEN_EVENT_UP,
320 SLAVE_PORT_GEN_EVENT_NONE,
321 };
322
323 enum slave_port_state_event {
324 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
325 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
326 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
327 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
328 };
329
330 enum {
331 MLX4_PERM_LOCAL_READ = 1 << 10,
332 MLX4_PERM_LOCAL_WRITE = 1 << 11,
333 MLX4_PERM_REMOTE_READ = 1 << 12,
334 MLX4_PERM_REMOTE_WRITE = 1 << 13,
335 MLX4_PERM_ATOMIC = 1 << 14,
336 MLX4_PERM_BIND_MW = 1 << 15,
337 MLX4_PERM_MASK = 0xFC00
338 };
339
340 enum {
341 MLX4_OPCODE_NOP = 0x00,
342 MLX4_OPCODE_SEND_INVAL = 0x01,
343 MLX4_OPCODE_RDMA_WRITE = 0x08,
344 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
345 MLX4_OPCODE_SEND = 0x0a,
346 MLX4_OPCODE_SEND_IMM = 0x0b,
347 MLX4_OPCODE_LSO = 0x0e,
348 MLX4_OPCODE_RDMA_READ = 0x10,
349 MLX4_OPCODE_ATOMIC_CS = 0x11,
350 MLX4_OPCODE_ATOMIC_FA = 0x12,
351 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
352 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
353 MLX4_OPCODE_BIND_MW = 0x18,
354 MLX4_OPCODE_FMR = 0x19,
355 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
356 MLX4_OPCODE_CONFIG_CMD = 0x1f,
357
358 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
359 MLX4_RECV_OPCODE_SEND = 0x01,
360 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
361 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
362
363 MLX4_CQE_OPCODE_ERROR = 0x1e,
364 MLX4_CQE_OPCODE_RESIZE = 0x16,
365 };
366
367 enum {
368 MLX4_STAT_RATE_OFFSET = 5
369 };
370
371 enum mlx4_protocol {
372 MLX4_PROT_IB_IPV6 = 0,
373 MLX4_PROT_ETH,
374 MLX4_PROT_IB_IPV4,
375 MLX4_PROT_FCOE
376 };
377
378 enum {
379 MLX4_MTT_FLAG_PRESENT = 1
380 };
381
382 enum mlx4_qp_region {
383 MLX4_QP_REGION_FW = 0,
384 MLX4_QP_REGION_RSS_RAW_ETH,
385 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
386 MLX4_QP_REGION_ETH_ADDR,
387 MLX4_QP_REGION_FC_ADDR,
388 MLX4_QP_REGION_FC_EXCH,
389 MLX4_NUM_QP_REGION
390 };
391
392 enum mlx4_port_type {
393 MLX4_PORT_TYPE_NONE = 0,
394 MLX4_PORT_TYPE_IB = 1,
395 MLX4_PORT_TYPE_ETH = 2,
396 MLX4_PORT_TYPE_AUTO = 3
397 };
398
399 enum mlx4_special_vlan_idx {
400 MLX4_NO_VLAN_IDX = 0,
401 MLX4_VLAN_MISS_IDX,
402 MLX4_VLAN_REGULAR
403 };
404
405 enum mlx4_steer_type {
406 MLX4_MC_STEER = 0,
407 MLX4_UC_STEER,
408 MLX4_NUM_STEERS
409 };
410
411 enum {
412 MLX4_NUM_FEXCH = 64 * 1024,
413 };
414
415 enum {
416 MLX4_MAX_FAST_REG_PAGES = 511,
417 };
418
419 enum {
420 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
421 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
422 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
423 };
424
425 /* Port mgmt change event handling */
426 enum {
427 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
428 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
429 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
430 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
431 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
432 };
433
434 enum {
435 MLX4_DEVICE_STATE_UP = 1 << 0,
436 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
437 };
438
439 enum {
440 MLX4_INTERFACE_STATE_UP = 1 << 0,
441 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
442 };
443
444 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
445 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
446
447 enum mlx4_module_id {
448 MLX4_MODULE_ID_SFP = 0x3,
449 MLX4_MODULE_ID_QSFP = 0xC,
450 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
451 MLX4_MODULE_ID_QSFP28 = 0x11,
452 };
453
454 enum { /* rl */
455 MLX4_QP_RATE_LIMIT_NONE = 0,
456 MLX4_QP_RATE_LIMIT_KBS = 1,
457 MLX4_QP_RATE_LIMIT_MBS = 2,
458 MLX4_QP_RATE_LIMIT_GBS = 3
459 };
460
461 struct mlx4_rate_limit_caps {
462 u16 num_rates; /* Number of different rates */
463 u8 min_unit;
464 u16 min_val;
465 u8 max_unit;
466 u16 max_val;
467 };
468
469 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
470 {
471 return (major << 32) | (minor << 16) | subminor;
472 }
473
474 struct mlx4_phys_caps {
475 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
476 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
477 u32 num_phys_eqs;
478 u32 base_sqpn;
479 u32 base_proxy_sqpn;
480 u32 base_tunnel_sqpn;
481 };
482
483 struct mlx4_caps {
484 u64 fw_ver;
485 u32 function;
486 int num_ports;
487 int vl_cap[MLX4_MAX_PORTS + 1];
488 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
489 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
490 u64 def_mac[MLX4_MAX_PORTS + 1];
491 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
492 int gid_table_len[MLX4_MAX_PORTS + 1];
493 int pkey_table_len[MLX4_MAX_PORTS + 1];
494 int trans_type[MLX4_MAX_PORTS + 1];
495 int vendor_oui[MLX4_MAX_PORTS + 1];
496 int wavelength[MLX4_MAX_PORTS + 1];
497 u64 trans_code[MLX4_MAX_PORTS + 1];
498 int local_ca_ack_delay;
499 int num_uars;
500 u32 uar_page_size;
501 int bf_reg_size;
502 int bf_regs_per_page;
503 int max_sq_sg;
504 int max_rq_sg;
505 int num_qps;
506 int max_wqes;
507 int max_sq_desc_sz;
508 int max_rq_desc_sz;
509 int max_qp_init_rdma;
510 int max_qp_dest_rdma;
511 u32 *qp0_qkey;
512 u32 *qp0_proxy;
513 u32 *qp1_proxy;
514 u32 *qp0_tunnel;
515 u32 *qp1_tunnel;
516 int num_srqs;
517 int max_srq_wqes;
518 int max_srq_sge;
519 int reserved_srqs;
520 int num_cqs;
521 int max_cqes;
522 int reserved_cqs;
523 int num_sys_eqs;
524 int num_eqs;
525 int reserved_eqs;
526 int num_comp_vectors;
527 int comp_pool;
528 int num_mpts;
529 int max_fmr_maps;
530 int num_mtts;
531 int fmr_reserved_mtts;
532 int reserved_mtts;
533 int reserved_mrws;
534 int reserved_uars;
535 int num_mgms;
536 int num_amgms;
537 int reserved_mcgs;
538 int num_qp_per_mgm;
539 int steering_mode;
540 int dmfs_high_steer_mode;
541 int fs_log_max_ucast_qp_range_size;
542 int num_pds;
543 int reserved_pds;
544 int max_xrcds;
545 int reserved_xrcds;
546 int mtt_entry_sz;
547 u32 max_msg_sz;
548 u32 page_size_cap;
549 u64 flags;
550 u64 flags2;
551 u32 bmme_flags;
552 u32 reserved_lkey;
553 u16 stat_rate_support;
554 u8 port_width_cap[MLX4_MAX_PORTS + 1];
555 int max_gso_sz;
556 int max_rss_tbl_sz;
557 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
558 int reserved_qps;
559 int reserved_qps_base[MLX4_NUM_QP_REGION];
560 int log_num_macs;
561 int log_num_vlans;
562 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
563 u8 supported_type[MLX4_MAX_PORTS + 1];
564 u8 suggested_type[MLX4_MAX_PORTS + 1];
565 u8 default_sense[MLX4_MAX_PORTS + 1];
566 u32 port_mask[MLX4_MAX_PORTS + 1];
567 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
568 u32 max_counters;
569 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
570 u16 sqp_demux;
571 u32 eqe_size;
572 u32 cqe_size;
573 u8 eqe_factor;
574 u32 userspace_caps; /* userspace must be aware of these */
575 u32 function_caps; /* VFs must be aware of these */
576 u16 hca_core_clock;
577 u64 phys_port_id[MLX4_MAX_PORTS + 1];
578 int tunnel_offload_mode;
579 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
580 u8 alloc_res_qp_mask;
581 u32 dmfs_high_rate_qpn_base;
582 u32 dmfs_high_rate_qpn_range;
583 u32 vf_caps;
584 struct mlx4_rate_limit_caps rl_caps;
585 };
586
587 struct mlx4_buf_list {
588 void *buf;
589 dma_addr_t map;
590 };
591
592 struct mlx4_buf {
593 struct mlx4_buf_list direct;
594 struct mlx4_buf_list *page_list;
595 int nbufs;
596 int npages;
597 int page_shift;
598 };
599
600 struct mlx4_mtt {
601 u32 offset;
602 int order;
603 int page_shift;
604 };
605
606 enum {
607 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
608 };
609
610 struct mlx4_db_pgdir {
611 struct list_head list;
612 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
613 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
614 unsigned long *bits[2];
615 __be32 *db_page;
616 dma_addr_t db_dma;
617 };
618
619 struct mlx4_ib_user_db_page;
620
621 struct mlx4_db {
622 __be32 *db;
623 union {
624 struct mlx4_db_pgdir *pgdir;
625 struct mlx4_ib_user_db_page *user_page;
626 } u;
627 dma_addr_t dma;
628 int index;
629 int order;
630 };
631
632 struct mlx4_hwq_resources {
633 struct mlx4_db db;
634 struct mlx4_mtt mtt;
635 struct mlx4_buf buf;
636 };
637
638 struct mlx4_mr {
639 struct mlx4_mtt mtt;
640 u64 iova;
641 u64 size;
642 u32 key;
643 u32 pd;
644 u32 access;
645 int enabled;
646 };
647
648 enum mlx4_mw_type {
649 MLX4_MW_TYPE_1 = 1,
650 MLX4_MW_TYPE_2 = 2,
651 };
652
653 struct mlx4_mw {
654 u32 key;
655 u32 pd;
656 enum mlx4_mw_type type;
657 int enabled;
658 };
659
660 struct mlx4_fmr {
661 struct mlx4_mr mr;
662 struct mlx4_mpt_entry *mpt;
663 __be64 *mtts;
664 dma_addr_t dma_handle;
665 int max_pages;
666 int max_maps;
667 int maps;
668 u8 page_shift;
669 };
670
671 struct mlx4_uar {
672 unsigned long pfn;
673 int index;
674 struct list_head bf_list;
675 unsigned free_bf_bmap;
676 void __iomem *map;
677 void __iomem *bf_map;
678 };
679
680 struct mlx4_bf {
681 unsigned int offset;
682 int buf_size;
683 struct mlx4_uar *uar;
684 void __iomem *reg;
685 };
686
687 struct mlx4_cq {
688 void (*comp) (struct mlx4_cq *);
689 void (*event) (struct mlx4_cq *, enum mlx4_event);
690
691 struct mlx4_uar *uar;
692
693 u32 cons_index;
694
695 u16 irq;
696 __be32 *set_ci_db;
697 __be32 *arm_db;
698 int arm_sn;
699
700 int cqn;
701 unsigned vector;
702
703 atomic_t refcount;
704 struct completion free;
705 struct {
706 struct list_head list;
707 void (*comp)(struct mlx4_cq *);
708 void *priv;
709 } tasklet_ctx;
710 int reset_notify_added;
711 struct list_head reset_notify;
712 };
713
714 struct mlx4_qp {
715 void (*event) (struct mlx4_qp *, enum mlx4_event);
716
717 int qpn;
718
719 atomic_t refcount;
720 struct completion free;
721 };
722
723 struct mlx4_srq {
724 void (*event) (struct mlx4_srq *, enum mlx4_event);
725
726 int srqn;
727 int max;
728 int max_gs;
729 int wqe_shift;
730
731 atomic_t refcount;
732 struct completion free;
733 };
734
735 struct mlx4_av {
736 __be32 port_pd;
737 u8 reserved1;
738 u8 g_slid;
739 __be16 dlid;
740 u8 reserved2;
741 u8 gid_index;
742 u8 stat_rate;
743 u8 hop_limit;
744 __be32 sl_tclass_flowlabel;
745 u8 dgid[16];
746 };
747
748 struct mlx4_eth_av {
749 __be32 port_pd;
750 u8 reserved1;
751 u8 smac_idx;
752 u16 reserved2;
753 u8 reserved3;
754 u8 gid_index;
755 u8 stat_rate;
756 u8 hop_limit;
757 __be32 sl_tclass_flowlabel;
758 u8 dgid[16];
759 u8 s_mac[6];
760 u8 reserved4[2];
761 __be16 vlan;
762 u8 mac[ETH_ALEN];
763 };
764
765 union mlx4_ext_av {
766 struct mlx4_av ib;
767 struct mlx4_eth_av eth;
768 };
769
770 struct mlx4_counter {
771 u8 reserved1[3];
772 u8 counter_mode;
773 __be32 num_ifc;
774 u32 reserved2[2];
775 __be64 rx_frames;
776 __be64 rx_bytes;
777 __be64 tx_frames;
778 __be64 tx_bytes;
779 };
780
781 struct mlx4_quotas {
782 int qp;
783 int cq;
784 int srq;
785 int mpt;
786 int mtt;
787 int counter;
788 int xrcd;
789 };
790
791 struct mlx4_vf_dev {
792 u8 min_port;
793 u8 n_ports;
794 };
795
796 struct mlx4_dev_persistent {
797 struct pci_dev *pdev;
798 struct mlx4_dev *dev;
799 int nvfs[MLX4_MAX_PORTS + 1];
800 int num_vfs;
801 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
802 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
803 struct work_struct catas_work;
804 struct workqueue_struct *catas_wq;
805 struct mutex device_state_mutex; /* protect HW state */
806 u8 state;
807 struct mutex interface_state_mutex; /* protect SW state */
808 u8 interface_state;
809 };
810
811 struct mlx4_dev {
812 struct mlx4_dev_persistent *persist;
813 unsigned long flags;
814 unsigned long num_slaves;
815 struct mlx4_caps caps;
816 struct mlx4_phys_caps phys_caps;
817 struct mlx4_quotas quotas;
818 struct radix_tree_root qp_table_tree;
819 u8 rev_id;
820 char board_id[MLX4_BOARD_ID_LEN];
821 int numa_node;
822 int oper_log_mgm_entry_size;
823 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
824 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
825 struct mlx4_vf_dev *dev_vfs;
826 };
827
828 struct mlx4_eqe {
829 u8 reserved1;
830 u8 type;
831 u8 reserved2;
832 u8 subtype;
833 union {
834 u32 raw[6];
835 struct {
836 __be32 cqn;
837 } __packed comp;
838 struct {
839 u16 reserved1;
840 __be16 token;
841 u32 reserved2;
842 u8 reserved3[3];
843 u8 status;
844 __be64 out_param;
845 } __packed cmd;
846 struct {
847 __be32 qpn;
848 } __packed qp;
849 struct {
850 __be32 srqn;
851 } __packed srq;
852 struct {
853 __be32 cqn;
854 u32 reserved1;
855 u8 reserved2[3];
856 u8 syndrome;
857 } __packed cq_err;
858 struct {
859 u32 reserved1[2];
860 __be32 port;
861 } __packed port_change;
862 struct {
863 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
864 u32 reserved;
865 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
866 } __packed comm_channel_arm;
867 struct {
868 u8 port;
869 u8 reserved[3];
870 __be64 mac;
871 } __packed mac_update;
872 struct {
873 __be32 slave_id;
874 } __packed flr_event;
875 struct {
876 __be16 current_temperature;
877 __be16 warning_threshold;
878 } __packed warming;
879 struct {
880 u8 reserved[3];
881 u8 port;
882 union {
883 struct {
884 __be16 mstr_sm_lid;
885 __be16 port_lid;
886 __be32 changed_attr;
887 u8 reserved[3];
888 u8 mstr_sm_sl;
889 __be64 gid_prefix;
890 } __packed port_info;
891 struct {
892 __be32 block_ptr;
893 __be32 tbl_entries_mask;
894 } __packed tbl_change_info;
895 } params;
896 } __packed port_mgmt_change;
897 struct {
898 u8 reserved[3];
899 u8 port;
900 u32 reserved1[5];
901 } __packed bad_cable;
902 } event;
903 u8 slave_id;
904 u8 reserved3[2];
905 u8 owner;
906 } __packed;
907
908 struct mlx4_init_port_param {
909 int set_guid0;
910 int set_node_guid;
911 int set_si_guid;
912 u16 mtu;
913 int port_width_cap;
914 u16 vl_cap;
915 u16 max_gid;
916 u16 max_pkey;
917 u64 guid0;
918 u64 node_guid;
919 u64 si_guid;
920 };
921
922 #define MAD_IFC_DATA_SZ 192
923 /* MAD IFC Mailbox */
924 struct mlx4_mad_ifc {
925 u8 base_version;
926 u8 mgmt_class;
927 u8 class_version;
928 u8 method;
929 __be16 status;
930 __be16 class_specific;
931 __be64 tid;
932 __be16 attr_id;
933 __be16 resv;
934 __be32 attr_mod;
935 __be64 mkey;
936 __be16 dr_slid;
937 __be16 dr_dlid;
938 u8 reserved[28];
939 u8 data[MAD_IFC_DATA_SZ];
940 } __packed;
941
942 #define mlx4_foreach_port(port, dev, type) \
943 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
944 if ((type) == (dev)->caps.port_mask[(port)])
945
946 #define mlx4_foreach_non_ib_transport_port(port, dev) \
947 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
948 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
949
950 #define mlx4_foreach_ib_transport_port(port, dev) \
951 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
952 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
953 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
954
955 #define MLX4_INVALID_SLAVE_ID 0xFF
956
957 void handle_port_mgmt_change_event(struct work_struct *work);
958
959 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
960 {
961 return dev->caps.function;
962 }
963
964 static inline int mlx4_is_master(struct mlx4_dev *dev)
965 {
966 return dev->flags & MLX4_FLAG_MASTER;
967 }
968
969 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
970 {
971 return dev->phys_caps.base_sqpn + 8 +
972 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
973 }
974
975 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
976 {
977 return (qpn < dev->phys_caps.base_sqpn + 8 +
978 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
979 qpn >= dev->phys_caps.base_sqpn) ||
980 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
981 }
982
983 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
984 {
985 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
986
987 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
988 return 1;
989
990 return 0;
991 }
992
993 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
994 {
995 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
996 }
997
998 static inline int mlx4_is_slave(struct mlx4_dev *dev)
999 {
1000 return dev->flags & MLX4_FLAG_SLAVE;
1001 }
1002
1003 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1004 {
1005 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1006 }
1007
1008 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1009 struct mlx4_buf *buf, gfp_t gfp);
1010 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1011 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1012 {
1013 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
1014 return buf->direct.buf + offset;
1015 else
1016 return buf->page_list[offset >> PAGE_SHIFT].buf +
1017 (offset & (PAGE_SIZE - 1));
1018 }
1019
1020 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1021 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1022 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1023 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1024
1025 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1026 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1027 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1028 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1029
1030 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1031 struct mlx4_mtt *mtt);
1032 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1033 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1034
1035 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1036 int npages, int page_shift, struct mlx4_mr *mr);
1037 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1038 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1039 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1040 struct mlx4_mw *mw);
1041 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1042 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1043 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1044 int start_index, int npages, u64 *page_list);
1045 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1046 struct mlx4_buf *buf, gfp_t gfp);
1047
1048 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1049 gfp_t gfp);
1050 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1051
1052 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1053 int size, int max_direct);
1054 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1055 int size);
1056
1057 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1058 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1059 unsigned vector, int collapsed, int timestamp_en);
1060 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1061 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1062 int *base, u8 flags);
1063 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1064
1065 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1066 gfp_t gfp);
1067 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1068
1069 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1070 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1071 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1072 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1073 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1074
1075 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1076 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1077
1078 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1079 int block_mcast_loopback, enum mlx4_protocol prot);
1080 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1081 enum mlx4_protocol prot);
1082 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1083 u8 port, int block_mcast_loopback,
1084 enum mlx4_protocol protocol, u64 *reg_id);
1085 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1086 enum mlx4_protocol protocol, u64 reg_id);
1087
1088 enum {
1089 MLX4_DOMAIN_UVERBS = 0x1000,
1090 MLX4_DOMAIN_ETHTOOL = 0x2000,
1091 MLX4_DOMAIN_RFS = 0x3000,
1092 MLX4_DOMAIN_NIC = 0x5000,
1093 };
1094
1095 enum mlx4_net_trans_rule_id {
1096 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1097 MLX4_NET_TRANS_RULE_ID_IB,
1098 MLX4_NET_TRANS_RULE_ID_IPV6,
1099 MLX4_NET_TRANS_RULE_ID_IPV4,
1100 MLX4_NET_TRANS_RULE_ID_TCP,
1101 MLX4_NET_TRANS_RULE_ID_UDP,
1102 MLX4_NET_TRANS_RULE_ID_VXLAN,
1103 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1104 };
1105
1106 extern const u16 __sw_id_hw[];
1107
1108 static inline int map_hw_to_sw_id(u16 header_id)
1109 {
1110
1111 int i;
1112 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1113 if (header_id == __sw_id_hw[i])
1114 return i;
1115 }
1116 return -EINVAL;
1117 }
1118
1119 enum mlx4_net_trans_promisc_mode {
1120 MLX4_FS_REGULAR = 1,
1121 MLX4_FS_ALL_DEFAULT,
1122 MLX4_FS_MC_DEFAULT,
1123 MLX4_FS_UC_SNIFFER,
1124 MLX4_FS_MC_SNIFFER,
1125 MLX4_FS_MODE_NUM, /* should be last */
1126 };
1127
1128 struct mlx4_spec_eth {
1129 u8 dst_mac[ETH_ALEN];
1130 u8 dst_mac_msk[ETH_ALEN];
1131 u8 src_mac[ETH_ALEN];
1132 u8 src_mac_msk[ETH_ALEN];
1133 u8 ether_type_enable;
1134 __be16 ether_type;
1135 __be16 vlan_id_msk;
1136 __be16 vlan_id;
1137 };
1138
1139 struct mlx4_spec_tcp_udp {
1140 __be16 dst_port;
1141 __be16 dst_port_msk;
1142 __be16 src_port;
1143 __be16 src_port_msk;
1144 };
1145
1146 struct mlx4_spec_ipv4 {
1147 __be32 dst_ip;
1148 __be32 dst_ip_msk;
1149 __be32 src_ip;
1150 __be32 src_ip_msk;
1151 };
1152
1153 struct mlx4_spec_ib {
1154 __be32 l3_qpn;
1155 __be32 qpn_msk;
1156 u8 dst_gid[16];
1157 u8 dst_gid_msk[16];
1158 };
1159
1160 struct mlx4_spec_vxlan {
1161 __be32 vni;
1162 __be32 vni_mask;
1163
1164 };
1165
1166 struct mlx4_spec_list {
1167 struct list_head list;
1168 enum mlx4_net_trans_rule_id id;
1169 union {
1170 struct mlx4_spec_eth eth;
1171 struct mlx4_spec_ib ib;
1172 struct mlx4_spec_ipv4 ipv4;
1173 struct mlx4_spec_tcp_udp tcp_udp;
1174 struct mlx4_spec_vxlan vxlan;
1175 };
1176 };
1177
1178 enum mlx4_net_trans_hw_rule_queue {
1179 MLX4_NET_TRANS_Q_FIFO,
1180 MLX4_NET_TRANS_Q_LIFO,
1181 };
1182
1183 struct mlx4_net_trans_rule {
1184 struct list_head list;
1185 enum mlx4_net_trans_hw_rule_queue queue_mode;
1186 bool exclusive;
1187 bool allow_loopback;
1188 enum mlx4_net_trans_promisc_mode promisc_mode;
1189 u8 port;
1190 u16 priority;
1191 u32 qpn;
1192 };
1193
1194 struct mlx4_net_trans_rule_hw_ctrl {
1195 __be16 prio;
1196 u8 type;
1197 u8 flags;
1198 u8 rsvd1;
1199 u8 funcid;
1200 u8 vep;
1201 u8 port;
1202 __be32 qpn;
1203 __be32 rsvd2;
1204 };
1205
1206 struct mlx4_net_trans_rule_hw_ib {
1207 u8 size;
1208 u8 rsvd1;
1209 __be16 id;
1210 u32 rsvd2;
1211 __be32 l3_qpn;
1212 __be32 qpn_mask;
1213 u8 dst_gid[16];
1214 u8 dst_gid_msk[16];
1215 } __packed;
1216
1217 struct mlx4_net_trans_rule_hw_eth {
1218 u8 size;
1219 u8 rsvd;
1220 __be16 id;
1221 u8 rsvd1[6];
1222 u8 dst_mac[6];
1223 u16 rsvd2;
1224 u8 dst_mac_msk[6];
1225 u16 rsvd3;
1226 u8 src_mac[6];
1227 u16 rsvd4;
1228 u8 src_mac_msk[6];
1229 u8 rsvd5;
1230 u8 ether_type_enable;
1231 __be16 ether_type;
1232 __be16 vlan_tag_msk;
1233 __be16 vlan_tag;
1234 } __packed;
1235
1236 struct mlx4_net_trans_rule_hw_tcp_udp {
1237 u8 size;
1238 u8 rsvd;
1239 __be16 id;
1240 __be16 rsvd1[3];
1241 __be16 dst_port;
1242 __be16 rsvd2;
1243 __be16 dst_port_msk;
1244 __be16 rsvd3;
1245 __be16 src_port;
1246 __be16 rsvd4;
1247 __be16 src_port_msk;
1248 } __packed;
1249
1250 struct mlx4_net_trans_rule_hw_ipv4 {
1251 u8 size;
1252 u8 rsvd;
1253 __be16 id;
1254 __be32 rsvd1;
1255 __be32 dst_ip;
1256 __be32 dst_ip_msk;
1257 __be32 src_ip;
1258 __be32 src_ip_msk;
1259 } __packed;
1260
1261 struct mlx4_net_trans_rule_hw_vxlan {
1262 u8 size;
1263 u8 rsvd;
1264 __be16 id;
1265 __be32 rsvd1;
1266 __be32 vni;
1267 __be32 vni_mask;
1268 } __packed;
1269
1270 struct _rule_hw {
1271 union {
1272 struct {
1273 u8 size;
1274 u8 rsvd;
1275 __be16 id;
1276 };
1277 struct mlx4_net_trans_rule_hw_eth eth;
1278 struct mlx4_net_trans_rule_hw_ib ib;
1279 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1280 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1281 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1282 };
1283 };
1284
1285 enum {
1286 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1287 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1288 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1289 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1290 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1291 };
1292
1293
1294 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1295 enum mlx4_net_trans_promisc_mode mode);
1296 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1297 enum mlx4_net_trans_promisc_mode mode);
1298 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1299 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1300 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1301 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1302 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1303
1304 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1305 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1306 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1307 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1308 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1309 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1310 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1311 u8 promisc);
1312 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1313 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1314 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1315 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1316 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1317
1318 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1319 int npages, u64 iova, u32 *lkey, u32 *rkey);
1320 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1321 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1322 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1323 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1324 u32 *lkey, u32 *rkey);
1325 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1326 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1327 int mlx4_test_interrupts(struct mlx4_dev *dev);
1328 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1329 int *vector);
1330 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1331
1332 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1333
1334 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1335 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1336 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1337
1338 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1339 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1340
1341 int mlx4_flow_attach(struct mlx4_dev *dev,
1342 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1343 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1344 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1345 enum mlx4_net_trans_promisc_mode flow_type);
1346 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1347 enum mlx4_net_trans_rule_id id);
1348 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1349
1350 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1351 int port, int qpn, u16 prio, u64 *reg_id);
1352
1353 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1354 int i, int val);
1355
1356 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1357
1358 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1359 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1360 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1361 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1362 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1363 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1364 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1365
1366 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1367 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1368
1369 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1370 int *slave_id);
1371 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1372 u8 *gid);
1373
1374 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1375 u32 max_range_qpn);
1376
1377 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1378
1379 struct mlx4_active_ports {
1380 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1381 };
1382 /* Returns a bitmap of the physical ports which are assigned to slave */
1383 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1384
1385 /* Returns the physical port that represents the virtual port of the slave, */
1386 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1387 /* mapping is returned. */
1388 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1389
1390 struct mlx4_slaves_pport {
1391 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1392 };
1393 /* Returns a bitmap of all slaves that are assigned to port. */
1394 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1395 int port);
1396
1397 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1398 /* the ports that are set in crit_ports. */
1399 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1400 struct mlx4_dev *dev,
1401 const struct mlx4_active_ports *crit_ports);
1402
1403 /* Returns the slave's virtual port that represents the physical port. */
1404 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1405
1406 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1407
1408 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1409 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1410 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1411 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1412 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1413 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1414 int enable);
1415 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1416 struct mlx4_mpt_entry ***mpt_entry);
1417 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1418 struct mlx4_mpt_entry **mpt_entry);
1419 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1420 u32 pdn);
1421 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1422 struct mlx4_mpt_entry *mpt_entry,
1423 u32 access);
1424 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1425 struct mlx4_mpt_entry **mpt_entry);
1426 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1427 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1428 u64 iova, u64 size, int npages,
1429 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1430
1431 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1432 u16 offset, u16 size, u8 *data);
1433
1434 /* Returns true if running in low memory profile (kdump kernel) */
1435 static inline bool mlx4_low_memory_profile(void)
1436 {
1437 return is_kdump_kernel();
1438 }
1439
1440 /* ACCESS REG commands */
1441 enum mlx4_access_reg_method {
1442 MLX4_ACCESS_REG_QUERY = 0x1,
1443 MLX4_ACCESS_REG_WRITE = 0x2,
1444 };
1445
1446 /* ACCESS PTYS Reg command */
1447 enum mlx4_ptys_proto {
1448 MLX4_PTYS_IB = 1<<0,
1449 MLX4_PTYS_EN = 1<<2,
1450 };
1451
1452 struct mlx4_ptys_reg {
1453 u8 resrvd1;
1454 u8 local_port;
1455 u8 resrvd2;
1456 u8 proto_mask;
1457 __be32 resrvd3[2];
1458 __be32 eth_proto_cap;
1459 __be16 ib_width_cap;
1460 __be16 ib_speed_cap;
1461 __be32 resrvd4;
1462 __be32 eth_proto_admin;
1463 __be16 ib_width_admin;
1464 __be16 ib_speed_admin;
1465 __be32 resrvd5;
1466 __be32 eth_proto_oper;
1467 __be16 ib_width_oper;
1468 __be16 ib_speed_oper;
1469 __be32 resrvd6;
1470 __be32 eth_proto_lp_adv;
1471 } __packed;
1472
1473 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1474 enum mlx4_access_reg_method method,
1475 struct mlx4_ptys_reg *ptys_reg);
1476
1477 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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