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vxlan: advertise link netns in fdb messages
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
51
52 #define MLX4_NUM_UP 8
53 #define MLX4_NUM_TC 8
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
58 */
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
62
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
65
66 enum {
67 MLX4_FLAG_MSI_X = 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
69 MLX4_FLAG_MASTER = 1 << 2,
70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
73 };
74
75 enum {
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
78 };
79
80 enum {
81 MLX4_MAX_PORTS = 2,
82 MLX4_MAX_PORT_PKEYS = 128
83 };
84
85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
86 * These qkeys must not be allowed for general use. This is a 64k range,
87 * and to test for violation, we use the mask (protect against future chg).
88 */
89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
91
92 enum {
93 MLX4_BOARD_ID_LEN = 64
94 };
95
96 enum {
97 MLX4_MAX_NUM_PF = 16,
98 MLX4_MAX_NUM_VF = 126,
99 MLX4_MAX_NUM_VF_P_PORT = 64,
100 MLX4_MFUNC_MAX = 80,
101 MLX4_MAX_EQ_NUM = 1024,
102 MLX4_MFUNC_EQ_NUM = 4,
103 MLX4_MFUNC_MAX_EQES = 8,
104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
105 };
106
107 /* Driver supports 3 diffrent device methods to manage traffic steering:
108 * -device managed - High level API for ib and eth flow steering. FW is
109 * managing flow steering tables.
110 * - B0 steering mode - Common low level API for ib and (if supported) eth.
111 * - A0 steering mode - Limited low level API for eth. In case of IB,
112 * B0 mode is in use.
113 */
114 enum {
115 MLX4_STEERING_MODE_A0,
116 MLX4_STEERING_MODE_B0,
117 MLX4_STEERING_MODE_DEVICE_MANAGED
118 };
119
120 enum {
121 MLX4_STEERING_DMFS_A0_DEFAULT,
122 MLX4_STEERING_DMFS_A0_DYNAMIC,
123 MLX4_STEERING_DMFS_A0_STATIC,
124 MLX4_STEERING_DMFS_A0_DISABLE,
125 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
126 };
127
128 static inline const char *mlx4_steering_mode_str(int steering_mode)
129 {
130 switch (steering_mode) {
131 case MLX4_STEERING_MODE_A0:
132 return "A0 steering";
133
134 case MLX4_STEERING_MODE_B0:
135 return "B0 steering";
136
137 case MLX4_STEERING_MODE_DEVICE_MANAGED:
138 return "Device managed flow steering";
139
140 default:
141 return "Unrecognize steering mode";
142 }
143 }
144
145 enum {
146 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
147 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
148 };
149
150 enum {
151 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
152 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
153 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
154 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
155 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
156 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
157 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
158 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
159 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
160 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
161 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
162 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
163 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
164 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
165 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
166 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
167 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
168 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
169 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
170 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
171 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
172 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
173 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
174 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
175 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
176 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
177 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
178 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
179 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
180 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
181 };
182
183 enum {
184 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
185 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
186 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
187 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
188 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
190 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
191 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
192 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
193 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
194 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
195 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
196 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
197 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
198 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
199 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
201 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
202 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
203 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19
204 };
205
206 enum {
207 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
208 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
209 };
210
211 enum {
212 MLX4_VF_CAP_FLAG_RESET = 1 << 0
213 };
214
215 /* bit enums for an 8-bit flags field indicating special use
216 * QPs which require special handling in qp_reserve_range.
217 * Currently, this only includes QPs used by the ETH interface,
218 * where we expect to use blueflame. These QPs must not have
219 * bits 6 and 7 set in their qp number.
220 *
221 * This enum may use only bits 0..7.
222 */
223 enum {
224 MLX4_RESERVE_A0_QP = 1 << 6,
225 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
226 };
227
228 enum {
229 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
230 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
231 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
232 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
233 };
234
235 enum {
236 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
237 };
238
239 enum {
240 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
241 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
242 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
243 };
244
245
246 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
247
248 enum {
249 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
250 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
251 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
252 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
253 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
254 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
255 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
256 };
257
258 enum mlx4_event {
259 MLX4_EVENT_TYPE_COMP = 0x00,
260 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
261 MLX4_EVENT_TYPE_COMM_EST = 0x02,
262 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
263 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
264 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
265 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
266 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
267 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
268 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
269 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
270 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
271 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
272 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
273 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
274 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
275 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
276 MLX4_EVENT_TYPE_CMD = 0x0a,
277 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
278 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
279 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
280 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
281 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
282 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
283 MLX4_EVENT_TYPE_NONE = 0xff,
284 };
285
286 enum {
287 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
288 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
289 };
290
291 enum {
292 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
293 };
294
295 enum slave_port_state {
296 SLAVE_PORT_DOWN = 0,
297 SLAVE_PENDING_UP,
298 SLAVE_PORT_UP,
299 };
300
301 enum slave_port_gen_event {
302 SLAVE_PORT_GEN_EVENT_DOWN = 0,
303 SLAVE_PORT_GEN_EVENT_UP,
304 SLAVE_PORT_GEN_EVENT_NONE,
305 };
306
307 enum slave_port_state_event {
308 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
309 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
310 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
311 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
312 };
313
314 enum {
315 MLX4_PERM_LOCAL_READ = 1 << 10,
316 MLX4_PERM_LOCAL_WRITE = 1 << 11,
317 MLX4_PERM_REMOTE_READ = 1 << 12,
318 MLX4_PERM_REMOTE_WRITE = 1 << 13,
319 MLX4_PERM_ATOMIC = 1 << 14,
320 MLX4_PERM_BIND_MW = 1 << 15,
321 MLX4_PERM_MASK = 0xFC00
322 };
323
324 enum {
325 MLX4_OPCODE_NOP = 0x00,
326 MLX4_OPCODE_SEND_INVAL = 0x01,
327 MLX4_OPCODE_RDMA_WRITE = 0x08,
328 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
329 MLX4_OPCODE_SEND = 0x0a,
330 MLX4_OPCODE_SEND_IMM = 0x0b,
331 MLX4_OPCODE_LSO = 0x0e,
332 MLX4_OPCODE_RDMA_READ = 0x10,
333 MLX4_OPCODE_ATOMIC_CS = 0x11,
334 MLX4_OPCODE_ATOMIC_FA = 0x12,
335 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
336 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
337 MLX4_OPCODE_BIND_MW = 0x18,
338 MLX4_OPCODE_FMR = 0x19,
339 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
340 MLX4_OPCODE_CONFIG_CMD = 0x1f,
341
342 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
343 MLX4_RECV_OPCODE_SEND = 0x01,
344 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
345 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
346
347 MLX4_CQE_OPCODE_ERROR = 0x1e,
348 MLX4_CQE_OPCODE_RESIZE = 0x16,
349 };
350
351 enum {
352 MLX4_STAT_RATE_OFFSET = 5
353 };
354
355 enum mlx4_protocol {
356 MLX4_PROT_IB_IPV6 = 0,
357 MLX4_PROT_ETH,
358 MLX4_PROT_IB_IPV4,
359 MLX4_PROT_FCOE
360 };
361
362 enum {
363 MLX4_MTT_FLAG_PRESENT = 1
364 };
365
366 enum mlx4_qp_region {
367 MLX4_QP_REGION_FW = 0,
368 MLX4_QP_REGION_RSS_RAW_ETH,
369 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
370 MLX4_QP_REGION_ETH_ADDR,
371 MLX4_QP_REGION_FC_ADDR,
372 MLX4_QP_REGION_FC_EXCH,
373 MLX4_NUM_QP_REGION
374 };
375
376 enum mlx4_port_type {
377 MLX4_PORT_TYPE_NONE = 0,
378 MLX4_PORT_TYPE_IB = 1,
379 MLX4_PORT_TYPE_ETH = 2,
380 MLX4_PORT_TYPE_AUTO = 3
381 };
382
383 enum mlx4_special_vlan_idx {
384 MLX4_NO_VLAN_IDX = 0,
385 MLX4_VLAN_MISS_IDX,
386 MLX4_VLAN_REGULAR
387 };
388
389 enum mlx4_steer_type {
390 MLX4_MC_STEER = 0,
391 MLX4_UC_STEER,
392 MLX4_NUM_STEERS
393 };
394
395 enum {
396 MLX4_NUM_FEXCH = 64 * 1024,
397 };
398
399 enum {
400 MLX4_MAX_FAST_REG_PAGES = 511,
401 };
402
403 enum {
404 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
405 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
406 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
407 };
408
409 /* Port mgmt change event handling */
410 enum {
411 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
412 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
413 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
414 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
415 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
416 };
417
418 enum {
419 MLX4_DEVICE_STATE_UP = 1 << 0,
420 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
421 };
422
423 enum {
424 MLX4_INTERFACE_STATE_UP = 1 << 0,
425 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
426 };
427
428 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
429 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
430
431 enum mlx4_module_id {
432 MLX4_MODULE_ID_SFP = 0x3,
433 MLX4_MODULE_ID_QSFP = 0xC,
434 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
435 MLX4_MODULE_ID_QSFP28 = 0x11,
436 };
437
438 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
439 {
440 return (major << 32) | (minor << 16) | subminor;
441 }
442
443 struct mlx4_phys_caps {
444 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
445 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
446 u32 num_phys_eqs;
447 u32 base_sqpn;
448 u32 base_proxy_sqpn;
449 u32 base_tunnel_sqpn;
450 };
451
452 struct mlx4_caps {
453 u64 fw_ver;
454 u32 function;
455 int num_ports;
456 int vl_cap[MLX4_MAX_PORTS + 1];
457 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
458 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
459 u64 def_mac[MLX4_MAX_PORTS + 1];
460 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
461 int gid_table_len[MLX4_MAX_PORTS + 1];
462 int pkey_table_len[MLX4_MAX_PORTS + 1];
463 int trans_type[MLX4_MAX_PORTS + 1];
464 int vendor_oui[MLX4_MAX_PORTS + 1];
465 int wavelength[MLX4_MAX_PORTS + 1];
466 u64 trans_code[MLX4_MAX_PORTS + 1];
467 int local_ca_ack_delay;
468 int num_uars;
469 u32 uar_page_size;
470 int bf_reg_size;
471 int bf_regs_per_page;
472 int max_sq_sg;
473 int max_rq_sg;
474 int num_qps;
475 int max_wqes;
476 int max_sq_desc_sz;
477 int max_rq_desc_sz;
478 int max_qp_init_rdma;
479 int max_qp_dest_rdma;
480 u32 *qp0_qkey;
481 u32 *qp0_proxy;
482 u32 *qp1_proxy;
483 u32 *qp0_tunnel;
484 u32 *qp1_tunnel;
485 int num_srqs;
486 int max_srq_wqes;
487 int max_srq_sge;
488 int reserved_srqs;
489 int num_cqs;
490 int max_cqes;
491 int reserved_cqs;
492 int num_sys_eqs;
493 int num_eqs;
494 int reserved_eqs;
495 int num_comp_vectors;
496 int comp_pool;
497 int num_mpts;
498 int max_fmr_maps;
499 int num_mtts;
500 int fmr_reserved_mtts;
501 int reserved_mtts;
502 int reserved_mrws;
503 int reserved_uars;
504 int num_mgms;
505 int num_amgms;
506 int reserved_mcgs;
507 int num_qp_per_mgm;
508 int steering_mode;
509 int dmfs_high_steer_mode;
510 int fs_log_max_ucast_qp_range_size;
511 int num_pds;
512 int reserved_pds;
513 int max_xrcds;
514 int reserved_xrcds;
515 int mtt_entry_sz;
516 u32 max_msg_sz;
517 u32 page_size_cap;
518 u64 flags;
519 u64 flags2;
520 u32 bmme_flags;
521 u32 reserved_lkey;
522 u16 stat_rate_support;
523 u8 port_width_cap[MLX4_MAX_PORTS + 1];
524 int max_gso_sz;
525 int max_rss_tbl_sz;
526 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
527 int reserved_qps;
528 int reserved_qps_base[MLX4_NUM_QP_REGION];
529 int log_num_macs;
530 int log_num_vlans;
531 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
532 u8 supported_type[MLX4_MAX_PORTS + 1];
533 u8 suggested_type[MLX4_MAX_PORTS + 1];
534 u8 default_sense[MLX4_MAX_PORTS + 1];
535 u32 port_mask[MLX4_MAX_PORTS + 1];
536 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
537 u32 max_counters;
538 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
539 u16 sqp_demux;
540 u32 eqe_size;
541 u32 cqe_size;
542 u8 eqe_factor;
543 u32 userspace_caps; /* userspace must be aware of these */
544 u32 function_caps; /* VFs must be aware of these */
545 u16 hca_core_clock;
546 u64 phys_port_id[MLX4_MAX_PORTS + 1];
547 int tunnel_offload_mode;
548 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
549 u8 alloc_res_qp_mask;
550 u32 dmfs_high_rate_qpn_base;
551 u32 dmfs_high_rate_qpn_range;
552 u32 vf_caps;
553 };
554
555 struct mlx4_buf_list {
556 void *buf;
557 dma_addr_t map;
558 };
559
560 struct mlx4_buf {
561 struct mlx4_buf_list direct;
562 struct mlx4_buf_list *page_list;
563 int nbufs;
564 int npages;
565 int page_shift;
566 };
567
568 struct mlx4_mtt {
569 u32 offset;
570 int order;
571 int page_shift;
572 };
573
574 enum {
575 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
576 };
577
578 struct mlx4_db_pgdir {
579 struct list_head list;
580 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
581 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
582 unsigned long *bits[2];
583 __be32 *db_page;
584 dma_addr_t db_dma;
585 };
586
587 struct mlx4_ib_user_db_page;
588
589 struct mlx4_db {
590 __be32 *db;
591 union {
592 struct mlx4_db_pgdir *pgdir;
593 struct mlx4_ib_user_db_page *user_page;
594 } u;
595 dma_addr_t dma;
596 int index;
597 int order;
598 };
599
600 struct mlx4_hwq_resources {
601 struct mlx4_db db;
602 struct mlx4_mtt mtt;
603 struct mlx4_buf buf;
604 };
605
606 struct mlx4_mr {
607 struct mlx4_mtt mtt;
608 u64 iova;
609 u64 size;
610 u32 key;
611 u32 pd;
612 u32 access;
613 int enabled;
614 };
615
616 enum mlx4_mw_type {
617 MLX4_MW_TYPE_1 = 1,
618 MLX4_MW_TYPE_2 = 2,
619 };
620
621 struct mlx4_mw {
622 u32 key;
623 u32 pd;
624 enum mlx4_mw_type type;
625 int enabled;
626 };
627
628 struct mlx4_fmr {
629 struct mlx4_mr mr;
630 struct mlx4_mpt_entry *mpt;
631 __be64 *mtts;
632 dma_addr_t dma_handle;
633 int max_pages;
634 int max_maps;
635 int maps;
636 u8 page_shift;
637 };
638
639 struct mlx4_uar {
640 unsigned long pfn;
641 int index;
642 struct list_head bf_list;
643 unsigned free_bf_bmap;
644 void __iomem *map;
645 void __iomem *bf_map;
646 };
647
648 struct mlx4_bf {
649 unsigned int offset;
650 int buf_size;
651 struct mlx4_uar *uar;
652 void __iomem *reg;
653 };
654
655 struct mlx4_cq {
656 void (*comp) (struct mlx4_cq *);
657 void (*event) (struct mlx4_cq *, enum mlx4_event);
658
659 struct mlx4_uar *uar;
660
661 u32 cons_index;
662
663 u16 irq;
664 __be32 *set_ci_db;
665 __be32 *arm_db;
666 int arm_sn;
667
668 int cqn;
669 unsigned vector;
670
671 atomic_t refcount;
672 struct completion free;
673 struct {
674 struct list_head list;
675 void (*comp)(struct mlx4_cq *);
676 void *priv;
677 } tasklet_ctx;
678 };
679
680 struct mlx4_qp {
681 void (*event) (struct mlx4_qp *, enum mlx4_event);
682
683 int qpn;
684
685 atomic_t refcount;
686 struct completion free;
687 };
688
689 struct mlx4_srq {
690 void (*event) (struct mlx4_srq *, enum mlx4_event);
691
692 int srqn;
693 int max;
694 int max_gs;
695 int wqe_shift;
696
697 atomic_t refcount;
698 struct completion free;
699 };
700
701 struct mlx4_av {
702 __be32 port_pd;
703 u8 reserved1;
704 u8 g_slid;
705 __be16 dlid;
706 u8 reserved2;
707 u8 gid_index;
708 u8 stat_rate;
709 u8 hop_limit;
710 __be32 sl_tclass_flowlabel;
711 u8 dgid[16];
712 };
713
714 struct mlx4_eth_av {
715 __be32 port_pd;
716 u8 reserved1;
717 u8 smac_idx;
718 u16 reserved2;
719 u8 reserved3;
720 u8 gid_index;
721 u8 stat_rate;
722 u8 hop_limit;
723 __be32 sl_tclass_flowlabel;
724 u8 dgid[16];
725 u8 s_mac[6];
726 u8 reserved4[2];
727 __be16 vlan;
728 u8 mac[ETH_ALEN];
729 };
730
731 union mlx4_ext_av {
732 struct mlx4_av ib;
733 struct mlx4_eth_av eth;
734 };
735
736 struct mlx4_counter {
737 u8 reserved1[3];
738 u8 counter_mode;
739 __be32 num_ifc;
740 u32 reserved2[2];
741 __be64 rx_frames;
742 __be64 rx_bytes;
743 __be64 tx_frames;
744 __be64 tx_bytes;
745 };
746
747 struct mlx4_quotas {
748 int qp;
749 int cq;
750 int srq;
751 int mpt;
752 int mtt;
753 int counter;
754 int xrcd;
755 };
756
757 struct mlx4_vf_dev {
758 u8 min_port;
759 u8 n_ports;
760 };
761
762 struct mlx4_dev_persistent {
763 struct pci_dev *pdev;
764 struct mlx4_dev *dev;
765 int nvfs[MLX4_MAX_PORTS + 1];
766 int num_vfs;
767 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
768 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
769 struct work_struct catas_work;
770 struct workqueue_struct *catas_wq;
771 struct mutex device_state_mutex; /* protect HW state */
772 u8 state;
773 struct mutex interface_state_mutex; /* protect SW state */
774 u8 interface_state;
775 };
776
777 struct mlx4_dev {
778 struct mlx4_dev_persistent *persist;
779 unsigned long flags;
780 unsigned long num_slaves;
781 struct mlx4_caps caps;
782 struct mlx4_phys_caps phys_caps;
783 struct mlx4_quotas quotas;
784 struct radix_tree_root qp_table_tree;
785 u8 rev_id;
786 char board_id[MLX4_BOARD_ID_LEN];
787 int numa_node;
788 int oper_log_mgm_entry_size;
789 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
790 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
791 struct mlx4_vf_dev *dev_vfs;
792 };
793
794 struct mlx4_eqe {
795 u8 reserved1;
796 u8 type;
797 u8 reserved2;
798 u8 subtype;
799 union {
800 u32 raw[6];
801 struct {
802 __be32 cqn;
803 } __packed comp;
804 struct {
805 u16 reserved1;
806 __be16 token;
807 u32 reserved2;
808 u8 reserved3[3];
809 u8 status;
810 __be64 out_param;
811 } __packed cmd;
812 struct {
813 __be32 qpn;
814 } __packed qp;
815 struct {
816 __be32 srqn;
817 } __packed srq;
818 struct {
819 __be32 cqn;
820 u32 reserved1;
821 u8 reserved2[3];
822 u8 syndrome;
823 } __packed cq_err;
824 struct {
825 u32 reserved1[2];
826 __be32 port;
827 } __packed port_change;
828 struct {
829 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
830 u32 reserved;
831 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
832 } __packed comm_channel_arm;
833 struct {
834 u8 port;
835 u8 reserved[3];
836 __be64 mac;
837 } __packed mac_update;
838 struct {
839 __be32 slave_id;
840 } __packed flr_event;
841 struct {
842 __be16 current_temperature;
843 __be16 warning_threshold;
844 } __packed warming;
845 struct {
846 u8 reserved[3];
847 u8 port;
848 union {
849 struct {
850 __be16 mstr_sm_lid;
851 __be16 port_lid;
852 __be32 changed_attr;
853 u8 reserved[3];
854 u8 mstr_sm_sl;
855 __be64 gid_prefix;
856 } __packed port_info;
857 struct {
858 __be32 block_ptr;
859 __be32 tbl_entries_mask;
860 } __packed tbl_change_info;
861 } params;
862 } __packed port_mgmt_change;
863 } event;
864 u8 slave_id;
865 u8 reserved3[2];
866 u8 owner;
867 } __packed;
868
869 struct mlx4_init_port_param {
870 int set_guid0;
871 int set_node_guid;
872 int set_si_guid;
873 u16 mtu;
874 int port_width_cap;
875 u16 vl_cap;
876 u16 max_gid;
877 u16 max_pkey;
878 u64 guid0;
879 u64 node_guid;
880 u64 si_guid;
881 };
882
883 #define MAD_IFC_DATA_SZ 192
884 /* MAD IFC Mailbox */
885 struct mlx4_mad_ifc {
886 u8 base_version;
887 u8 mgmt_class;
888 u8 class_version;
889 u8 method;
890 __be16 status;
891 __be16 class_specific;
892 __be64 tid;
893 __be16 attr_id;
894 __be16 resv;
895 __be32 attr_mod;
896 __be64 mkey;
897 __be16 dr_slid;
898 __be16 dr_dlid;
899 u8 reserved[28];
900 u8 data[MAD_IFC_DATA_SZ];
901 } __packed;
902
903 #define mlx4_foreach_port(port, dev, type) \
904 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
905 if ((type) == (dev)->caps.port_mask[(port)])
906
907 #define mlx4_foreach_non_ib_transport_port(port, dev) \
908 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
909 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
910
911 #define mlx4_foreach_ib_transport_port(port, dev) \
912 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
913 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
914 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
915
916 #define MLX4_INVALID_SLAVE_ID 0xFF
917
918 void handle_port_mgmt_change_event(struct work_struct *work);
919
920 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
921 {
922 return dev->caps.function;
923 }
924
925 static inline int mlx4_is_master(struct mlx4_dev *dev)
926 {
927 return dev->flags & MLX4_FLAG_MASTER;
928 }
929
930 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
931 {
932 return dev->phys_caps.base_sqpn + 8 +
933 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
934 }
935
936 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
937 {
938 return (qpn < dev->phys_caps.base_sqpn + 8 +
939 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
940 qpn >= dev->phys_caps.base_sqpn) ||
941 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
942 }
943
944 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
945 {
946 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
947
948 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
949 return 1;
950
951 return 0;
952 }
953
954 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
955 {
956 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
957 }
958
959 static inline int mlx4_is_slave(struct mlx4_dev *dev)
960 {
961 return dev->flags & MLX4_FLAG_SLAVE;
962 }
963
964 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
965 struct mlx4_buf *buf, gfp_t gfp);
966 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
967 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
968 {
969 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
970 return buf->direct.buf + offset;
971 else
972 return buf->page_list[offset >> PAGE_SHIFT].buf +
973 (offset & (PAGE_SIZE - 1));
974 }
975
976 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
977 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
978 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
979 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
980
981 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
982 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
983 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
984 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
985
986 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
987 struct mlx4_mtt *mtt);
988 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
989 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
990
991 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
992 int npages, int page_shift, struct mlx4_mr *mr);
993 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
994 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
995 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
996 struct mlx4_mw *mw);
997 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
998 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
999 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1000 int start_index, int npages, u64 *page_list);
1001 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1002 struct mlx4_buf *buf, gfp_t gfp);
1003
1004 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1005 gfp_t gfp);
1006 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1007
1008 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1009 int size, int max_direct);
1010 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1011 int size);
1012
1013 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1014 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1015 unsigned vector, int collapsed, int timestamp_en);
1016 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1017 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1018 int *base, u8 flags);
1019 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1020
1021 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1022 gfp_t gfp);
1023 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1024
1025 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1026 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1027 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1028 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1029 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1030
1031 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1032 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1033
1034 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1035 int block_mcast_loopback, enum mlx4_protocol prot);
1036 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1037 enum mlx4_protocol prot);
1038 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1039 u8 port, int block_mcast_loopback,
1040 enum mlx4_protocol protocol, u64 *reg_id);
1041 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1042 enum mlx4_protocol protocol, u64 reg_id);
1043
1044 enum {
1045 MLX4_DOMAIN_UVERBS = 0x1000,
1046 MLX4_DOMAIN_ETHTOOL = 0x2000,
1047 MLX4_DOMAIN_RFS = 0x3000,
1048 MLX4_DOMAIN_NIC = 0x5000,
1049 };
1050
1051 enum mlx4_net_trans_rule_id {
1052 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1053 MLX4_NET_TRANS_RULE_ID_IB,
1054 MLX4_NET_TRANS_RULE_ID_IPV6,
1055 MLX4_NET_TRANS_RULE_ID_IPV4,
1056 MLX4_NET_TRANS_RULE_ID_TCP,
1057 MLX4_NET_TRANS_RULE_ID_UDP,
1058 MLX4_NET_TRANS_RULE_ID_VXLAN,
1059 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1060 };
1061
1062 extern const u16 __sw_id_hw[];
1063
1064 static inline int map_hw_to_sw_id(u16 header_id)
1065 {
1066
1067 int i;
1068 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1069 if (header_id == __sw_id_hw[i])
1070 return i;
1071 }
1072 return -EINVAL;
1073 }
1074
1075 enum mlx4_net_trans_promisc_mode {
1076 MLX4_FS_REGULAR = 1,
1077 MLX4_FS_ALL_DEFAULT,
1078 MLX4_FS_MC_DEFAULT,
1079 MLX4_FS_UC_SNIFFER,
1080 MLX4_FS_MC_SNIFFER,
1081 MLX4_FS_MODE_NUM, /* should be last */
1082 };
1083
1084 struct mlx4_spec_eth {
1085 u8 dst_mac[ETH_ALEN];
1086 u8 dst_mac_msk[ETH_ALEN];
1087 u8 src_mac[ETH_ALEN];
1088 u8 src_mac_msk[ETH_ALEN];
1089 u8 ether_type_enable;
1090 __be16 ether_type;
1091 __be16 vlan_id_msk;
1092 __be16 vlan_id;
1093 };
1094
1095 struct mlx4_spec_tcp_udp {
1096 __be16 dst_port;
1097 __be16 dst_port_msk;
1098 __be16 src_port;
1099 __be16 src_port_msk;
1100 };
1101
1102 struct mlx4_spec_ipv4 {
1103 __be32 dst_ip;
1104 __be32 dst_ip_msk;
1105 __be32 src_ip;
1106 __be32 src_ip_msk;
1107 };
1108
1109 struct mlx4_spec_ib {
1110 __be32 l3_qpn;
1111 __be32 qpn_msk;
1112 u8 dst_gid[16];
1113 u8 dst_gid_msk[16];
1114 };
1115
1116 struct mlx4_spec_vxlan {
1117 __be32 vni;
1118 __be32 vni_mask;
1119
1120 };
1121
1122 struct mlx4_spec_list {
1123 struct list_head list;
1124 enum mlx4_net_trans_rule_id id;
1125 union {
1126 struct mlx4_spec_eth eth;
1127 struct mlx4_spec_ib ib;
1128 struct mlx4_spec_ipv4 ipv4;
1129 struct mlx4_spec_tcp_udp tcp_udp;
1130 struct mlx4_spec_vxlan vxlan;
1131 };
1132 };
1133
1134 enum mlx4_net_trans_hw_rule_queue {
1135 MLX4_NET_TRANS_Q_FIFO,
1136 MLX4_NET_TRANS_Q_LIFO,
1137 };
1138
1139 struct mlx4_net_trans_rule {
1140 struct list_head list;
1141 enum mlx4_net_trans_hw_rule_queue queue_mode;
1142 bool exclusive;
1143 bool allow_loopback;
1144 enum mlx4_net_trans_promisc_mode promisc_mode;
1145 u8 port;
1146 u16 priority;
1147 u32 qpn;
1148 };
1149
1150 struct mlx4_net_trans_rule_hw_ctrl {
1151 __be16 prio;
1152 u8 type;
1153 u8 flags;
1154 u8 rsvd1;
1155 u8 funcid;
1156 u8 vep;
1157 u8 port;
1158 __be32 qpn;
1159 __be32 rsvd2;
1160 };
1161
1162 struct mlx4_net_trans_rule_hw_ib {
1163 u8 size;
1164 u8 rsvd1;
1165 __be16 id;
1166 u32 rsvd2;
1167 __be32 l3_qpn;
1168 __be32 qpn_mask;
1169 u8 dst_gid[16];
1170 u8 dst_gid_msk[16];
1171 } __packed;
1172
1173 struct mlx4_net_trans_rule_hw_eth {
1174 u8 size;
1175 u8 rsvd;
1176 __be16 id;
1177 u8 rsvd1[6];
1178 u8 dst_mac[6];
1179 u16 rsvd2;
1180 u8 dst_mac_msk[6];
1181 u16 rsvd3;
1182 u8 src_mac[6];
1183 u16 rsvd4;
1184 u8 src_mac_msk[6];
1185 u8 rsvd5;
1186 u8 ether_type_enable;
1187 __be16 ether_type;
1188 __be16 vlan_tag_msk;
1189 __be16 vlan_tag;
1190 } __packed;
1191
1192 struct mlx4_net_trans_rule_hw_tcp_udp {
1193 u8 size;
1194 u8 rsvd;
1195 __be16 id;
1196 __be16 rsvd1[3];
1197 __be16 dst_port;
1198 __be16 rsvd2;
1199 __be16 dst_port_msk;
1200 __be16 rsvd3;
1201 __be16 src_port;
1202 __be16 rsvd4;
1203 __be16 src_port_msk;
1204 } __packed;
1205
1206 struct mlx4_net_trans_rule_hw_ipv4 {
1207 u8 size;
1208 u8 rsvd;
1209 __be16 id;
1210 __be32 rsvd1;
1211 __be32 dst_ip;
1212 __be32 dst_ip_msk;
1213 __be32 src_ip;
1214 __be32 src_ip_msk;
1215 } __packed;
1216
1217 struct mlx4_net_trans_rule_hw_vxlan {
1218 u8 size;
1219 u8 rsvd;
1220 __be16 id;
1221 __be32 rsvd1;
1222 __be32 vni;
1223 __be32 vni_mask;
1224 } __packed;
1225
1226 struct _rule_hw {
1227 union {
1228 struct {
1229 u8 size;
1230 u8 rsvd;
1231 __be16 id;
1232 };
1233 struct mlx4_net_trans_rule_hw_eth eth;
1234 struct mlx4_net_trans_rule_hw_ib ib;
1235 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1236 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1237 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1238 };
1239 };
1240
1241 enum {
1242 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1243 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1244 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1245 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1246 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1247 };
1248
1249
1250 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1251 enum mlx4_net_trans_promisc_mode mode);
1252 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1253 enum mlx4_net_trans_promisc_mode mode);
1254 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1255 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1256 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1257 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1258 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1259
1260 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1261 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1262 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1263 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1264 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1265 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1266 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1267 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1268 u8 promisc);
1269 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1270 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1271 u8 *pg, u16 *ratelimit);
1272 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1273 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1274 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1275 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1276 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1277
1278 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1279 int npages, u64 iova, u32 *lkey, u32 *rkey);
1280 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1281 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1282 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1283 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1284 u32 *lkey, u32 *rkey);
1285 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1286 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1287 int mlx4_test_interrupts(struct mlx4_dev *dev);
1288 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1289 int *vector);
1290 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1291
1292 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1293
1294 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1295 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1296 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1297
1298 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1299 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1300
1301 int mlx4_flow_attach(struct mlx4_dev *dev,
1302 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1303 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1304 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1305 enum mlx4_net_trans_promisc_mode flow_type);
1306 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1307 enum mlx4_net_trans_rule_id id);
1308 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1309
1310 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1311 int port, int qpn, u16 prio, u64 *reg_id);
1312
1313 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1314 int i, int val);
1315
1316 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1317
1318 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1319 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1320 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1321 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1322 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1323 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1324 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1325
1326 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1327 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1328
1329 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1330 int *slave_id);
1331 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1332 u8 *gid);
1333
1334 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1335 u32 max_range_qpn);
1336
1337 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1338
1339 struct mlx4_active_ports {
1340 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1341 };
1342 /* Returns a bitmap of the physical ports which are assigned to slave */
1343 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1344
1345 /* Returns the physical port that represents the virtual port of the slave, */
1346 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1347 /* mapping is returned. */
1348 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1349
1350 struct mlx4_slaves_pport {
1351 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1352 };
1353 /* Returns a bitmap of all slaves that are assigned to port. */
1354 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1355 int port);
1356
1357 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1358 /* the ports that are set in crit_ports. */
1359 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1360 struct mlx4_dev *dev,
1361 const struct mlx4_active_ports *crit_ports);
1362
1363 /* Returns the slave's virtual port that represents the physical port. */
1364 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1365
1366 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1367
1368 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1369 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1370 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1371 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1372 int enable);
1373 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1374 struct mlx4_mpt_entry ***mpt_entry);
1375 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1376 struct mlx4_mpt_entry **mpt_entry);
1377 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1378 u32 pdn);
1379 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1380 struct mlx4_mpt_entry *mpt_entry,
1381 u32 access);
1382 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1383 struct mlx4_mpt_entry **mpt_entry);
1384 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1385 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1386 u64 iova, u64 size, int npages,
1387 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1388
1389 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1390 u16 offset, u16 size, u8 *data);
1391
1392 /* Returns true if running in low memory profile (kdump kernel) */
1393 static inline bool mlx4_low_memory_profile(void)
1394 {
1395 return is_kdump_kernel();
1396 }
1397
1398 /* ACCESS REG commands */
1399 enum mlx4_access_reg_method {
1400 MLX4_ACCESS_REG_QUERY = 0x1,
1401 MLX4_ACCESS_REG_WRITE = 0x2,
1402 };
1403
1404 /* ACCESS PTYS Reg command */
1405 enum mlx4_ptys_proto {
1406 MLX4_PTYS_IB = 1<<0,
1407 MLX4_PTYS_EN = 1<<2,
1408 };
1409
1410 struct mlx4_ptys_reg {
1411 u8 resrvd1;
1412 u8 local_port;
1413 u8 resrvd2;
1414 u8 proto_mask;
1415 __be32 resrvd3[2];
1416 __be32 eth_proto_cap;
1417 __be16 ib_width_cap;
1418 __be16 ib_speed_cap;
1419 __be32 resrvd4;
1420 __be32 eth_proto_admin;
1421 __be16 ib_width_admin;
1422 __be16 ib_speed_admin;
1423 __be32 resrvd5;
1424 __be32 eth_proto_oper;
1425 __be16 ib_width_oper;
1426 __be16 ib_speed_oper;
1427 __be32 resrvd6;
1428 __be32 eth_proto_lp_adv;
1429 } __packed;
1430
1431 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1432 enum mlx4_access_reg_method method,
1433 struct mlx4_ptys_reg *ptys_reg);
1434
1435 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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