2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <asm/atomic.h>
43 MLX4_FLAG_MSI_X
= 1 << 0,
51 MLX4_DEV_CAP_FLAG_RC
= 1 << 0,
52 MLX4_DEV_CAP_FLAG_UC
= 1 << 1,
53 MLX4_DEV_CAP_FLAG_UD
= 1 << 2,
54 MLX4_DEV_CAP_FLAG_SRQ
= 1 << 6,
55 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1 << 7,
56 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1 << 8,
57 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1 << 9,
58 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1 << 16,
59 MLX4_DEV_CAP_FLAG_APM
= 1 << 17,
60 MLX4_DEV_CAP_FLAG_ATOMIC
= 1 << 18,
61 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1 << 19,
62 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1 << 20,
63 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1 << 21
67 MLX4_EVENT_TYPE_COMP
= 0x00,
68 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
69 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
70 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
71 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
72 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
73 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
74 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
75 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
76 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
77 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
78 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
79 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
80 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
81 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
82 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
83 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
84 MLX4_EVENT_TYPE_CMD
= 0x0a
88 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
89 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
93 MLX4_PERM_LOCAL_READ
= 1 << 10,
94 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
95 MLX4_PERM_REMOTE_READ
= 1 << 12,
96 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
97 MLX4_PERM_ATOMIC
= 1 << 14
101 MLX4_OPCODE_NOP
= 0x00,
102 MLX4_OPCODE_SEND_INVAL
= 0x01,
103 MLX4_OPCODE_RDMA_WRITE
= 0x08,
104 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
105 MLX4_OPCODE_SEND
= 0x0a,
106 MLX4_OPCODE_SEND_IMM
= 0x0b,
107 MLX4_OPCODE_LSO
= 0x0e,
108 MLX4_OPCODE_RDMA_READ
= 0x10,
109 MLX4_OPCODE_ATOMIC_CS
= 0x11,
110 MLX4_OPCODE_ATOMIC_FA
= 0x12,
111 MLX4_OPCODE_ATOMIC_MASK_CS
= 0x14,
112 MLX4_OPCODE_ATOMIC_MASK_FA
= 0x15,
113 MLX4_OPCODE_BIND_MW
= 0x18,
114 MLX4_OPCODE_FMR
= 0x19,
115 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
116 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
118 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
119 MLX4_RECV_OPCODE_SEND
= 0x01,
120 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
121 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
123 MLX4_CQE_OPCODE_ERROR
= 0x1e,
124 MLX4_CQE_OPCODE_RESIZE
= 0x16,
128 MLX4_STAT_RATE_OFFSET
= 5
138 int local_ca_ack_delay
;
141 int bf_regs_per_page
;
148 int max_qp_init_rdma
;
149 int max_qp_dest_rdma
;
163 int fmr_reserved_mtts
;
176 u16 stat_rate_support
;
180 struct mlx4_buf_list
{
187 struct mlx4_buf_list direct
;
188 struct mlx4_buf_list
*page_list
;
217 void (*comp
) (struct mlx4_cq
*);
218 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
220 struct mlx4_uar
*uar
;
231 struct completion free
;
235 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
240 struct completion free
;
244 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
252 struct completion free
;
264 __be32 sl_tclass_flowlabel
;
269 struct pci_dev
*pdev
;
271 struct mlx4_caps caps
;
272 struct radix_tree_root qp_table_tree
;
275 struct mlx4_init_port_param
{
289 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
290 struct mlx4_buf
*buf
);
291 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
293 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
294 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
296 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
297 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
299 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
300 struct mlx4_mtt
*mtt
);
301 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
302 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
304 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
305 int npages
, int page_shift
, struct mlx4_mr
*mr
);
306 void mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
307 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
308 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
309 int start_index
, int npages
, u64
*page_list
);
310 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
311 struct mlx4_buf
*buf
);
313 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
314 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
);
315 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
317 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int sqpn
, struct mlx4_qp
*qp
);
318 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
320 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, struct mlx4_mtt
*mtt
,
321 u64 db_rec
, struct mlx4_srq
*srq
);
322 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
323 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
325 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, struct mlx4_init_port_param
*param
, int port
);
326 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
328 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16]);
329 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16]);
331 #endif /* MLX4_DEVICE_H */