2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <linux/atomic.h>
42 #define MAX_MSIX_P_PORT 17
44 #define MSIX_LEGACY_SZ 4
45 #define MIN_MSIX_P_PORT 5
48 MLX4_FLAG_MSI_X
= 1 << 0,
49 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
50 MLX4_FLAG_MASTER
= 1 << 2,
51 MLX4_FLAG_SLAVE
= 1 << 3,
52 MLX4_FLAG_SRIOV
= 1 << 4,
60 MLX4_BOARD_ID_LEN
= 64
67 MLX4_MFUNC_EQ_NUM
= 4,
68 MLX4_MFUNC_MAX_EQES
= 8,
69 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
73 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
74 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
75 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
76 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
77 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
78 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
79 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
80 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
81 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
82 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
83 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
84 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
85 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
86 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
87 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
88 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
89 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
90 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
91 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
92 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
93 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
94 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
95 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
96 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
97 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
98 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55
102 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
103 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
104 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2
107 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
110 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
111 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
112 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
113 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
114 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
118 MLX4_EVENT_TYPE_COMP
= 0x00,
119 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
120 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
121 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
122 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
123 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
124 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
125 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
126 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
127 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
128 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
129 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
130 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
131 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
132 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
133 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
134 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
135 MLX4_EVENT_TYPE_CMD
= 0x0a,
136 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
137 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
138 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
139 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
140 MLX4_EVENT_TYPE_NONE
= 0xff,
144 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
145 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
149 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
153 MLX4_PERM_LOCAL_READ
= 1 << 10,
154 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
155 MLX4_PERM_REMOTE_READ
= 1 << 12,
156 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
157 MLX4_PERM_ATOMIC
= 1 << 14
161 MLX4_OPCODE_NOP
= 0x00,
162 MLX4_OPCODE_SEND_INVAL
= 0x01,
163 MLX4_OPCODE_RDMA_WRITE
= 0x08,
164 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
165 MLX4_OPCODE_SEND
= 0x0a,
166 MLX4_OPCODE_SEND_IMM
= 0x0b,
167 MLX4_OPCODE_LSO
= 0x0e,
168 MLX4_OPCODE_RDMA_READ
= 0x10,
169 MLX4_OPCODE_ATOMIC_CS
= 0x11,
170 MLX4_OPCODE_ATOMIC_FA
= 0x12,
171 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
172 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
173 MLX4_OPCODE_BIND_MW
= 0x18,
174 MLX4_OPCODE_FMR
= 0x19,
175 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
176 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
178 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
179 MLX4_RECV_OPCODE_SEND
= 0x01,
180 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
181 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
183 MLX4_CQE_OPCODE_ERROR
= 0x1e,
184 MLX4_CQE_OPCODE_RESIZE
= 0x16,
188 MLX4_STAT_RATE_OFFSET
= 5
192 MLX4_PROT_IB_IPV6
= 0,
199 MLX4_MTT_FLAG_PRESENT
= 1
202 enum mlx4_qp_region
{
203 MLX4_QP_REGION_FW
= 0,
204 MLX4_QP_REGION_ETH_ADDR
,
205 MLX4_QP_REGION_FC_ADDR
,
206 MLX4_QP_REGION_FC_EXCH
,
210 enum mlx4_port_type
{
211 MLX4_PORT_TYPE_NONE
= 0,
212 MLX4_PORT_TYPE_IB
= 1,
213 MLX4_PORT_TYPE_ETH
= 2,
214 MLX4_PORT_TYPE_AUTO
= 3
217 enum mlx4_special_vlan_idx
{
218 MLX4_NO_VLAN_IDX
= 0,
223 enum mlx4_steer_type
{
230 MLX4_NUM_FEXCH
= 64 * 1024,
234 MLX4_MAX_FAST_REG_PAGES
= 511,
237 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
239 return (major
<< 32) | (minor
<< 16) | subminor
;
246 int vl_cap
[MLX4_MAX_PORTS
+ 1];
247 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
248 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
249 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
250 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
251 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
252 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
253 int trans_type
[MLX4_MAX_PORTS
+ 1];
254 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
255 int wavelength
[MLX4_MAX_PORTS
+ 1];
256 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
257 int local_ca_ack_delay
;
261 int bf_regs_per_page
;
268 int max_qp_init_rdma
;
269 int max_qp_dest_rdma
;
280 int num_comp_vectors
;
285 int fmr_reserved_mtts
;
304 u16 stat_rate_support
;
305 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
308 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
310 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
314 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
315 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
316 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
317 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
318 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
319 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
321 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
324 struct mlx4_buf_list
{
330 struct mlx4_buf_list direct
;
331 struct mlx4_buf_list
*page_list
;
344 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
347 struct mlx4_db_pgdir
{
348 struct list_head list
;
349 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
350 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
351 unsigned long *bits
[2];
356 struct mlx4_ib_user_db_page
;
361 struct mlx4_db_pgdir
*pgdir
;
362 struct mlx4_ib_user_db_page
*user_page
;
369 struct mlx4_hwq_resources
{
387 struct mlx4_mpt_entry
*mpt
;
389 dma_addr_t dma_handle
;
399 struct list_head bf_list
;
400 unsigned free_bf_bmap
;
402 void __iomem
*bf_map
;
406 unsigned long offset
;
408 struct mlx4_uar
*uar
;
413 void (*comp
) (struct mlx4_cq
*);
414 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
416 struct mlx4_uar
*uar
;
428 struct completion free
;
432 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
437 struct completion free
;
441 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
449 struct completion free
;
461 __be32 sl_tclass_flowlabel
;
474 __be32 sl_tclass_flowlabel
;
483 struct mlx4_eth_av eth
;
486 struct mlx4_counter
{
498 struct pci_dev
*pdev
;
500 unsigned long num_slaves
;
501 struct mlx4_caps caps
;
502 struct radix_tree_root qp_table_tree
;
504 char board_id
[MLX4_BOARD_ID_LEN
];
508 struct mlx4_init_port_param
{
522 #define mlx4_foreach_port(port, dev, type) \
523 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
524 if ((type) == (dev)->caps.port_mask[(port)])
526 #define mlx4_foreach_ib_transport_port(port, dev) \
527 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
528 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
529 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
531 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
533 return dev
->flags
& MLX4_FLAG_MASTER
;
536 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
538 return (qpn
< dev
->caps
.sqp_start
+ 8);
541 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
543 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
546 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
548 return dev
->flags
& MLX4_FLAG_SLAVE
;
551 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
552 struct mlx4_buf
*buf
);
553 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
554 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
556 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
557 return buf
->direct
.buf
+ offset
;
559 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
560 (offset
& (PAGE_SIZE
- 1));
563 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
564 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
565 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
566 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
568 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
569 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
570 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
571 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
573 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
574 struct mlx4_mtt
*mtt
);
575 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
576 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
578 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
579 int npages
, int page_shift
, struct mlx4_mr
*mr
);
580 void mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
581 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
582 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
583 int start_index
, int npages
, u64
*page_list
);
584 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
585 struct mlx4_buf
*buf
);
587 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
);
588 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
590 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
591 int size
, int max_direct
);
592 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
595 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
596 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
597 unsigned vector
, int collapsed
);
598 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
600 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
601 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
603 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
);
604 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
606 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
607 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
608 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
609 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
610 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
612 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
613 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
615 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
616 int block_mcast_loopback
, enum mlx4_protocol prot
);
617 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
618 enum mlx4_protocol prot
);
619 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
620 int block_mcast_loopback
, enum mlx4_protocol protocol
);
621 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
622 enum mlx4_protocol protocol
);
623 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
624 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
625 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
626 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
627 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
629 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
630 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
631 int mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
632 int mlx4_get_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *qpn
);
633 void mlx4_put_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int qpn
);
634 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
);
635 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
636 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
637 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
639 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
);
640 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
641 u8
*pg
, u16
*ratelimit
);
642 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
643 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
644 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, int index
);
646 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
647 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
648 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
649 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
650 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
651 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
652 u32
*lkey
, u32
*rkey
);
653 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
654 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
655 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
656 int mlx4_assign_eq(struct mlx4_dev
*dev
, char* name
, int* vector
);
657 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
659 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
660 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
662 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
663 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
665 #endif /* MLX4_DEVICE_H */