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Merge branch 'for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define DEFAULT_UAR_PAGE_SHIFT 12
48
49 #define MAX_MSIX_P_PORT 17
50 #define MAX_MSIX 64
51 #define MIN_MSIX_P_PORT 5
52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)
54
55 #define MLX4_MAX_100M_UNITS_VAL 255 /*
56 * work around: can't set values
57 * greater then this value when
58 * using 100 Mbps units.
59 */
60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
62 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63
64 #define MLX4_ROCE_MAX_GIDS 128
65 #define MLX4_ROCE_PF_GIDS 16
66
67 enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
74 MLX4_FLAG_BONDED = 1 << 7
75 };
76
77 enum {
78 MLX4_PORT_CAP_IS_SM = 1 << 1,
79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
80 };
81
82 enum {
83 MLX4_MAX_PORTS = 2,
84 MLX4_MAX_PORT_PKEYS = 128,
85 MLX4_MAX_PORT_GIDS = 128
86 };
87
88 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
89 * These qkeys must not be allowed for general use. This is a 64k range,
90 * and to test for violation, we use the mask (protect against future chg).
91 */
92 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
93 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
94
95 enum {
96 MLX4_BOARD_ID_LEN = 64
97 };
98
99 enum {
100 MLX4_MAX_NUM_PF = 16,
101 MLX4_MAX_NUM_VF = 126,
102 MLX4_MAX_NUM_VF_P_PORT = 64,
103 MLX4_MFUNC_MAX = 128,
104 MLX4_MAX_EQ_NUM = 1024,
105 MLX4_MFUNC_EQ_NUM = 4,
106 MLX4_MFUNC_MAX_EQES = 8,
107 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
108 };
109
110 /* Driver supports 3 diffrent device methods to manage traffic steering:
111 * -device managed - High level API for ib and eth flow steering. FW is
112 * managing flow steering tables.
113 * - B0 steering mode - Common low level API for ib and (if supported) eth.
114 * - A0 steering mode - Limited low level API for eth. In case of IB,
115 * B0 mode is in use.
116 */
117 enum {
118 MLX4_STEERING_MODE_A0,
119 MLX4_STEERING_MODE_B0,
120 MLX4_STEERING_MODE_DEVICE_MANAGED
121 };
122
123 enum {
124 MLX4_STEERING_DMFS_A0_DEFAULT,
125 MLX4_STEERING_DMFS_A0_DYNAMIC,
126 MLX4_STEERING_DMFS_A0_STATIC,
127 MLX4_STEERING_DMFS_A0_DISABLE,
128 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
129 };
130
131 static inline const char *mlx4_steering_mode_str(int steering_mode)
132 {
133 switch (steering_mode) {
134 case MLX4_STEERING_MODE_A0:
135 return "A0 steering";
136
137 case MLX4_STEERING_MODE_B0:
138 return "B0 steering";
139
140 case MLX4_STEERING_MODE_DEVICE_MANAGED:
141 return "Device managed flow steering";
142
143 default:
144 return "Unrecognize steering mode";
145 }
146 }
147
148 enum {
149 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
150 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
151 };
152
153 enum {
154 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
155 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
156 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
157 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
158 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
159 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
160 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
161 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
162 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
163 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
164 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
165 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
166 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
167 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
168 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
169 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
170 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
171 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
172 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
173 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
174 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
175 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
176 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
177 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
178 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
179 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
180 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
181 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
185 };
186
187 enum {
188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
192 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
193 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
194 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
195 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
196 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
197 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
198 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
199 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
200 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
201 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
202 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
203 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
204 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
205 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
207 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
208 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
209 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
210 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
211 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
212 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
213 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
214 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
215 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
216 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
217 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
218 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
219 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
220 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
221 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
222 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
223 };
224
225 enum {
226 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
227 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
228 };
229
230 enum {
231 MLX4_VF_CAP_FLAG_RESET = 1 << 0
232 };
233
234 /* bit enums for an 8-bit flags field indicating special use
235 * QPs which require special handling in qp_reserve_range.
236 * Currently, this only includes QPs used by the ETH interface,
237 * where we expect to use blueflame. These QPs must not have
238 * bits 6 and 7 set in their qp number.
239 *
240 * This enum may use only bits 0..7.
241 */
242 enum {
243 MLX4_RESERVE_A0_QP = 1 << 6,
244 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
245 };
246
247 enum {
248 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
249 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
250 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
251 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
252 };
253
254 enum {
255 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
256 };
257
258 enum {
259 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
260 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
261 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
262 };
263
264
265 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
266
267 enum {
268 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
269 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
270 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
271 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
272 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
273 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
274 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
275 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
276 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
277 };
278
279 enum {
280 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
281 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
282 };
283
284 enum mlx4_event {
285 MLX4_EVENT_TYPE_COMP = 0x00,
286 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
287 MLX4_EVENT_TYPE_COMM_EST = 0x02,
288 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
289 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
290 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
291 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
292 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
293 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
294 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
295 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
296 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
297 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
298 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
299 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
300 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
301 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
302 MLX4_EVENT_TYPE_CMD = 0x0a,
303 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
304 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
305 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
306 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
307 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
308 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
309 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
310 MLX4_EVENT_TYPE_NONE = 0xff,
311 };
312
313 enum {
314 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
315 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
316 };
317
318 enum {
319 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
320 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
321 };
322
323 enum {
324 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
325 };
326
327 enum slave_port_state {
328 SLAVE_PORT_DOWN = 0,
329 SLAVE_PENDING_UP,
330 SLAVE_PORT_UP,
331 };
332
333 enum slave_port_gen_event {
334 SLAVE_PORT_GEN_EVENT_DOWN = 0,
335 SLAVE_PORT_GEN_EVENT_UP,
336 SLAVE_PORT_GEN_EVENT_NONE,
337 };
338
339 enum slave_port_state_event {
340 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
341 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
342 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
343 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
344 };
345
346 enum {
347 MLX4_PERM_LOCAL_READ = 1 << 10,
348 MLX4_PERM_LOCAL_WRITE = 1 << 11,
349 MLX4_PERM_REMOTE_READ = 1 << 12,
350 MLX4_PERM_REMOTE_WRITE = 1 << 13,
351 MLX4_PERM_ATOMIC = 1 << 14,
352 MLX4_PERM_BIND_MW = 1 << 15,
353 MLX4_PERM_MASK = 0xFC00
354 };
355
356 enum {
357 MLX4_OPCODE_NOP = 0x00,
358 MLX4_OPCODE_SEND_INVAL = 0x01,
359 MLX4_OPCODE_RDMA_WRITE = 0x08,
360 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
361 MLX4_OPCODE_SEND = 0x0a,
362 MLX4_OPCODE_SEND_IMM = 0x0b,
363 MLX4_OPCODE_LSO = 0x0e,
364 MLX4_OPCODE_RDMA_READ = 0x10,
365 MLX4_OPCODE_ATOMIC_CS = 0x11,
366 MLX4_OPCODE_ATOMIC_FA = 0x12,
367 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
368 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
369 MLX4_OPCODE_BIND_MW = 0x18,
370 MLX4_OPCODE_FMR = 0x19,
371 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
372 MLX4_OPCODE_CONFIG_CMD = 0x1f,
373
374 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
375 MLX4_RECV_OPCODE_SEND = 0x01,
376 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
377 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
378
379 MLX4_CQE_OPCODE_ERROR = 0x1e,
380 MLX4_CQE_OPCODE_RESIZE = 0x16,
381 };
382
383 enum {
384 MLX4_STAT_RATE_OFFSET = 5
385 };
386
387 enum mlx4_protocol {
388 MLX4_PROT_IB_IPV6 = 0,
389 MLX4_PROT_ETH,
390 MLX4_PROT_IB_IPV4,
391 MLX4_PROT_FCOE
392 };
393
394 enum {
395 MLX4_MTT_FLAG_PRESENT = 1
396 };
397
398 enum mlx4_qp_region {
399 MLX4_QP_REGION_FW = 0,
400 MLX4_QP_REGION_RSS_RAW_ETH,
401 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
402 MLX4_QP_REGION_ETH_ADDR,
403 MLX4_QP_REGION_FC_ADDR,
404 MLX4_QP_REGION_FC_EXCH,
405 MLX4_NUM_QP_REGION
406 };
407
408 enum mlx4_port_type {
409 MLX4_PORT_TYPE_NONE = 0,
410 MLX4_PORT_TYPE_IB = 1,
411 MLX4_PORT_TYPE_ETH = 2,
412 MLX4_PORT_TYPE_AUTO = 3
413 };
414
415 enum mlx4_special_vlan_idx {
416 MLX4_NO_VLAN_IDX = 0,
417 MLX4_VLAN_MISS_IDX,
418 MLX4_VLAN_REGULAR
419 };
420
421 enum mlx4_steer_type {
422 MLX4_MC_STEER = 0,
423 MLX4_UC_STEER,
424 MLX4_NUM_STEERS
425 };
426
427 enum {
428 MLX4_NUM_FEXCH = 64 * 1024,
429 };
430
431 enum {
432 MLX4_MAX_FAST_REG_PAGES = 511,
433 };
434
435 enum {
436 /*
437 * Max wqe size for rdma read is 512 bytes, so this
438 * limits our max_sge_rd as the wqe needs to fit:
439 * - ctrl segment (16 bytes)
440 * - rdma segment (16 bytes)
441 * - scatter elements (16 bytes each)
442 */
443 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
444 };
445
446 enum {
447 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
448 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
449 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
450 };
451
452 /* Port mgmt change event handling */
453 enum {
454 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
455 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
456 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
457 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
458 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
459 };
460
461 enum {
462 MLX4_DEVICE_STATE_UP = 1 << 0,
463 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
464 };
465
466 enum {
467 MLX4_INTERFACE_STATE_UP = 1 << 0,
468 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
469 MLX4_INTERFACE_STATE_SHUTDOWN = 1 << 2,
470 };
471
472 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
473 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
474
475 enum mlx4_module_id {
476 MLX4_MODULE_ID_SFP = 0x3,
477 MLX4_MODULE_ID_QSFP = 0xC,
478 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
479 MLX4_MODULE_ID_QSFP28 = 0x11,
480 };
481
482 enum { /* rl */
483 MLX4_QP_RATE_LIMIT_NONE = 0,
484 MLX4_QP_RATE_LIMIT_KBS = 1,
485 MLX4_QP_RATE_LIMIT_MBS = 2,
486 MLX4_QP_RATE_LIMIT_GBS = 3
487 };
488
489 struct mlx4_rate_limit_caps {
490 u16 num_rates; /* Number of different rates */
491 u8 min_unit;
492 u16 min_val;
493 u8 max_unit;
494 u16 max_val;
495 };
496
497 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
498 {
499 return (major << 32) | (minor << 16) | subminor;
500 }
501
502 struct mlx4_phys_caps {
503 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
504 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
505 u32 num_phys_eqs;
506 u32 base_sqpn;
507 u32 base_proxy_sqpn;
508 u32 base_tunnel_sqpn;
509 };
510
511 struct mlx4_caps {
512 u64 fw_ver;
513 u32 function;
514 int num_ports;
515 int vl_cap[MLX4_MAX_PORTS + 1];
516 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
517 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
518 u64 def_mac[MLX4_MAX_PORTS + 1];
519 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
520 int gid_table_len[MLX4_MAX_PORTS + 1];
521 int pkey_table_len[MLX4_MAX_PORTS + 1];
522 int trans_type[MLX4_MAX_PORTS + 1];
523 int vendor_oui[MLX4_MAX_PORTS + 1];
524 int wavelength[MLX4_MAX_PORTS + 1];
525 u64 trans_code[MLX4_MAX_PORTS + 1];
526 int local_ca_ack_delay;
527 int num_uars;
528 u32 uar_page_size;
529 int bf_reg_size;
530 int bf_regs_per_page;
531 int max_sq_sg;
532 int max_rq_sg;
533 int num_qps;
534 int max_wqes;
535 int max_sq_desc_sz;
536 int max_rq_desc_sz;
537 int max_qp_init_rdma;
538 int max_qp_dest_rdma;
539 int max_tc_eth;
540 u32 *qp0_qkey;
541 u32 *qp0_proxy;
542 u32 *qp1_proxy;
543 u32 *qp0_tunnel;
544 u32 *qp1_tunnel;
545 int num_srqs;
546 int max_srq_wqes;
547 int max_srq_sge;
548 int reserved_srqs;
549 int num_cqs;
550 int max_cqes;
551 int reserved_cqs;
552 int num_sys_eqs;
553 int num_eqs;
554 int reserved_eqs;
555 int num_comp_vectors;
556 int num_mpts;
557 int max_fmr_maps;
558 int num_mtts;
559 int fmr_reserved_mtts;
560 int reserved_mtts;
561 int reserved_mrws;
562 int reserved_uars;
563 int num_mgms;
564 int num_amgms;
565 int reserved_mcgs;
566 int num_qp_per_mgm;
567 int steering_mode;
568 int dmfs_high_steer_mode;
569 int fs_log_max_ucast_qp_range_size;
570 int num_pds;
571 int reserved_pds;
572 int max_xrcds;
573 int reserved_xrcds;
574 int mtt_entry_sz;
575 u32 max_msg_sz;
576 u32 page_size_cap;
577 u64 flags;
578 u64 flags2;
579 u32 bmme_flags;
580 u32 reserved_lkey;
581 u16 stat_rate_support;
582 u8 port_width_cap[MLX4_MAX_PORTS + 1];
583 int max_gso_sz;
584 int max_rss_tbl_sz;
585 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
586 int reserved_qps;
587 int reserved_qps_base[MLX4_NUM_QP_REGION];
588 int log_num_macs;
589 int log_num_vlans;
590 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
591 u8 supported_type[MLX4_MAX_PORTS + 1];
592 u8 suggested_type[MLX4_MAX_PORTS + 1];
593 u8 default_sense[MLX4_MAX_PORTS + 1];
594 u32 port_mask[MLX4_MAX_PORTS + 1];
595 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
596 u32 max_counters;
597 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
598 u16 sqp_demux;
599 u32 eqe_size;
600 u32 cqe_size;
601 u8 eqe_factor;
602 u32 userspace_caps; /* userspace must be aware of these */
603 u32 function_caps; /* VFs must be aware of these */
604 u16 hca_core_clock;
605 u64 phys_port_id[MLX4_MAX_PORTS + 1];
606 int tunnel_offload_mode;
607 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
608 u8 phv_bit[MLX4_MAX_PORTS + 1];
609 u8 alloc_res_qp_mask;
610 u32 dmfs_high_rate_qpn_base;
611 u32 dmfs_high_rate_qpn_range;
612 u32 vf_caps;
613 struct mlx4_rate_limit_caps rl_caps;
614 };
615
616 struct mlx4_buf_list {
617 void *buf;
618 dma_addr_t map;
619 };
620
621 struct mlx4_buf {
622 struct mlx4_buf_list direct;
623 struct mlx4_buf_list *page_list;
624 int nbufs;
625 int npages;
626 int page_shift;
627 };
628
629 struct mlx4_mtt {
630 u32 offset;
631 int order;
632 int page_shift;
633 };
634
635 enum {
636 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
637 };
638
639 struct mlx4_db_pgdir {
640 struct list_head list;
641 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
642 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
643 unsigned long *bits[2];
644 __be32 *db_page;
645 dma_addr_t db_dma;
646 };
647
648 struct mlx4_ib_user_db_page;
649
650 struct mlx4_db {
651 __be32 *db;
652 union {
653 struct mlx4_db_pgdir *pgdir;
654 struct mlx4_ib_user_db_page *user_page;
655 } u;
656 dma_addr_t dma;
657 int index;
658 int order;
659 };
660
661 struct mlx4_hwq_resources {
662 struct mlx4_db db;
663 struct mlx4_mtt mtt;
664 struct mlx4_buf buf;
665 };
666
667 struct mlx4_mr {
668 struct mlx4_mtt mtt;
669 u64 iova;
670 u64 size;
671 u32 key;
672 u32 pd;
673 u32 access;
674 int enabled;
675 };
676
677 enum mlx4_mw_type {
678 MLX4_MW_TYPE_1 = 1,
679 MLX4_MW_TYPE_2 = 2,
680 };
681
682 struct mlx4_mw {
683 u32 key;
684 u32 pd;
685 enum mlx4_mw_type type;
686 int enabled;
687 };
688
689 struct mlx4_fmr {
690 struct mlx4_mr mr;
691 struct mlx4_mpt_entry *mpt;
692 __be64 *mtts;
693 dma_addr_t dma_handle;
694 int max_pages;
695 int max_maps;
696 int maps;
697 u8 page_shift;
698 };
699
700 struct mlx4_uar {
701 unsigned long pfn;
702 int index;
703 struct list_head bf_list;
704 unsigned free_bf_bmap;
705 void __iomem *map;
706 void __iomem *bf_map;
707 };
708
709 struct mlx4_bf {
710 unsigned int offset;
711 int buf_size;
712 struct mlx4_uar *uar;
713 void __iomem *reg;
714 };
715
716 struct mlx4_cq {
717 void (*comp) (struct mlx4_cq *);
718 void (*event) (struct mlx4_cq *, enum mlx4_event);
719
720 struct mlx4_uar *uar;
721
722 u32 cons_index;
723
724 u16 irq;
725 __be32 *set_ci_db;
726 __be32 *arm_db;
727 int arm_sn;
728
729 int cqn;
730 unsigned vector;
731
732 atomic_t refcount;
733 struct completion free;
734 struct {
735 struct list_head list;
736 void (*comp)(struct mlx4_cq *);
737 void *priv;
738 } tasklet_ctx;
739 int reset_notify_added;
740 struct list_head reset_notify;
741 };
742
743 struct mlx4_qp {
744 void (*event) (struct mlx4_qp *, enum mlx4_event);
745
746 int qpn;
747
748 atomic_t refcount;
749 struct completion free;
750 };
751
752 struct mlx4_srq {
753 void (*event) (struct mlx4_srq *, enum mlx4_event);
754
755 int srqn;
756 int max;
757 int max_gs;
758 int wqe_shift;
759
760 atomic_t refcount;
761 struct completion free;
762 };
763
764 struct mlx4_av {
765 __be32 port_pd;
766 u8 reserved1;
767 u8 g_slid;
768 __be16 dlid;
769 u8 reserved2;
770 u8 gid_index;
771 u8 stat_rate;
772 u8 hop_limit;
773 __be32 sl_tclass_flowlabel;
774 u8 dgid[16];
775 };
776
777 struct mlx4_eth_av {
778 __be32 port_pd;
779 u8 reserved1;
780 u8 smac_idx;
781 u16 reserved2;
782 u8 reserved3;
783 u8 gid_index;
784 u8 stat_rate;
785 u8 hop_limit;
786 __be32 sl_tclass_flowlabel;
787 u8 dgid[16];
788 u8 s_mac[6];
789 u8 reserved4[2];
790 __be16 vlan;
791 u8 mac[ETH_ALEN];
792 };
793
794 union mlx4_ext_av {
795 struct mlx4_av ib;
796 struct mlx4_eth_av eth;
797 };
798
799 /* Counters should be saturate once they reach their maximum value */
800 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
801 if ((value) > U32_MAX) \
802 counter = cpu_to_be32(U32_MAX); \
803 else \
804 counter = cpu_to_be32(value); \
805 } while (0)
806
807 struct mlx4_counter {
808 u8 reserved1[3];
809 u8 counter_mode;
810 __be32 num_ifc;
811 u32 reserved2[2];
812 __be64 rx_frames;
813 __be64 rx_bytes;
814 __be64 tx_frames;
815 __be64 tx_bytes;
816 };
817
818 struct mlx4_quotas {
819 int qp;
820 int cq;
821 int srq;
822 int mpt;
823 int mtt;
824 int counter;
825 int xrcd;
826 };
827
828 struct mlx4_vf_dev {
829 u8 min_port;
830 u8 n_ports;
831 };
832
833 enum mlx4_pci_status {
834 MLX4_PCI_STATUS_DISABLED,
835 MLX4_PCI_STATUS_ENABLED,
836 };
837
838 struct mlx4_dev_persistent {
839 struct pci_dev *pdev;
840 struct mlx4_dev *dev;
841 int nvfs[MLX4_MAX_PORTS + 1];
842 int num_vfs;
843 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
844 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
845 struct work_struct catas_work;
846 struct workqueue_struct *catas_wq;
847 struct mutex device_state_mutex; /* protect HW state */
848 u8 state;
849 struct mutex interface_state_mutex; /* protect SW state */
850 u8 interface_state;
851 struct mutex pci_status_mutex; /* sync pci state */
852 enum mlx4_pci_status pci_status;
853 };
854
855 struct mlx4_dev {
856 struct mlx4_dev_persistent *persist;
857 unsigned long flags;
858 unsigned long num_slaves;
859 struct mlx4_caps caps;
860 struct mlx4_phys_caps phys_caps;
861 struct mlx4_quotas quotas;
862 struct radix_tree_root qp_table_tree;
863 u8 rev_id;
864 u8 port_random_macs;
865 char board_id[MLX4_BOARD_ID_LEN];
866 int numa_node;
867 int oper_log_mgm_entry_size;
868 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
869 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
870 struct mlx4_vf_dev *dev_vfs;
871 u8 uar_page_shift;
872 };
873
874 struct mlx4_clock_params {
875 u64 offset;
876 u8 bar;
877 u8 size;
878 };
879
880 struct mlx4_eqe {
881 u8 reserved1;
882 u8 type;
883 u8 reserved2;
884 u8 subtype;
885 union {
886 u32 raw[6];
887 struct {
888 __be32 cqn;
889 } __packed comp;
890 struct {
891 u16 reserved1;
892 __be16 token;
893 u32 reserved2;
894 u8 reserved3[3];
895 u8 status;
896 __be64 out_param;
897 } __packed cmd;
898 struct {
899 __be32 qpn;
900 } __packed qp;
901 struct {
902 __be32 srqn;
903 } __packed srq;
904 struct {
905 __be32 cqn;
906 u32 reserved1;
907 u8 reserved2[3];
908 u8 syndrome;
909 } __packed cq_err;
910 struct {
911 u32 reserved1[2];
912 __be32 port;
913 } __packed port_change;
914 struct {
915 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
916 u32 reserved;
917 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
918 } __packed comm_channel_arm;
919 struct {
920 u8 port;
921 u8 reserved[3];
922 __be64 mac;
923 } __packed mac_update;
924 struct {
925 __be32 slave_id;
926 } __packed flr_event;
927 struct {
928 __be16 current_temperature;
929 __be16 warning_threshold;
930 } __packed warming;
931 struct {
932 u8 reserved[3];
933 u8 port;
934 union {
935 struct {
936 __be16 mstr_sm_lid;
937 __be16 port_lid;
938 __be32 changed_attr;
939 u8 reserved[3];
940 u8 mstr_sm_sl;
941 __be64 gid_prefix;
942 } __packed port_info;
943 struct {
944 __be32 block_ptr;
945 __be32 tbl_entries_mask;
946 } __packed tbl_change_info;
947 } params;
948 } __packed port_mgmt_change;
949 struct {
950 u8 reserved[3];
951 u8 port;
952 u32 reserved1[5];
953 } __packed bad_cable;
954 } event;
955 u8 slave_id;
956 u8 reserved3[2];
957 u8 owner;
958 } __packed;
959
960 struct mlx4_init_port_param {
961 int set_guid0;
962 int set_node_guid;
963 int set_si_guid;
964 u16 mtu;
965 int port_width_cap;
966 u16 vl_cap;
967 u16 max_gid;
968 u16 max_pkey;
969 u64 guid0;
970 u64 node_guid;
971 u64 si_guid;
972 };
973
974 #define MAD_IFC_DATA_SZ 192
975 /* MAD IFC Mailbox */
976 struct mlx4_mad_ifc {
977 u8 base_version;
978 u8 mgmt_class;
979 u8 class_version;
980 u8 method;
981 __be16 status;
982 __be16 class_specific;
983 __be64 tid;
984 __be16 attr_id;
985 __be16 resv;
986 __be32 attr_mod;
987 __be64 mkey;
988 __be16 dr_slid;
989 __be16 dr_dlid;
990 u8 reserved[28];
991 u8 data[MAD_IFC_DATA_SZ];
992 } __packed;
993
994 #define mlx4_foreach_port(port, dev, type) \
995 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
996 if ((type) == (dev)->caps.port_mask[(port)])
997
998 #define mlx4_foreach_ib_transport_port(port, dev) \
999 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1000 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1001 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \
1002 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2))
1003
1004 #define MLX4_INVALID_SLAVE_ID 0xFF
1005 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1006
1007 void handle_port_mgmt_change_event(struct work_struct *work);
1008
1009 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1010 {
1011 return dev->caps.function;
1012 }
1013
1014 static inline int mlx4_is_master(struct mlx4_dev *dev)
1015 {
1016 return dev->flags & MLX4_FLAG_MASTER;
1017 }
1018
1019 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1020 {
1021 return dev->phys_caps.base_sqpn + 8 +
1022 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1023 }
1024
1025 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1026 {
1027 return (qpn < dev->phys_caps.base_sqpn + 8 +
1028 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1029 qpn >= dev->phys_caps.base_sqpn) ||
1030 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1031 }
1032
1033 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1034 {
1035 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1036
1037 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1038 return 1;
1039
1040 return 0;
1041 }
1042
1043 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1044 {
1045 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1046 }
1047
1048 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1049 {
1050 return dev->flags & MLX4_FLAG_SLAVE;
1051 }
1052
1053 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1054 {
1055 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1056 }
1057
1058 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1059 struct mlx4_buf *buf, gfp_t gfp);
1060 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1061 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1062 {
1063 if (buf->nbufs == 1)
1064 return buf->direct.buf + offset;
1065 else
1066 return buf->page_list[offset >> PAGE_SHIFT].buf +
1067 (offset & (PAGE_SIZE - 1));
1068 }
1069
1070 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1071 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1072 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1073 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1074
1075 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1076 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1077 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1078 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1079
1080 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1081 struct mlx4_mtt *mtt);
1082 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1083 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1084
1085 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1086 int npages, int page_shift, struct mlx4_mr *mr);
1087 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1088 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1089 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1090 struct mlx4_mw *mw);
1091 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1092 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1093 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1094 int start_index, int npages, u64 *page_list);
1095 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1096 struct mlx4_buf *buf, gfp_t gfp);
1097
1098 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1099 gfp_t gfp);
1100 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1101
1102 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1103 int size);
1104 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1105 int size);
1106
1107 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1108 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1109 unsigned vector, int collapsed, int timestamp_en);
1110 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1111 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1112 int *base, u8 flags);
1113 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1114
1115 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1116 gfp_t gfp);
1117 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1118
1119 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1120 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1121 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1122 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1123 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1124
1125 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1126 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1127
1128 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1129 int block_mcast_loopback, enum mlx4_protocol prot);
1130 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1131 enum mlx4_protocol prot);
1132 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1133 u8 port, int block_mcast_loopback,
1134 enum mlx4_protocol protocol, u64 *reg_id);
1135 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1136 enum mlx4_protocol protocol, u64 reg_id);
1137
1138 enum {
1139 MLX4_DOMAIN_UVERBS = 0x1000,
1140 MLX4_DOMAIN_ETHTOOL = 0x2000,
1141 MLX4_DOMAIN_RFS = 0x3000,
1142 MLX4_DOMAIN_NIC = 0x5000,
1143 };
1144
1145 enum mlx4_net_trans_rule_id {
1146 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1147 MLX4_NET_TRANS_RULE_ID_IB,
1148 MLX4_NET_TRANS_RULE_ID_IPV6,
1149 MLX4_NET_TRANS_RULE_ID_IPV4,
1150 MLX4_NET_TRANS_RULE_ID_TCP,
1151 MLX4_NET_TRANS_RULE_ID_UDP,
1152 MLX4_NET_TRANS_RULE_ID_VXLAN,
1153 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1154 };
1155
1156 extern const u16 __sw_id_hw[];
1157
1158 static inline int map_hw_to_sw_id(u16 header_id)
1159 {
1160
1161 int i;
1162 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1163 if (header_id == __sw_id_hw[i])
1164 return i;
1165 }
1166 return -EINVAL;
1167 }
1168
1169 enum mlx4_net_trans_promisc_mode {
1170 MLX4_FS_REGULAR = 1,
1171 MLX4_FS_ALL_DEFAULT,
1172 MLX4_FS_MC_DEFAULT,
1173 MLX4_FS_MIRROR_RX_PORT,
1174 MLX4_FS_MIRROR_SX_PORT,
1175 MLX4_FS_UC_SNIFFER,
1176 MLX4_FS_MC_SNIFFER,
1177 MLX4_FS_MODE_NUM, /* should be last */
1178 };
1179
1180 struct mlx4_spec_eth {
1181 u8 dst_mac[ETH_ALEN];
1182 u8 dst_mac_msk[ETH_ALEN];
1183 u8 src_mac[ETH_ALEN];
1184 u8 src_mac_msk[ETH_ALEN];
1185 u8 ether_type_enable;
1186 __be16 ether_type;
1187 __be16 vlan_id_msk;
1188 __be16 vlan_id;
1189 };
1190
1191 struct mlx4_spec_tcp_udp {
1192 __be16 dst_port;
1193 __be16 dst_port_msk;
1194 __be16 src_port;
1195 __be16 src_port_msk;
1196 };
1197
1198 struct mlx4_spec_ipv4 {
1199 __be32 dst_ip;
1200 __be32 dst_ip_msk;
1201 __be32 src_ip;
1202 __be32 src_ip_msk;
1203 };
1204
1205 struct mlx4_spec_ib {
1206 __be32 l3_qpn;
1207 __be32 qpn_msk;
1208 u8 dst_gid[16];
1209 u8 dst_gid_msk[16];
1210 };
1211
1212 struct mlx4_spec_vxlan {
1213 __be32 vni;
1214 __be32 vni_mask;
1215
1216 };
1217
1218 struct mlx4_spec_list {
1219 struct list_head list;
1220 enum mlx4_net_trans_rule_id id;
1221 union {
1222 struct mlx4_spec_eth eth;
1223 struct mlx4_spec_ib ib;
1224 struct mlx4_spec_ipv4 ipv4;
1225 struct mlx4_spec_tcp_udp tcp_udp;
1226 struct mlx4_spec_vxlan vxlan;
1227 };
1228 };
1229
1230 enum mlx4_net_trans_hw_rule_queue {
1231 MLX4_NET_TRANS_Q_FIFO,
1232 MLX4_NET_TRANS_Q_LIFO,
1233 };
1234
1235 struct mlx4_net_trans_rule {
1236 struct list_head list;
1237 enum mlx4_net_trans_hw_rule_queue queue_mode;
1238 bool exclusive;
1239 bool allow_loopback;
1240 enum mlx4_net_trans_promisc_mode promisc_mode;
1241 u8 port;
1242 u16 priority;
1243 u32 qpn;
1244 };
1245
1246 struct mlx4_net_trans_rule_hw_ctrl {
1247 __be16 prio;
1248 u8 type;
1249 u8 flags;
1250 u8 rsvd1;
1251 u8 funcid;
1252 u8 vep;
1253 u8 port;
1254 __be32 qpn;
1255 __be32 rsvd2;
1256 };
1257
1258 struct mlx4_net_trans_rule_hw_ib {
1259 u8 size;
1260 u8 rsvd1;
1261 __be16 id;
1262 u32 rsvd2;
1263 __be32 l3_qpn;
1264 __be32 qpn_mask;
1265 u8 dst_gid[16];
1266 u8 dst_gid_msk[16];
1267 } __packed;
1268
1269 struct mlx4_net_trans_rule_hw_eth {
1270 u8 size;
1271 u8 rsvd;
1272 __be16 id;
1273 u8 rsvd1[6];
1274 u8 dst_mac[6];
1275 u16 rsvd2;
1276 u8 dst_mac_msk[6];
1277 u16 rsvd3;
1278 u8 src_mac[6];
1279 u16 rsvd4;
1280 u8 src_mac_msk[6];
1281 u8 rsvd5;
1282 u8 ether_type_enable;
1283 __be16 ether_type;
1284 __be16 vlan_tag_msk;
1285 __be16 vlan_tag;
1286 } __packed;
1287
1288 struct mlx4_net_trans_rule_hw_tcp_udp {
1289 u8 size;
1290 u8 rsvd;
1291 __be16 id;
1292 __be16 rsvd1[3];
1293 __be16 dst_port;
1294 __be16 rsvd2;
1295 __be16 dst_port_msk;
1296 __be16 rsvd3;
1297 __be16 src_port;
1298 __be16 rsvd4;
1299 __be16 src_port_msk;
1300 } __packed;
1301
1302 struct mlx4_net_trans_rule_hw_ipv4 {
1303 u8 size;
1304 u8 rsvd;
1305 __be16 id;
1306 __be32 rsvd1;
1307 __be32 dst_ip;
1308 __be32 dst_ip_msk;
1309 __be32 src_ip;
1310 __be32 src_ip_msk;
1311 } __packed;
1312
1313 struct mlx4_net_trans_rule_hw_vxlan {
1314 u8 size;
1315 u8 rsvd;
1316 __be16 id;
1317 __be32 rsvd1;
1318 __be32 vni;
1319 __be32 vni_mask;
1320 } __packed;
1321
1322 struct _rule_hw {
1323 union {
1324 struct {
1325 u8 size;
1326 u8 rsvd;
1327 __be16 id;
1328 };
1329 struct mlx4_net_trans_rule_hw_eth eth;
1330 struct mlx4_net_trans_rule_hw_ib ib;
1331 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1332 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1333 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1334 };
1335 };
1336
1337 enum {
1338 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1339 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1340 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1341 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1342 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1343 };
1344
1345
1346 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1347 enum mlx4_net_trans_promisc_mode mode);
1348 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1349 enum mlx4_net_trans_promisc_mode mode);
1350 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1351 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1352 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1353 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1354 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1355
1356 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1357 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1358 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1359 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1360 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1361 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1362 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1363 u8 promisc);
1364 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1365 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1366 u8 ignore_fcs_value);
1367 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1368 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1369 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1370 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1371 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1372 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1373 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1374
1375 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1376 int npages, u64 iova, u32 *lkey, u32 *rkey);
1377 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1378 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1379 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1380 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1381 u32 *lkey, u32 *rkey);
1382 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1383 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1384 int mlx4_test_interrupts(struct mlx4_dev *dev);
1385 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1386 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1387 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1388 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1389 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1390
1391 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1392 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1393
1394 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1395 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1396 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1397
1398 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1399 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1400 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1401
1402 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1403 int port);
1404 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1405 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1406 int mlx4_flow_attach(struct mlx4_dev *dev,
1407 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1408 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1409 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1410 enum mlx4_net_trans_promisc_mode flow_type);
1411 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1412 enum mlx4_net_trans_rule_id id);
1413 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1414
1415 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1416 int port, int qpn, u16 prio, u64 *reg_id);
1417
1418 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1419 int i, int val);
1420
1421 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1422
1423 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1424 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1425 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1426 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1427 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1428 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1429 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1430
1431 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1432 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1433
1434 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1435 int *slave_id);
1436 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1437 u8 *gid);
1438
1439 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1440 u32 max_range_qpn);
1441
1442 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1443
1444 struct mlx4_active_ports {
1445 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1446 };
1447 /* Returns a bitmap of the physical ports which are assigned to slave */
1448 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1449
1450 /* Returns the physical port that represents the virtual port of the slave, */
1451 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1452 /* mapping is returned. */
1453 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1454
1455 struct mlx4_slaves_pport {
1456 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1457 };
1458 /* Returns a bitmap of all slaves that are assigned to port. */
1459 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1460 int port);
1461
1462 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1463 /* the ports that are set in crit_ports. */
1464 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1465 struct mlx4_dev *dev,
1466 const struct mlx4_active_ports *crit_ports);
1467
1468 /* Returns the slave's virtual port that represents the physical port. */
1469 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1470
1471 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1472
1473 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1474 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1475 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1476 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1477 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1478 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1479 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1480 int enable);
1481 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1482 struct mlx4_mpt_entry ***mpt_entry);
1483 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1484 struct mlx4_mpt_entry **mpt_entry);
1485 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1486 u32 pdn);
1487 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1488 struct mlx4_mpt_entry *mpt_entry,
1489 u32 access);
1490 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1491 struct mlx4_mpt_entry **mpt_entry);
1492 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1493 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1494 u64 iova, u64 size, int npages,
1495 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1496
1497 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1498 u16 offset, u16 size, u8 *data);
1499 int mlx4_max_tc(struct mlx4_dev *dev);
1500
1501 /* Returns true if running in low memory profile (kdump kernel) */
1502 static inline bool mlx4_low_memory_profile(void)
1503 {
1504 return is_kdump_kernel();
1505 }
1506
1507 /* ACCESS REG commands */
1508 enum mlx4_access_reg_method {
1509 MLX4_ACCESS_REG_QUERY = 0x1,
1510 MLX4_ACCESS_REG_WRITE = 0x2,
1511 };
1512
1513 /* ACCESS PTYS Reg command */
1514 enum mlx4_ptys_proto {
1515 MLX4_PTYS_IB = 1<<0,
1516 MLX4_PTYS_EN = 1<<2,
1517 };
1518
1519 struct mlx4_ptys_reg {
1520 u8 resrvd1;
1521 u8 local_port;
1522 u8 resrvd2;
1523 u8 proto_mask;
1524 __be32 resrvd3[2];
1525 __be32 eth_proto_cap;
1526 __be16 ib_width_cap;
1527 __be16 ib_speed_cap;
1528 __be32 resrvd4;
1529 __be32 eth_proto_admin;
1530 __be16 ib_width_admin;
1531 __be16 ib_speed_admin;
1532 __be32 resrvd5;
1533 __be32 eth_proto_oper;
1534 __be16 ib_width_oper;
1535 __be16 ib_speed_oper;
1536 __be32 resrvd6;
1537 __be32 eth_proto_lp_adv;
1538 } __packed;
1539
1540 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1541 enum mlx4_access_reg_method method,
1542 struct mlx4_ptys_reg *ptys_reg);
1543
1544 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1545 struct mlx4_clock_params *params);
1546
1547 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1548 {
1549 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1550 }
1551
1552 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1553 {
1554 /* The first 128 UARs are used for EQ doorbells */
1555 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1556 }
1557 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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