projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
net/mlx4_core: Set device configuration data to be persistent across reset
[deliverable/linux.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
51
52 #define MLX4_NUM_UP 8
53 #define MLX4_NUM_TC 8
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
58 */
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
62
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
65
66 enum {
67 MLX4_FLAG_MSI_X = 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
69 MLX4_FLAG_MASTER = 1 << 2,
70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
73 };
74
75 enum {
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
78 };
79
80 enum {
81 MLX4_MAX_PORTS = 2,
82 MLX4_MAX_PORT_PKEYS = 128
83 };
84
85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
86 * These qkeys must not be allowed for general use. This is a 64k range,
87 * and to test for violation, we use the mask (protect against future chg).
88 */
89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
91
92 enum {
93 MLX4_BOARD_ID_LEN = 64
94 };
95
96 enum {
97 MLX4_MAX_NUM_PF = 16,
98 MLX4_MAX_NUM_VF = 126,
99 MLX4_MAX_NUM_VF_P_PORT = 64,
100 MLX4_MFUNC_MAX = 80,
101 MLX4_MAX_EQ_NUM = 1024,
102 MLX4_MFUNC_EQ_NUM = 4,
103 MLX4_MFUNC_MAX_EQES = 8,
104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
105 };
106
107 /* Driver supports 3 diffrent device methods to manage traffic steering:
108 * -device managed - High level API for ib and eth flow steering. FW is
109 * managing flow steering tables.
110 * - B0 steering mode - Common low level API for ib and (if supported) eth.
111 * - A0 steering mode - Limited low level API for eth. In case of IB,
112 * B0 mode is in use.
113 */
114 enum {
115 MLX4_STEERING_MODE_A0,
116 MLX4_STEERING_MODE_B0,
117 MLX4_STEERING_MODE_DEVICE_MANAGED
118 };
119
120 enum {
121 MLX4_STEERING_DMFS_A0_DEFAULT,
122 MLX4_STEERING_DMFS_A0_DYNAMIC,
123 MLX4_STEERING_DMFS_A0_STATIC,
124 MLX4_STEERING_DMFS_A0_DISABLE,
125 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
126 };
127
128 static inline const char *mlx4_steering_mode_str(int steering_mode)
129 {
130 switch (steering_mode) {
131 case MLX4_STEERING_MODE_A0:
132 return "A0 steering";
133
134 case MLX4_STEERING_MODE_B0:
135 return "B0 steering";
136
137 case MLX4_STEERING_MODE_DEVICE_MANAGED:
138 return "Device managed flow steering";
139
140 default:
141 return "Unrecognize steering mode";
142 }
143 }
144
145 enum {
146 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
147 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
148 };
149
150 enum {
151 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
152 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
153 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
154 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
155 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
156 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
157 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
158 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
159 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
160 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
161 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
162 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
163 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
164 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
165 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
166 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
167 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
168 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
169 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
170 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
171 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
172 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
173 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
174 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
175 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
176 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
177 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
178 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
179 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
180 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
181 };
182
183 enum {
184 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
185 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
186 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
187 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
188 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
190 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
191 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
192 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
193 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
194 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
195 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
196 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
197 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
198 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
199 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
201 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
202 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
203 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19
204 };
205
206 enum {
207 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
208 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
209 };
210
211 /* bit enums for an 8-bit flags field indicating special use
212 * QPs which require special handling in qp_reserve_range.
213 * Currently, this only includes QPs used by the ETH interface,
214 * where we expect to use blueflame. These QPs must not have
215 * bits 6 and 7 set in their qp number.
216 *
217 * This enum may use only bits 0..7.
218 */
219 enum {
220 MLX4_RESERVE_A0_QP = 1 << 6,
221 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
222 };
223
224 enum {
225 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
226 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
227 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
228 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
229 };
230
231 enum {
232 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
233 };
234
235 enum {
236 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
237 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
238 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
239 };
240
241
242 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
243
244 enum {
245 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
246 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
247 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
248 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
249 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
250 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
251 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
252 };
253
254 enum mlx4_event {
255 MLX4_EVENT_TYPE_COMP = 0x00,
256 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
257 MLX4_EVENT_TYPE_COMM_EST = 0x02,
258 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
259 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
260 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
261 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
262 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
263 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
264 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
265 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
266 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
267 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
268 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
269 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
270 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
271 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
272 MLX4_EVENT_TYPE_CMD = 0x0a,
273 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
274 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
275 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
276 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
277 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
278 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
279 MLX4_EVENT_TYPE_NONE = 0xff,
280 };
281
282 enum {
283 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
284 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
285 };
286
287 enum {
288 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
289 };
290
291 enum slave_port_state {
292 SLAVE_PORT_DOWN = 0,
293 SLAVE_PENDING_UP,
294 SLAVE_PORT_UP,
295 };
296
297 enum slave_port_gen_event {
298 SLAVE_PORT_GEN_EVENT_DOWN = 0,
299 SLAVE_PORT_GEN_EVENT_UP,
300 SLAVE_PORT_GEN_EVENT_NONE,
301 };
302
303 enum slave_port_state_event {
304 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
305 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
306 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
307 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
308 };
309
310 enum {
311 MLX4_PERM_LOCAL_READ = 1 << 10,
312 MLX4_PERM_LOCAL_WRITE = 1 << 11,
313 MLX4_PERM_REMOTE_READ = 1 << 12,
314 MLX4_PERM_REMOTE_WRITE = 1 << 13,
315 MLX4_PERM_ATOMIC = 1 << 14,
316 MLX4_PERM_BIND_MW = 1 << 15,
317 MLX4_PERM_MASK = 0xFC00
318 };
319
320 enum {
321 MLX4_OPCODE_NOP = 0x00,
322 MLX4_OPCODE_SEND_INVAL = 0x01,
323 MLX4_OPCODE_RDMA_WRITE = 0x08,
324 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
325 MLX4_OPCODE_SEND = 0x0a,
326 MLX4_OPCODE_SEND_IMM = 0x0b,
327 MLX4_OPCODE_LSO = 0x0e,
328 MLX4_OPCODE_RDMA_READ = 0x10,
329 MLX4_OPCODE_ATOMIC_CS = 0x11,
330 MLX4_OPCODE_ATOMIC_FA = 0x12,
331 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
332 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
333 MLX4_OPCODE_BIND_MW = 0x18,
334 MLX4_OPCODE_FMR = 0x19,
335 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
336 MLX4_OPCODE_CONFIG_CMD = 0x1f,
337
338 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
339 MLX4_RECV_OPCODE_SEND = 0x01,
340 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
341 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
342
343 MLX4_CQE_OPCODE_ERROR = 0x1e,
344 MLX4_CQE_OPCODE_RESIZE = 0x16,
345 };
346
347 enum {
348 MLX4_STAT_RATE_OFFSET = 5
349 };
350
351 enum mlx4_protocol {
352 MLX4_PROT_IB_IPV6 = 0,
353 MLX4_PROT_ETH,
354 MLX4_PROT_IB_IPV4,
355 MLX4_PROT_FCOE
356 };
357
358 enum {
359 MLX4_MTT_FLAG_PRESENT = 1
360 };
361
362 enum mlx4_qp_region {
363 MLX4_QP_REGION_FW = 0,
364 MLX4_QP_REGION_RSS_RAW_ETH,
365 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
366 MLX4_QP_REGION_ETH_ADDR,
367 MLX4_QP_REGION_FC_ADDR,
368 MLX4_QP_REGION_FC_EXCH,
369 MLX4_NUM_QP_REGION
370 };
371
372 enum mlx4_port_type {
373 MLX4_PORT_TYPE_NONE = 0,
374 MLX4_PORT_TYPE_IB = 1,
375 MLX4_PORT_TYPE_ETH = 2,
376 MLX4_PORT_TYPE_AUTO = 3
377 };
378
379 enum mlx4_special_vlan_idx {
380 MLX4_NO_VLAN_IDX = 0,
381 MLX4_VLAN_MISS_IDX,
382 MLX4_VLAN_REGULAR
383 };
384
385 enum mlx4_steer_type {
386 MLX4_MC_STEER = 0,
387 MLX4_UC_STEER,
388 MLX4_NUM_STEERS
389 };
390
391 enum {
392 MLX4_NUM_FEXCH = 64 * 1024,
393 };
394
395 enum {
396 MLX4_MAX_FAST_REG_PAGES = 511,
397 };
398
399 enum {
400 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
401 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
402 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
403 };
404
405 /* Port mgmt change event handling */
406 enum {
407 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
408 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
409 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
410 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
411 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
412 };
413
414 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
415 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
416
417 enum mlx4_module_id {
418 MLX4_MODULE_ID_SFP = 0x3,
419 MLX4_MODULE_ID_QSFP = 0xC,
420 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
421 MLX4_MODULE_ID_QSFP28 = 0x11,
422 };
423
424 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
425 {
426 return (major << 32) | (minor << 16) | subminor;
427 }
428
429 struct mlx4_phys_caps {
430 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
431 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
432 u32 num_phys_eqs;
433 u32 base_sqpn;
434 u32 base_proxy_sqpn;
435 u32 base_tunnel_sqpn;
436 };
437
438 struct mlx4_caps {
439 u64 fw_ver;
440 u32 function;
441 int num_ports;
442 int vl_cap[MLX4_MAX_PORTS + 1];
443 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
444 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
445 u64 def_mac[MLX4_MAX_PORTS + 1];
446 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
447 int gid_table_len[MLX4_MAX_PORTS + 1];
448 int pkey_table_len[MLX4_MAX_PORTS + 1];
449 int trans_type[MLX4_MAX_PORTS + 1];
450 int vendor_oui[MLX4_MAX_PORTS + 1];
451 int wavelength[MLX4_MAX_PORTS + 1];
452 u64 trans_code[MLX4_MAX_PORTS + 1];
453 int local_ca_ack_delay;
454 int num_uars;
455 u32 uar_page_size;
456 int bf_reg_size;
457 int bf_regs_per_page;
458 int max_sq_sg;
459 int max_rq_sg;
460 int num_qps;
461 int max_wqes;
462 int max_sq_desc_sz;
463 int max_rq_desc_sz;
464 int max_qp_init_rdma;
465 int max_qp_dest_rdma;
466 u32 *qp0_qkey;
467 u32 *qp0_proxy;
468 u32 *qp1_proxy;
469 u32 *qp0_tunnel;
470 u32 *qp1_tunnel;
471 int num_srqs;
472 int max_srq_wqes;
473 int max_srq_sge;
474 int reserved_srqs;
475 int num_cqs;
476 int max_cqes;
477 int reserved_cqs;
478 int num_sys_eqs;
479 int num_eqs;
480 int reserved_eqs;
481 int num_comp_vectors;
482 int comp_pool;
483 int num_mpts;
484 int max_fmr_maps;
485 int num_mtts;
486 int fmr_reserved_mtts;
487 int reserved_mtts;
488 int reserved_mrws;
489 int reserved_uars;
490 int num_mgms;
491 int num_amgms;
492 int reserved_mcgs;
493 int num_qp_per_mgm;
494 int steering_mode;
495 int dmfs_high_steer_mode;
496 int fs_log_max_ucast_qp_range_size;
497 int num_pds;
498 int reserved_pds;
499 int max_xrcds;
500 int reserved_xrcds;
501 int mtt_entry_sz;
502 u32 max_msg_sz;
503 u32 page_size_cap;
504 u64 flags;
505 u64 flags2;
506 u32 bmme_flags;
507 u32 reserved_lkey;
508 u16 stat_rate_support;
509 u8 port_width_cap[MLX4_MAX_PORTS + 1];
510 int max_gso_sz;
511 int max_rss_tbl_sz;
512 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
513 int reserved_qps;
514 int reserved_qps_base[MLX4_NUM_QP_REGION];
515 int log_num_macs;
516 int log_num_vlans;
517 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
518 u8 supported_type[MLX4_MAX_PORTS + 1];
519 u8 suggested_type[MLX4_MAX_PORTS + 1];
520 u8 default_sense[MLX4_MAX_PORTS + 1];
521 u32 port_mask[MLX4_MAX_PORTS + 1];
522 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
523 u32 max_counters;
524 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
525 u16 sqp_demux;
526 u32 eqe_size;
527 u32 cqe_size;
528 u8 eqe_factor;
529 u32 userspace_caps; /* userspace must be aware of these */
530 u32 function_caps; /* VFs must be aware of these */
531 u16 hca_core_clock;
532 u64 phys_port_id[MLX4_MAX_PORTS + 1];
533 int tunnel_offload_mode;
534 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
535 u8 alloc_res_qp_mask;
536 u32 dmfs_high_rate_qpn_base;
537 u32 dmfs_high_rate_qpn_range;
538 };
539
540 struct mlx4_buf_list {
541 void *buf;
542 dma_addr_t map;
543 };
544
545 struct mlx4_buf {
546 struct mlx4_buf_list direct;
547 struct mlx4_buf_list *page_list;
548 int nbufs;
549 int npages;
550 int page_shift;
551 };
552
553 struct mlx4_mtt {
554 u32 offset;
555 int order;
556 int page_shift;
557 };
558
559 enum {
560 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
561 };
562
563 struct mlx4_db_pgdir {
564 struct list_head list;
565 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
566 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
567 unsigned long *bits[2];
568 __be32 *db_page;
569 dma_addr_t db_dma;
570 };
571
572 struct mlx4_ib_user_db_page;
573
574 struct mlx4_db {
575 __be32 *db;
576 union {
577 struct mlx4_db_pgdir *pgdir;
578 struct mlx4_ib_user_db_page *user_page;
579 } u;
580 dma_addr_t dma;
581 int index;
582 int order;
583 };
584
585 struct mlx4_hwq_resources {
586 struct mlx4_db db;
587 struct mlx4_mtt mtt;
588 struct mlx4_buf buf;
589 };
590
591 struct mlx4_mr {
592 struct mlx4_mtt mtt;
593 u64 iova;
594 u64 size;
595 u32 key;
596 u32 pd;
597 u32 access;
598 int enabled;
599 };
600
601 enum mlx4_mw_type {
602 MLX4_MW_TYPE_1 = 1,
603 MLX4_MW_TYPE_2 = 2,
604 };
605
606 struct mlx4_mw {
607 u32 key;
608 u32 pd;
609 enum mlx4_mw_type type;
610 int enabled;
611 };
612
613 struct mlx4_fmr {
614 struct mlx4_mr mr;
615 struct mlx4_mpt_entry *mpt;
616 __be64 *mtts;
617 dma_addr_t dma_handle;
618 int max_pages;
619 int max_maps;
620 int maps;
621 u8 page_shift;
622 };
623
624 struct mlx4_uar {
625 unsigned long pfn;
626 int index;
627 struct list_head bf_list;
628 unsigned free_bf_bmap;
629 void __iomem *map;
630 void __iomem *bf_map;
631 };
632
633 struct mlx4_bf {
634 unsigned int offset;
635 int buf_size;
636 struct mlx4_uar *uar;
637 void __iomem *reg;
638 };
639
640 struct mlx4_cq {
641 void (*comp) (struct mlx4_cq *);
642 void (*event) (struct mlx4_cq *, enum mlx4_event);
643
644 struct mlx4_uar *uar;
645
646 u32 cons_index;
647
648 u16 irq;
649 __be32 *set_ci_db;
650 __be32 *arm_db;
651 int arm_sn;
652
653 int cqn;
654 unsigned vector;
655
656 atomic_t refcount;
657 struct completion free;
658 struct {
659 struct list_head list;
660 void (*comp)(struct mlx4_cq *);
661 void *priv;
662 } tasklet_ctx;
663 };
664
665 struct mlx4_qp {
666 void (*event) (struct mlx4_qp *, enum mlx4_event);
667
668 int qpn;
669
670 atomic_t refcount;
671 struct completion free;
672 };
673
674 struct mlx4_srq {
675 void (*event) (struct mlx4_srq *, enum mlx4_event);
676
677 int srqn;
678 int max;
679 int max_gs;
680 int wqe_shift;
681
682 atomic_t refcount;
683 struct completion free;
684 };
685
686 struct mlx4_av {
687 __be32 port_pd;
688 u8 reserved1;
689 u8 g_slid;
690 __be16 dlid;
691 u8 reserved2;
692 u8 gid_index;
693 u8 stat_rate;
694 u8 hop_limit;
695 __be32 sl_tclass_flowlabel;
696 u8 dgid[16];
697 };
698
699 struct mlx4_eth_av {
700 __be32 port_pd;
701 u8 reserved1;
702 u8 smac_idx;
703 u16 reserved2;
704 u8 reserved3;
705 u8 gid_index;
706 u8 stat_rate;
707 u8 hop_limit;
708 __be32 sl_tclass_flowlabel;
709 u8 dgid[16];
710 u8 s_mac[6];
711 u8 reserved4[2];
712 __be16 vlan;
713 u8 mac[ETH_ALEN];
714 };
715
716 union mlx4_ext_av {
717 struct mlx4_av ib;
718 struct mlx4_eth_av eth;
719 };
720
721 struct mlx4_counter {
722 u8 reserved1[3];
723 u8 counter_mode;
724 __be32 num_ifc;
725 u32 reserved2[2];
726 __be64 rx_frames;
727 __be64 rx_bytes;
728 __be64 tx_frames;
729 __be64 tx_bytes;
730 };
731
732 struct mlx4_quotas {
733 int qp;
734 int cq;
735 int srq;
736 int mpt;
737 int mtt;
738 int counter;
739 int xrcd;
740 };
741
742 struct mlx4_vf_dev {
743 u8 min_port;
744 u8 n_ports;
745 };
746
747 struct mlx4_dev_persistent {
748 struct pci_dev *pdev;
749 struct mlx4_dev *dev;
750 int nvfs[MLX4_MAX_PORTS + 1];
751 int num_vfs;
752 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
753 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
754 };
755
756 struct mlx4_dev {
757 struct mlx4_dev_persistent *persist;
758 unsigned long flags;
759 unsigned long num_slaves;
760 struct mlx4_caps caps;
761 struct mlx4_phys_caps phys_caps;
762 struct mlx4_quotas quotas;
763 struct radix_tree_root qp_table_tree;
764 u8 rev_id;
765 char board_id[MLX4_BOARD_ID_LEN];
766 int numa_node;
767 int oper_log_mgm_entry_size;
768 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
769 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
770 struct mlx4_vf_dev *dev_vfs;
771 };
772
773 struct mlx4_eqe {
774 u8 reserved1;
775 u8 type;
776 u8 reserved2;
777 u8 subtype;
778 union {
779 u32 raw[6];
780 struct {
781 __be32 cqn;
782 } __packed comp;
783 struct {
784 u16 reserved1;
785 __be16 token;
786 u32 reserved2;
787 u8 reserved3[3];
788 u8 status;
789 __be64 out_param;
790 } __packed cmd;
791 struct {
792 __be32 qpn;
793 } __packed qp;
794 struct {
795 __be32 srqn;
796 } __packed srq;
797 struct {
798 __be32 cqn;
799 u32 reserved1;
800 u8 reserved2[3];
801 u8 syndrome;
802 } __packed cq_err;
803 struct {
804 u32 reserved1[2];
805 __be32 port;
806 } __packed port_change;
807 struct {
808 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
809 u32 reserved;
810 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
811 } __packed comm_channel_arm;
812 struct {
813 u8 port;
814 u8 reserved[3];
815 __be64 mac;
816 } __packed mac_update;
817 struct {
818 __be32 slave_id;
819 } __packed flr_event;
820 struct {
821 __be16 current_temperature;
822 __be16 warning_threshold;
823 } __packed warming;
824 struct {
825 u8 reserved[3];
826 u8 port;
827 union {
828 struct {
829 __be16 mstr_sm_lid;
830 __be16 port_lid;
831 __be32 changed_attr;
832 u8 reserved[3];
833 u8 mstr_sm_sl;
834 __be64 gid_prefix;
835 } __packed port_info;
836 struct {
837 __be32 block_ptr;
838 __be32 tbl_entries_mask;
839 } __packed tbl_change_info;
840 } params;
841 } __packed port_mgmt_change;
842 } event;
843 u8 slave_id;
844 u8 reserved3[2];
845 u8 owner;
846 } __packed;
847
848 struct mlx4_init_port_param {
849 int set_guid0;
850 int set_node_guid;
851 int set_si_guid;
852 u16 mtu;
853 int port_width_cap;
854 u16 vl_cap;
855 u16 max_gid;
856 u16 max_pkey;
857 u64 guid0;
858 u64 node_guid;
859 u64 si_guid;
860 };
861
862 #define MAD_IFC_DATA_SZ 192
863 /* MAD IFC Mailbox */
864 struct mlx4_mad_ifc {
865 u8 base_version;
866 u8 mgmt_class;
867 u8 class_version;
868 u8 method;
869 __be16 status;
870 __be16 class_specific;
871 __be64 tid;
872 __be16 attr_id;
873 __be16 resv;
874 __be32 attr_mod;
875 __be64 mkey;
876 __be16 dr_slid;
877 __be16 dr_dlid;
878 u8 reserved[28];
879 u8 data[MAD_IFC_DATA_SZ];
880 } __packed;
881
882 #define mlx4_foreach_port(port, dev, type) \
883 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
884 if ((type) == (dev)->caps.port_mask[(port)])
885
886 #define mlx4_foreach_non_ib_transport_port(port, dev) \
887 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
888 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
889
890 #define mlx4_foreach_ib_transport_port(port, dev) \
891 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
892 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
893 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
894
895 #define MLX4_INVALID_SLAVE_ID 0xFF
896
897 void handle_port_mgmt_change_event(struct work_struct *work);
898
899 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
900 {
901 return dev->caps.function;
902 }
903
904 static inline int mlx4_is_master(struct mlx4_dev *dev)
905 {
906 return dev->flags & MLX4_FLAG_MASTER;
907 }
908
909 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
910 {
911 return dev->phys_caps.base_sqpn + 8 +
912 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
913 }
914
915 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
916 {
917 return (qpn < dev->phys_caps.base_sqpn + 8 +
918 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
919 qpn >= dev->phys_caps.base_sqpn) ||
920 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
921 }
922
923 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
924 {
925 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
926
927 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
928 return 1;
929
930 return 0;
931 }
932
933 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
934 {
935 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
936 }
937
938 static inline int mlx4_is_slave(struct mlx4_dev *dev)
939 {
940 return dev->flags & MLX4_FLAG_SLAVE;
941 }
942
943 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
944 struct mlx4_buf *buf, gfp_t gfp);
945 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
946 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
947 {
948 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
949 return buf->direct.buf + offset;
950 else
951 return buf->page_list[offset >> PAGE_SHIFT].buf +
952 (offset & (PAGE_SIZE - 1));
953 }
954
955 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
956 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
957 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
958 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
959
960 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
961 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
962 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
963 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
964
965 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
966 struct mlx4_mtt *mtt);
967 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
968 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
969
970 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
971 int npages, int page_shift, struct mlx4_mr *mr);
972 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
973 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
974 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
975 struct mlx4_mw *mw);
976 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
977 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
978 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
979 int start_index, int npages, u64 *page_list);
980 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
981 struct mlx4_buf *buf, gfp_t gfp);
982
983 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
984 gfp_t gfp);
985 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
986
987 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
988 int size, int max_direct);
989 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
990 int size);
991
992 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
993 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
994 unsigned vector, int collapsed, int timestamp_en);
995 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
996 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
997 int *base, u8 flags);
998 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
999
1000 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1001 gfp_t gfp);
1002 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1003
1004 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1005 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1006 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1007 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1008 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1009
1010 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1011 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1012
1013 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1014 int block_mcast_loopback, enum mlx4_protocol prot);
1015 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1016 enum mlx4_protocol prot);
1017 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1018 u8 port, int block_mcast_loopback,
1019 enum mlx4_protocol protocol, u64 *reg_id);
1020 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1021 enum mlx4_protocol protocol, u64 reg_id);
1022
1023 enum {
1024 MLX4_DOMAIN_UVERBS = 0x1000,
1025 MLX4_DOMAIN_ETHTOOL = 0x2000,
1026 MLX4_DOMAIN_RFS = 0x3000,
1027 MLX4_DOMAIN_NIC = 0x5000,
1028 };
1029
1030 enum mlx4_net_trans_rule_id {
1031 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1032 MLX4_NET_TRANS_RULE_ID_IB,
1033 MLX4_NET_TRANS_RULE_ID_IPV6,
1034 MLX4_NET_TRANS_RULE_ID_IPV4,
1035 MLX4_NET_TRANS_RULE_ID_TCP,
1036 MLX4_NET_TRANS_RULE_ID_UDP,
1037 MLX4_NET_TRANS_RULE_ID_VXLAN,
1038 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1039 };
1040
1041 extern const u16 __sw_id_hw[];
1042
1043 static inline int map_hw_to_sw_id(u16 header_id)
1044 {
1045
1046 int i;
1047 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1048 if (header_id == __sw_id_hw[i])
1049 return i;
1050 }
1051 return -EINVAL;
1052 }
1053
1054 enum mlx4_net_trans_promisc_mode {
1055 MLX4_FS_REGULAR = 1,
1056 MLX4_FS_ALL_DEFAULT,
1057 MLX4_FS_MC_DEFAULT,
1058 MLX4_FS_UC_SNIFFER,
1059 MLX4_FS_MC_SNIFFER,
1060 MLX4_FS_MODE_NUM, /* should be last */
1061 };
1062
1063 struct mlx4_spec_eth {
1064 u8 dst_mac[ETH_ALEN];
1065 u8 dst_mac_msk[ETH_ALEN];
1066 u8 src_mac[ETH_ALEN];
1067 u8 src_mac_msk[ETH_ALEN];
1068 u8 ether_type_enable;
1069 __be16 ether_type;
1070 __be16 vlan_id_msk;
1071 __be16 vlan_id;
1072 };
1073
1074 struct mlx4_spec_tcp_udp {
1075 __be16 dst_port;
1076 __be16 dst_port_msk;
1077 __be16 src_port;
1078 __be16 src_port_msk;
1079 };
1080
1081 struct mlx4_spec_ipv4 {
1082 __be32 dst_ip;
1083 __be32 dst_ip_msk;
1084 __be32 src_ip;
1085 __be32 src_ip_msk;
1086 };
1087
1088 struct mlx4_spec_ib {
1089 __be32 l3_qpn;
1090 __be32 qpn_msk;
1091 u8 dst_gid[16];
1092 u8 dst_gid_msk[16];
1093 };
1094
1095 struct mlx4_spec_vxlan {
1096 __be32 vni;
1097 __be32 vni_mask;
1098
1099 };
1100
1101 struct mlx4_spec_list {
1102 struct list_head list;
1103 enum mlx4_net_trans_rule_id id;
1104 union {
1105 struct mlx4_spec_eth eth;
1106 struct mlx4_spec_ib ib;
1107 struct mlx4_spec_ipv4 ipv4;
1108 struct mlx4_spec_tcp_udp tcp_udp;
1109 struct mlx4_spec_vxlan vxlan;
1110 };
1111 };
1112
1113 enum mlx4_net_trans_hw_rule_queue {
1114 MLX4_NET_TRANS_Q_FIFO,
1115 MLX4_NET_TRANS_Q_LIFO,
1116 };
1117
1118 struct mlx4_net_trans_rule {
1119 struct list_head list;
1120 enum mlx4_net_trans_hw_rule_queue queue_mode;
1121 bool exclusive;
1122 bool allow_loopback;
1123 enum mlx4_net_trans_promisc_mode promisc_mode;
1124 u8 port;
1125 u16 priority;
1126 u32 qpn;
1127 };
1128
1129 struct mlx4_net_trans_rule_hw_ctrl {
1130 __be16 prio;
1131 u8 type;
1132 u8 flags;
1133 u8 rsvd1;
1134 u8 funcid;
1135 u8 vep;
1136 u8 port;
1137 __be32 qpn;
1138 __be32 rsvd2;
1139 };
1140
1141 struct mlx4_net_trans_rule_hw_ib {
1142 u8 size;
1143 u8 rsvd1;
1144 __be16 id;
1145 u32 rsvd2;
1146 __be32 l3_qpn;
1147 __be32 qpn_mask;
1148 u8 dst_gid[16];
1149 u8 dst_gid_msk[16];
1150 } __packed;
1151
1152 struct mlx4_net_trans_rule_hw_eth {
1153 u8 size;
1154 u8 rsvd;
1155 __be16 id;
1156 u8 rsvd1[6];
1157 u8 dst_mac[6];
1158 u16 rsvd2;
1159 u8 dst_mac_msk[6];
1160 u16 rsvd3;
1161 u8 src_mac[6];
1162 u16 rsvd4;
1163 u8 src_mac_msk[6];
1164 u8 rsvd5;
1165 u8 ether_type_enable;
1166 __be16 ether_type;
1167 __be16 vlan_tag_msk;
1168 __be16 vlan_tag;
1169 } __packed;
1170
1171 struct mlx4_net_trans_rule_hw_tcp_udp {
1172 u8 size;
1173 u8 rsvd;
1174 __be16 id;
1175 __be16 rsvd1[3];
1176 __be16 dst_port;
1177 __be16 rsvd2;
1178 __be16 dst_port_msk;
1179 __be16 rsvd3;
1180 __be16 src_port;
1181 __be16 rsvd4;
1182 __be16 src_port_msk;
1183 } __packed;
1184
1185 struct mlx4_net_trans_rule_hw_ipv4 {
1186 u8 size;
1187 u8 rsvd;
1188 __be16 id;
1189 __be32 rsvd1;
1190 __be32 dst_ip;
1191 __be32 dst_ip_msk;
1192 __be32 src_ip;
1193 __be32 src_ip_msk;
1194 } __packed;
1195
1196 struct mlx4_net_trans_rule_hw_vxlan {
1197 u8 size;
1198 u8 rsvd;
1199 __be16 id;
1200 __be32 rsvd1;
1201 __be32 vni;
1202 __be32 vni_mask;
1203 } __packed;
1204
1205 struct _rule_hw {
1206 union {
1207 struct {
1208 u8 size;
1209 u8 rsvd;
1210 __be16 id;
1211 };
1212 struct mlx4_net_trans_rule_hw_eth eth;
1213 struct mlx4_net_trans_rule_hw_ib ib;
1214 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1215 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1216 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1217 };
1218 };
1219
1220 enum {
1221 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1222 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1223 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1224 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1225 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1226 };
1227
1228
1229 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1230 enum mlx4_net_trans_promisc_mode mode);
1231 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1232 enum mlx4_net_trans_promisc_mode mode);
1233 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1234 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1235 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1236 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1237 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1238
1239 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1240 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1241 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1242 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1243 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1244 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1245 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1246 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1247 u8 promisc);
1248 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1249 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1250 u8 *pg, u16 *ratelimit);
1251 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1252 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1253 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1254 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1255 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1256
1257 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1258 int npages, u64 iova, u32 *lkey, u32 *rkey);
1259 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1260 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1261 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1262 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1263 u32 *lkey, u32 *rkey);
1264 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1265 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1266 int mlx4_test_interrupts(struct mlx4_dev *dev);
1267 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1268 int *vector);
1269 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1270
1271 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1272
1273 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1274 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1275 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1276
1277 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1278 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1279
1280 int mlx4_flow_attach(struct mlx4_dev *dev,
1281 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1282 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1283 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1284 enum mlx4_net_trans_promisc_mode flow_type);
1285 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1286 enum mlx4_net_trans_rule_id id);
1287 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1288
1289 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1290 int port, int qpn, u16 prio, u64 *reg_id);
1291
1292 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1293 int i, int val);
1294
1295 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1296
1297 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1298 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1299 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1300 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1301 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1302 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1303 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1304
1305 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1306 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1307
1308 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1309 int *slave_id);
1310 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1311 u8 *gid);
1312
1313 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1314 u32 max_range_qpn);
1315
1316 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1317
1318 struct mlx4_active_ports {
1319 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1320 };
1321 /* Returns a bitmap of the physical ports which are assigned to slave */
1322 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1323
1324 /* Returns the physical port that represents the virtual port of the slave, */
1325 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1326 /* mapping is returned. */
1327 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1328
1329 struct mlx4_slaves_pport {
1330 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1331 };
1332 /* Returns a bitmap of all slaves that are assigned to port. */
1333 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1334 int port);
1335
1336 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1337 /* the ports that are set in crit_ports. */
1338 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1339 struct mlx4_dev *dev,
1340 const struct mlx4_active_ports *crit_ports);
1341
1342 /* Returns the slave's virtual port that represents the physical port. */
1343 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1344
1345 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1346
1347 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1348 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1349 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1350 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1351 int enable);
1352 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1353 struct mlx4_mpt_entry ***mpt_entry);
1354 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1355 struct mlx4_mpt_entry **mpt_entry);
1356 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1357 u32 pdn);
1358 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1359 struct mlx4_mpt_entry *mpt_entry,
1360 u32 access);
1361 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1362 struct mlx4_mpt_entry **mpt_entry);
1363 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1364 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1365 u64 iova, u64 size, int npages,
1366 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1367
1368 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1369 u16 offset, u16 size, u8 *data);
1370
1371 /* Returns true if running in low memory profile (kdump kernel) */
1372 static inline bool mlx4_low_memory_profile(void)
1373 {
1374 return is_kdump_kernel();
1375 }
1376
1377 /* ACCESS REG commands */
1378 enum mlx4_access_reg_method {
1379 MLX4_ACCESS_REG_QUERY = 0x1,
1380 MLX4_ACCESS_REG_WRITE = 0x2,
1381 };
1382
1383 /* ACCESS PTYS Reg command */
1384 enum mlx4_ptys_proto {
1385 MLX4_PTYS_IB = 1<<0,
1386 MLX4_PTYS_EN = 1<<2,
1387 };
1388
1389 struct mlx4_ptys_reg {
1390 u8 resrvd1;
1391 u8 local_port;
1392 u8 resrvd2;
1393 u8 proto_mask;
1394 __be32 resrvd3[2];
1395 __be32 eth_proto_cap;
1396 __be16 ib_width_cap;
1397 __be16 ib_speed_cap;
1398 __be32 resrvd4;
1399 __be32 eth_proto_admin;
1400 __be16 ib_width_admin;
1401 __be16 ib_speed_admin;
1402 __be32 resrvd5;
1403 __be32 eth_proto_oper;
1404 __be16 ib_width_oper;
1405 __be16 ib_speed_oper;
1406 __be32 resrvd6;
1407 __be32 eth_proto_lp_adv;
1408 } __packed;
1409
1410 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1411 enum mlx4_access_reg_method method,
1412 struct mlx4_ptys_reg *ptys_reg);
1413
1414 #endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
This page took 0.059847 seconds and 6 git commands to generate.