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net/mlx5e: Fix checksum handling for non-stripped vlan packets
[deliverable/linux.git] / include / linux / mlx5 / device.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #else
45 #error Host endianness not defined
46 #endif
47
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68 /* insert a value to a struct */
69 #define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
75 } while (0)
76
77 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83 } while (0)
84
85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87 __mlx5_mask(typ, fld))
88
89 #define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93 })
94
95 #define MLX5_SET64(typ, p, fld, v) do { \
96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
99 } while (0)
100
101 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
102
103 #define MLX5_GET64_PR(typ, p, fld) ({ \
104 u64 ___t = MLX5_GET64(typ, p, fld); \
105 pr_debug(#fld " = 0x%llx\n", ___t); \
106 ___t; \
107 })
108
109 /* Big endian getters */
110 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
111 __mlx5_64_off(typ, fld)))
112
113 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
114 type_t tmp; \
115 switch (sizeof(tmp)) { \
116 case sizeof(u8): \
117 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
118 break; \
119 case sizeof(u16): \
120 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
121 break; \
122 case sizeof(u32): \
123 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
124 break; \
125 case sizeof(u64): \
126 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
127 break; \
128 } \
129 tmp; \
130 })
131
132 enum {
133 MLX5_MAX_COMMANDS = 32,
134 MLX5_CMD_DATA_BLOCK_SIZE = 512,
135 MLX5_PCI_CMD_XPORT = 7,
136 MLX5_MKEY_BSF_OCTO_SIZE = 4,
137 MLX5_MAX_PSVS = 4,
138 };
139
140 enum {
141 MLX5_EXTENDED_UD_AV = 0x80000000,
142 };
143
144 enum {
145 MLX5_CQ_STATE_ARMED = 9,
146 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
147 MLX5_CQ_STATE_FIRED = 0xa,
148 };
149
150 enum {
151 MLX5_STAT_RATE_OFFSET = 5,
152 };
153
154 enum {
155 MLX5_INLINE_SEG = 0x80000000,
156 };
157
158 enum {
159 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
160 };
161
162 enum {
163 MLX5_MIN_PKEY_TABLE_SIZE = 128,
164 MLX5_MAX_LOG_PKEY_TABLE = 5,
165 };
166
167 enum {
168 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
169 };
170
171 enum {
172 MLX5_PFAULT_SUBTYPE_WQE = 0,
173 MLX5_PFAULT_SUBTYPE_RDMA = 1,
174 };
175
176 enum {
177 MLX5_PERM_LOCAL_READ = 1 << 2,
178 MLX5_PERM_LOCAL_WRITE = 1 << 3,
179 MLX5_PERM_REMOTE_READ = 1 << 4,
180 MLX5_PERM_REMOTE_WRITE = 1 << 5,
181 MLX5_PERM_ATOMIC = 1 << 6,
182 MLX5_PERM_UMR_EN = 1 << 7,
183 };
184
185 enum {
186 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
187 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
188 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
189 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
190 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
191 };
192
193 enum {
194 MLX5_ACCESS_MODE_PA = 0,
195 MLX5_ACCESS_MODE_MTT = 1,
196 MLX5_ACCESS_MODE_KLM = 2
197 };
198
199 enum {
200 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
201 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
202 MLX5_MKEY_BSF_EN = 1 << 30,
203 MLX5_MKEY_LEN64 = 1 << 31,
204 };
205
206 enum {
207 MLX5_EN_RD = (u64)1,
208 MLX5_EN_WR = (u64)2
209 };
210
211 enum {
212 MLX5_BF_REGS_PER_PAGE = 4,
213 MLX5_MAX_UAR_PAGES = 1 << 8,
214 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
215 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
216 };
217
218 enum {
219 MLX5_MKEY_MASK_LEN = 1ull << 0,
220 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
221 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
222 MLX5_MKEY_MASK_PD = 1ull << 7,
223 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
224 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
225 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
226 MLX5_MKEY_MASK_KEY = 1ull << 13,
227 MLX5_MKEY_MASK_QPN = 1ull << 14,
228 MLX5_MKEY_MASK_LR = 1ull << 17,
229 MLX5_MKEY_MASK_LW = 1ull << 18,
230 MLX5_MKEY_MASK_RR = 1ull << 19,
231 MLX5_MKEY_MASK_RW = 1ull << 20,
232 MLX5_MKEY_MASK_A = 1ull << 21,
233 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
234 MLX5_MKEY_MASK_FREE = 1ull << 29,
235 };
236
237 enum {
238 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
239
240 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
241 MLX5_UMR_CHECK_FREE = (2 << 5),
242
243 MLX5_UMR_INLINE = (1 << 7),
244 };
245
246 #define MLX5_UMR_MTT_ALIGNMENT 0x40
247 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
248 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
249
250 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
251
252 enum {
253 MLX5_EVENT_QUEUE_TYPE_QP = 0,
254 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
255 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
256 };
257
258 enum mlx5_event {
259 MLX5_EVENT_TYPE_COMP = 0x0,
260
261 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
262 MLX5_EVENT_TYPE_COMM_EST = 0x02,
263 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
264 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
265 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
266
267 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
268 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
269 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
270 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
271 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
272 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
273
274 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
275 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
276 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
277 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
278
279 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
280 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
281
282 MLX5_EVENT_TYPE_CMD = 0x0a,
283 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
284
285 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
286 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
287 };
288
289 enum {
290 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
291 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
292 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
293 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
294 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
295 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
296 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
297 };
298
299 enum {
300 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
301 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
302 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
303 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
304 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
305 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
306 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
307 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
308 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
309 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
310 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
311 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
312 };
313
314 enum {
315 MLX5_ROCE_VERSION_1 = 0,
316 MLX5_ROCE_VERSION_2 = 2,
317 };
318
319 enum {
320 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
321 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
322 };
323
324 enum {
325 MLX5_ROCE_L3_TYPE_IPV4 = 0,
326 MLX5_ROCE_L3_TYPE_IPV6 = 1,
327 };
328
329 enum {
330 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
331 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
332 };
333
334 enum {
335 MLX5_OPCODE_NOP = 0x00,
336 MLX5_OPCODE_SEND_INVAL = 0x01,
337 MLX5_OPCODE_RDMA_WRITE = 0x08,
338 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
339 MLX5_OPCODE_SEND = 0x0a,
340 MLX5_OPCODE_SEND_IMM = 0x0b,
341 MLX5_OPCODE_LSO = 0x0e,
342 MLX5_OPCODE_RDMA_READ = 0x10,
343 MLX5_OPCODE_ATOMIC_CS = 0x11,
344 MLX5_OPCODE_ATOMIC_FA = 0x12,
345 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
346 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
347 MLX5_OPCODE_BIND_MW = 0x18,
348 MLX5_OPCODE_CONFIG_CMD = 0x1f,
349
350 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
351 MLX5_RECV_OPCODE_SEND = 0x01,
352 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
353 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
354
355 MLX5_CQE_OPCODE_ERROR = 0x1e,
356 MLX5_CQE_OPCODE_RESIZE = 0x16,
357
358 MLX5_OPCODE_SET_PSV = 0x20,
359 MLX5_OPCODE_GET_PSV = 0x21,
360 MLX5_OPCODE_CHECK_PSV = 0x22,
361 MLX5_OPCODE_RGET_PSV = 0x26,
362 MLX5_OPCODE_RCHECK_PSV = 0x27,
363
364 MLX5_OPCODE_UMR = 0x25,
365
366 };
367
368 enum {
369 MLX5_SET_PORT_RESET_QKEY = 0,
370 MLX5_SET_PORT_GUID0 = 16,
371 MLX5_SET_PORT_NODE_GUID = 17,
372 MLX5_SET_PORT_SYS_GUID = 18,
373 MLX5_SET_PORT_GID_TABLE = 19,
374 MLX5_SET_PORT_PKEY_TABLE = 20,
375 };
376
377 enum {
378 MLX5_BW_NO_LIMIT = 0,
379 MLX5_100_MBPS_UNIT = 3,
380 MLX5_GBPS_UNIT = 4,
381 };
382
383 enum {
384 MLX5_MAX_PAGE_SHIFT = 31
385 };
386
387 enum {
388 MLX5_ADAPTER_PAGE_SHIFT = 12,
389 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
390 };
391
392 enum {
393 MLX5_CAP_OFF_CMDIF_CSUM = 46,
394 };
395
396 struct mlx5_inbox_hdr {
397 __be16 opcode;
398 u8 rsvd[4];
399 __be16 opmod;
400 };
401
402 struct mlx5_outbox_hdr {
403 u8 status;
404 u8 rsvd[3];
405 __be32 syndrome;
406 };
407
408 struct mlx5_cmd_query_adapter_mbox_in {
409 struct mlx5_inbox_hdr hdr;
410 u8 rsvd[8];
411 };
412
413 struct mlx5_cmd_query_adapter_mbox_out {
414 struct mlx5_outbox_hdr hdr;
415 u8 rsvd0[24];
416 u8 intapin;
417 u8 rsvd1[13];
418 __be16 vsd_vendor_id;
419 u8 vsd[208];
420 u8 vsd_psid[16];
421 };
422
423 enum mlx5_odp_transport_cap_bits {
424 MLX5_ODP_SUPPORT_SEND = 1 << 31,
425 MLX5_ODP_SUPPORT_RECV = 1 << 30,
426 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
427 MLX5_ODP_SUPPORT_READ = 1 << 28,
428 };
429
430 struct mlx5_odp_caps {
431 char reserved[0x10];
432 struct {
433 __be32 rc_odp_caps;
434 __be32 uc_odp_caps;
435 __be32 ud_odp_caps;
436 } per_transport_caps;
437 char reserved2[0xe4];
438 };
439
440 struct mlx5_cmd_init_hca_mbox_in {
441 struct mlx5_inbox_hdr hdr;
442 u8 rsvd0[2];
443 __be16 profile;
444 u8 rsvd1[4];
445 };
446
447 struct mlx5_cmd_init_hca_mbox_out {
448 struct mlx5_outbox_hdr hdr;
449 u8 rsvd[8];
450 };
451
452 struct mlx5_cmd_teardown_hca_mbox_in {
453 struct mlx5_inbox_hdr hdr;
454 u8 rsvd0[2];
455 __be16 profile;
456 u8 rsvd1[4];
457 };
458
459 struct mlx5_cmd_teardown_hca_mbox_out {
460 struct mlx5_outbox_hdr hdr;
461 u8 rsvd[8];
462 };
463
464 struct mlx5_cmd_layout {
465 u8 type;
466 u8 rsvd0[3];
467 __be32 inlen;
468 __be64 in_ptr;
469 __be32 in[4];
470 __be32 out[4];
471 __be64 out_ptr;
472 __be32 outlen;
473 u8 token;
474 u8 sig;
475 u8 rsvd1;
476 u8 status_own;
477 };
478
479
480 struct health_buffer {
481 __be32 assert_var[5];
482 __be32 rsvd0[3];
483 __be32 assert_exit_ptr;
484 __be32 assert_callra;
485 __be32 rsvd1[2];
486 __be32 fw_ver;
487 __be32 hw_id;
488 __be32 rsvd2;
489 u8 irisc_index;
490 u8 synd;
491 __be16 ext_synd;
492 };
493
494 struct mlx5_init_seg {
495 __be32 fw_rev;
496 __be32 cmdif_rev_fw_sub;
497 __be32 rsvd0[2];
498 __be32 cmdq_addr_h;
499 __be32 cmdq_addr_l_sz;
500 __be32 cmd_dbell;
501 __be32 rsvd1[120];
502 __be32 initializing;
503 struct health_buffer health;
504 __be32 rsvd2[880];
505 __be32 internal_timer_h;
506 __be32 internal_timer_l;
507 __be32 rsvd3[2];
508 __be32 health_counter;
509 __be32 rsvd4[1019];
510 __be64 ieee1588_clk;
511 __be32 ieee1588_clk_type;
512 __be32 clr_intx;
513 };
514
515 struct mlx5_eqe_comp {
516 __be32 reserved[6];
517 __be32 cqn;
518 };
519
520 struct mlx5_eqe_qp_srq {
521 __be32 reserved1[5];
522 u8 type;
523 u8 reserved2[3];
524 __be32 qp_srq_n;
525 };
526
527 struct mlx5_eqe_cq_err {
528 __be32 cqn;
529 u8 reserved1[7];
530 u8 syndrome;
531 };
532
533 struct mlx5_eqe_port_state {
534 u8 reserved0[8];
535 u8 port;
536 };
537
538 struct mlx5_eqe_gpio {
539 __be32 reserved0[2];
540 __be64 gpio_event;
541 };
542
543 struct mlx5_eqe_congestion {
544 u8 type;
545 u8 rsvd0;
546 u8 congestion_level;
547 };
548
549 struct mlx5_eqe_stall_vl {
550 u8 rsvd0[3];
551 u8 port_vl;
552 };
553
554 struct mlx5_eqe_cmd {
555 __be32 vector;
556 __be32 rsvd[6];
557 };
558
559 struct mlx5_eqe_page_req {
560 u8 rsvd0[2];
561 __be16 func_id;
562 __be32 num_pages;
563 __be32 rsvd1[5];
564 };
565
566 struct mlx5_eqe_page_fault {
567 __be32 bytes_committed;
568 union {
569 struct {
570 u16 reserved1;
571 __be16 wqe_index;
572 u16 reserved2;
573 __be16 packet_length;
574 u8 reserved3[12];
575 } __packed wqe;
576 struct {
577 __be32 r_key;
578 u16 reserved1;
579 __be16 packet_length;
580 __be32 rdma_op_len;
581 __be64 rdma_va;
582 } __packed rdma;
583 } __packed;
584 __be32 flags_qpn;
585 } __packed;
586
587 struct mlx5_eqe_vport_change {
588 u8 rsvd0[2];
589 __be16 vport_num;
590 __be32 rsvd1[6];
591 } __packed;
592
593 union ev_data {
594 __be32 raw[7];
595 struct mlx5_eqe_cmd cmd;
596 struct mlx5_eqe_comp comp;
597 struct mlx5_eqe_qp_srq qp_srq;
598 struct mlx5_eqe_cq_err cq_err;
599 struct mlx5_eqe_port_state port;
600 struct mlx5_eqe_gpio gpio;
601 struct mlx5_eqe_congestion cong;
602 struct mlx5_eqe_stall_vl stall_vl;
603 struct mlx5_eqe_page_req req_pages;
604 struct mlx5_eqe_page_fault page_fault;
605 struct mlx5_eqe_vport_change vport_change;
606 } __packed;
607
608 struct mlx5_eqe {
609 u8 rsvd0;
610 u8 type;
611 u8 rsvd1;
612 u8 sub_type;
613 __be32 rsvd2[7];
614 union ev_data data;
615 __be16 rsvd3;
616 u8 signature;
617 u8 owner;
618 } __packed;
619
620 struct mlx5_cmd_prot_block {
621 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
622 u8 rsvd0[48];
623 __be64 next;
624 __be32 block_num;
625 u8 rsvd1;
626 u8 token;
627 u8 ctrl_sig;
628 u8 sig;
629 };
630
631 enum {
632 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
633 };
634
635 struct mlx5_err_cqe {
636 u8 rsvd0[32];
637 __be32 srqn;
638 u8 rsvd1[18];
639 u8 vendor_err_synd;
640 u8 syndrome;
641 __be32 s_wqe_opcode_qpn;
642 __be16 wqe_counter;
643 u8 signature;
644 u8 op_own;
645 };
646
647 struct mlx5_cqe64 {
648 u8 outer_l3_tunneled;
649 u8 rsvd0;
650 __be16 wqe_id;
651 u8 lro_tcppsh_abort_dupack;
652 u8 lro_min_ttl;
653 __be16 lro_tcp_win;
654 __be32 lro_ack_seq_num;
655 __be32 rss_hash_result;
656 u8 rss_hash_type;
657 u8 ml_path;
658 u8 rsvd20[2];
659 __be16 check_sum;
660 __be16 slid;
661 __be32 flags_rqpn;
662 u8 hds_ip_ext;
663 u8 l4_l3_hdr_type;
664 __be16 vlan_info;
665 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
666 __be32 imm_inval_pkey;
667 u8 rsvd40[4];
668 __be32 byte_cnt;
669 __be32 timestamp_h;
670 __be32 timestamp_l;
671 __be32 sop_drop_qpn;
672 __be16 wqe_counter;
673 u8 signature;
674 u8 op_own;
675 };
676
677 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
678 {
679 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
680 }
681
682 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
683 {
684 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
685 }
686
687 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
688 {
689 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
690 }
691
692 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
693 {
694 return cqe->outer_l3_tunneled & 0x1;
695 }
696
697 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
698 {
699 return !!(cqe->l4_l3_hdr_type & 0x1);
700 }
701
702 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
703 {
704 u32 hi, lo;
705
706 hi = be32_to_cpu(cqe->timestamp_h);
707 lo = be32_to_cpu(cqe->timestamp_l);
708
709 return (u64)lo | ((u64)hi << 32);
710 }
711
712 struct mpwrq_cqe_bc {
713 __be16 filler_consumed_strides;
714 __be16 byte_cnt;
715 };
716
717 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
718 {
719 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
720
721 return be16_to_cpu(bc->byte_cnt);
722 }
723
724 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
725 {
726 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
727 }
728
729 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
730 {
731 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
732
733 return mpwrq_get_cqe_bc_consumed_strides(bc);
734 }
735
736 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
737 {
738 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
739
740 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
741 }
742
743 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
744 {
745 return be16_to_cpu(cqe->wqe_counter);
746 }
747
748 enum {
749 CQE_L4_HDR_TYPE_NONE = 0x0,
750 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
751 CQE_L4_HDR_TYPE_UDP = 0x2,
752 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
753 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
754 };
755
756 enum {
757 CQE_RSS_HTYPE_IP = 0x3 << 6,
758 CQE_RSS_HTYPE_L4 = 0x3 << 2,
759 };
760
761 enum {
762 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
763 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
764 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
765 };
766
767 enum {
768 CQE_L2_OK = 1 << 0,
769 CQE_L3_OK = 1 << 1,
770 CQE_L4_OK = 1 << 2,
771 };
772
773 struct mlx5_sig_err_cqe {
774 u8 rsvd0[16];
775 __be32 expected_trans_sig;
776 __be32 actual_trans_sig;
777 __be32 expected_reftag;
778 __be32 actual_reftag;
779 __be16 syndrome;
780 u8 rsvd22[2];
781 __be32 mkey;
782 __be64 err_offset;
783 u8 rsvd30[8];
784 __be32 qpn;
785 u8 rsvd38[2];
786 u8 signature;
787 u8 op_own;
788 };
789
790 struct mlx5_wqe_srq_next_seg {
791 u8 rsvd0[2];
792 __be16 next_wqe_index;
793 u8 signature;
794 u8 rsvd1[11];
795 };
796
797 union mlx5_ext_cqe {
798 struct ib_grh grh;
799 u8 inl[64];
800 };
801
802 struct mlx5_cqe128 {
803 union mlx5_ext_cqe inl_grh;
804 struct mlx5_cqe64 cqe64;
805 };
806
807 struct mlx5_srq_ctx {
808 u8 state_log_sz;
809 u8 rsvd0[3];
810 __be32 flags_xrcd;
811 __be32 pgoff_cqn;
812 u8 rsvd1[4];
813 u8 log_pg_sz;
814 u8 rsvd2[7];
815 __be32 pd;
816 __be16 lwm;
817 __be16 wqe_cnt;
818 u8 rsvd3[8];
819 __be64 db_record;
820 };
821
822 struct mlx5_create_srq_mbox_in {
823 struct mlx5_inbox_hdr hdr;
824 __be32 input_srqn;
825 u8 rsvd0[4];
826 struct mlx5_srq_ctx ctx;
827 u8 rsvd1[208];
828 __be64 pas[0];
829 };
830
831 struct mlx5_create_srq_mbox_out {
832 struct mlx5_outbox_hdr hdr;
833 __be32 srqn;
834 u8 rsvd[4];
835 };
836
837 struct mlx5_destroy_srq_mbox_in {
838 struct mlx5_inbox_hdr hdr;
839 __be32 srqn;
840 u8 rsvd[4];
841 };
842
843 struct mlx5_destroy_srq_mbox_out {
844 struct mlx5_outbox_hdr hdr;
845 u8 rsvd[8];
846 };
847
848 struct mlx5_query_srq_mbox_in {
849 struct mlx5_inbox_hdr hdr;
850 __be32 srqn;
851 u8 rsvd0[4];
852 };
853
854 struct mlx5_query_srq_mbox_out {
855 struct mlx5_outbox_hdr hdr;
856 u8 rsvd0[8];
857 struct mlx5_srq_ctx ctx;
858 u8 rsvd1[32];
859 __be64 pas[0];
860 };
861
862 struct mlx5_arm_srq_mbox_in {
863 struct mlx5_inbox_hdr hdr;
864 __be32 srqn;
865 __be16 rsvd;
866 __be16 lwm;
867 };
868
869 struct mlx5_arm_srq_mbox_out {
870 struct mlx5_outbox_hdr hdr;
871 u8 rsvd[8];
872 };
873
874 struct mlx5_cq_context {
875 u8 status;
876 u8 cqe_sz_flags;
877 u8 st;
878 u8 rsvd3;
879 u8 rsvd4[6];
880 __be16 page_offset;
881 __be32 log_sz_usr_page;
882 __be16 cq_period;
883 __be16 cq_max_count;
884 __be16 rsvd20;
885 __be16 c_eqn;
886 u8 log_pg_sz;
887 u8 rsvd25[7];
888 __be32 last_notified_index;
889 __be32 solicit_producer_index;
890 __be32 consumer_counter;
891 __be32 producer_counter;
892 u8 rsvd48[8];
893 __be64 db_record_addr;
894 };
895
896 struct mlx5_create_cq_mbox_in {
897 struct mlx5_inbox_hdr hdr;
898 __be32 input_cqn;
899 u8 rsvdx[4];
900 struct mlx5_cq_context ctx;
901 u8 rsvd6[192];
902 __be64 pas[0];
903 };
904
905 struct mlx5_create_cq_mbox_out {
906 struct mlx5_outbox_hdr hdr;
907 __be32 cqn;
908 u8 rsvd0[4];
909 };
910
911 struct mlx5_destroy_cq_mbox_in {
912 struct mlx5_inbox_hdr hdr;
913 __be32 cqn;
914 u8 rsvd0[4];
915 };
916
917 struct mlx5_destroy_cq_mbox_out {
918 struct mlx5_outbox_hdr hdr;
919 u8 rsvd0[8];
920 };
921
922 struct mlx5_query_cq_mbox_in {
923 struct mlx5_inbox_hdr hdr;
924 __be32 cqn;
925 u8 rsvd0[4];
926 };
927
928 struct mlx5_query_cq_mbox_out {
929 struct mlx5_outbox_hdr hdr;
930 u8 rsvd0[8];
931 struct mlx5_cq_context ctx;
932 u8 rsvd6[16];
933 __be64 pas[0];
934 };
935
936 struct mlx5_modify_cq_mbox_in {
937 struct mlx5_inbox_hdr hdr;
938 __be32 cqn;
939 __be32 field_select;
940 struct mlx5_cq_context ctx;
941 u8 rsvd[192];
942 __be64 pas[0];
943 };
944
945 struct mlx5_modify_cq_mbox_out {
946 struct mlx5_outbox_hdr hdr;
947 u8 rsvd[8];
948 };
949
950 struct mlx5_enable_hca_mbox_in {
951 struct mlx5_inbox_hdr hdr;
952 u8 rsvd[8];
953 };
954
955 struct mlx5_enable_hca_mbox_out {
956 struct mlx5_outbox_hdr hdr;
957 u8 rsvd[8];
958 };
959
960 struct mlx5_disable_hca_mbox_in {
961 struct mlx5_inbox_hdr hdr;
962 u8 rsvd[8];
963 };
964
965 struct mlx5_disable_hca_mbox_out {
966 struct mlx5_outbox_hdr hdr;
967 u8 rsvd[8];
968 };
969
970 struct mlx5_eq_context {
971 u8 status;
972 u8 ec_oi;
973 u8 st;
974 u8 rsvd2[7];
975 __be16 page_pffset;
976 __be32 log_sz_usr_page;
977 u8 rsvd3[7];
978 u8 intr;
979 u8 log_page_size;
980 u8 rsvd4[15];
981 __be32 consumer_counter;
982 __be32 produser_counter;
983 u8 rsvd5[16];
984 };
985
986 struct mlx5_create_eq_mbox_in {
987 struct mlx5_inbox_hdr hdr;
988 u8 rsvd0[3];
989 u8 input_eqn;
990 u8 rsvd1[4];
991 struct mlx5_eq_context ctx;
992 u8 rsvd2[8];
993 __be64 events_mask;
994 u8 rsvd3[176];
995 __be64 pas[0];
996 };
997
998 struct mlx5_create_eq_mbox_out {
999 struct mlx5_outbox_hdr hdr;
1000 u8 rsvd0[3];
1001 u8 eq_number;
1002 u8 rsvd1[4];
1003 };
1004
1005 struct mlx5_destroy_eq_mbox_in {
1006 struct mlx5_inbox_hdr hdr;
1007 u8 rsvd0[3];
1008 u8 eqn;
1009 u8 rsvd1[4];
1010 };
1011
1012 struct mlx5_destroy_eq_mbox_out {
1013 struct mlx5_outbox_hdr hdr;
1014 u8 rsvd[8];
1015 };
1016
1017 struct mlx5_map_eq_mbox_in {
1018 struct mlx5_inbox_hdr hdr;
1019 __be64 mask;
1020 u8 mu;
1021 u8 rsvd0[2];
1022 u8 eqn;
1023 u8 rsvd1[24];
1024 };
1025
1026 struct mlx5_map_eq_mbox_out {
1027 struct mlx5_outbox_hdr hdr;
1028 u8 rsvd[8];
1029 };
1030
1031 struct mlx5_query_eq_mbox_in {
1032 struct mlx5_inbox_hdr hdr;
1033 u8 rsvd0[3];
1034 u8 eqn;
1035 u8 rsvd1[4];
1036 };
1037
1038 struct mlx5_query_eq_mbox_out {
1039 struct mlx5_outbox_hdr hdr;
1040 u8 rsvd[8];
1041 struct mlx5_eq_context ctx;
1042 };
1043
1044 enum {
1045 MLX5_MKEY_STATUS_FREE = 1 << 6,
1046 };
1047
1048 struct mlx5_mkey_seg {
1049 /* This is a two bit field occupying bits 31-30.
1050 * bit 31 is always 0,
1051 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
1052 */
1053 u8 status;
1054 u8 pcie_control;
1055 u8 flags;
1056 u8 version;
1057 __be32 qpn_mkey7_0;
1058 u8 rsvd1[4];
1059 __be32 flags_pd;
1060 __be64 start_addr;
1061 __be64 len;
1062 __be32 bsfs_octo_size;
1063 u8 rsvd2[16];
1064 __be32 xlt_oct_size;
1065 u8 rsvd3[3];
1066 u8 log2_page_size;
1067 u8 rsvd4[4];
1068 };
1069
1070 struct mlx5_query_special_ctxs_mbox_in {
1071 struct mlx5_inbox_hdr hdr;
1072 u8 rsvd[8];
1073 };
1074
1075 struct mlx5_query_special_ctxs_mbox_out {
1076 struct mlx5_outbox_hdr hdr;
1077 __be32 dump_fill_mkey;
1078 __be32 reserved_lkey;
1079 };
1080
1081 struct mlx5_create_mkey_mbox_in {
1082 struct mlx5_inbox_hdr hdr;
1083 __be32 input_mkey_index;
1084 __be32 flags;
1085 struct mlx5_mkey_seg seg;
1086 u8 rsvd1[16];
1087 __be32 xlat_oct_act_size;
1088 __be32 rsvd2;
1089 u8 rsvd3[168];
1090 __be64 pas[0];
1091 };
1092
1093 struct mlx5_create_mkey_mbox_out {
1094 struct mlx5_outbox_hdr hdr;
1095 __be32 mkey;
1096 u8 rsvd[4];
1097 };
1098
1099 struct mlx5_destroy_mkey_mbox_in {
1100 struct mlx5_inbox_hdr hdr;
1101 __be32 mkey;
1102 u8 rsvd[4];
1103 };
1104
1105 struct mlx5_destroy_mkey_mbox_out {
1106 struct mlx5_outbox_hdr hdr;
1107 u8 rsvd[8];
1108 };
1109
1110 struct mlx5_query_mkey_mbox_in {
1111 struct mlx5_inbox_hdr hdr;
1112 __be32 mkey;
1113 };
1114
1115 struct mlx5_query_mkey_mbox_out {
1116 struct mlx5_outbox_hdr hdr;
1117 __be64 pas[0];
1118 };
1119
1120 struct mlx5_modify_mkey_mbox_in {
1121 struct mlx5_inbox_hdr hdr;
1122 __be32 mkey;
1123 __be64 pas[0];
1124 };
1125
1126 struct mlx5_modify_mkey_mbox_out {
1127 struct mlx5_outbox_hdr hdr;
1128 u8 rsvd[8];
1129 };
1130
1131 struct mlx5_dump_mkey_mbox_in {
1132 struct mlx5_inbox_hdr hdr;
1133 };
1134
1135 struct mlx5_dump_mkey_mbox_out {
1136 struct mlx5_outbox_hdr hdr;
1137 __be32 mkey;
1138 };
1139
1140 struct mlx5_mad_ifc_mbox_in {
1141 struct mlx5_inbox_hdr hdr;
1142 __be16 remote_lid;
1143 u8 rsvd0;
1144 u8 port;
1145 u8 rsvd1[4];
1146 u8 data[256];
1147 };
1148
1149 struct mlx5_mad_ifc_mbox_out {
1150 struct mlx5_outbox_hdr hdr;
1151 u8 rsvd[8];
1152 u8 data[256];
1153 };
1154
1155 struct mlx5_access_reg_mbox_in {
1156 struct mlx5_inbox_hdr hdr;
1157 u8 rsvd0[2];
1158 __be16 register_id;
1159 __be32 arg;
1160 __be32 data[0];
1161 };
1162
1163 struct mlx5_access_reg_mbox_out {
1164 struct mlx5_outbox_hdr hdr;
1165 u8 rsvd[8];
1166 __be32 data[0];
1167 };
1168
1169 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1170
1171 enum {
1172 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1173 };
1174
1175 struct mlx5_allocate_psv_in {
1176 struct mlx5_inbox_hdr hdr;
1177 __be32 npsv_pd;
1178 __be32 rsvd_psv0;
1179 };
1180
1181 struct mlx5_allocate_psv_out {
1182 struct mlx5_outbox_hdr hdr;
1183 u8 rsvd[8];
1184 __be32 psv_idx[4];
1185 };
1186
1187 struct mlx5_destroy_psv_in {
1188 struct mlx5_inbox_hdr hdr;
1189 __be32 psv_number;
1190 u8 rsvd[4];
1191 };
1192
1193 struct mlx5_destroy_psv_out {
1194 struct mlx5_outbox_hdr hdr;
1195 u8 rsvd[8];
1196 };
1197
1198 #define MLX5_CMD_OP_MAX 0x920
1199
1200 enum {
1201 VPORT_STATE_DOWN = 0x0,
1202 VPORT_STATE_UP = 0x1,
1203 };
1204
1205 enum {
1206 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1207 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1208 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1209 };
1210
1211 enum {
1212 MLX5_L3_PROT_TYPE_IPV4 = 0,
1213 MLX5_L3_PROT_TYPE_IPV6 = 1,
1214 };
1215
1216 enum {
1217 MLX5_L4_PROT_TYPE_TCP = 0,
1218 MLX5_L4_PROT_TYPE_UDP = 1,
1219 };
1220
1221 enum {
1222 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1223 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1224 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1225 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1226 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1227 };
1228
1229 enum {
1230 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1231 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1232 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1233
1234 };
1235
1236 enum {
1237 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1238 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1239 };
1240
1241 enum {
1242 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1243 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1244 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1245 };
1246
1247 enum mlx5_list_type {
1248 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1249 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1250 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1251 };
1252
1253 enum {
1254 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1255 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1256 };
1257
1258 enum mlx5_wol_mode {
1259 MLX5_WOL_DISABLE = 0,
1260 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1261 MLX5_WOL_MAGIC = 1 << 2,
1262 MLX5_WOL_ARP = 1 << 3,
1263 MLX5_WOL_BROADCAST = 1 << 4,
1264 MLX5_WOL_MULTICAST = 1 << 5,
1265 MLX5_WOL_UNICAST = 1 << 6,
1266 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1267 };
1268
1269 /* MLX5 DEV CAPs */
1270
1271 /* TODO: EAT.ME */
1272 enum mlx5_cap_mode {
1273 HCA_CAP_OPMOD_GET_MAX = 0,
1274 HCA_CAP_OPMOD_GET_CUR = 1,
1275 };
1276
1277 enum mlx5_cap_type {
1278 MLX5_CAP_GENERAL = 0,
1279 MLX5_CAP_ETHERNET_OFFLOADS,
1280 MLX5_CAP_ODP,
1281 MLX5_CAP_ATOMIC,
1282 MLX5_CAP_ROCE,
1283 MLX5_CAP_IPOIB_OFFLOADS,
1284 MLX5_CAP_EOIB_OFFLOADS,
1285 MLX5_CAP_FLOW_TABLE,
1286 MLX5_CAP_ESWITCH_FLOW_TABLE,
1287 MLX5_CAP_ESWITCH,
1288 MLX5_CAP_RESERVED,
1289 MLX5_CAP_VECTOR_CALC,
1290 /* NUM OF CAP Types */
1291 MLX5_CAP_NUM
1292 };
1293
1294 /* GET Dev Caps macros */
1295 #define MLX5_CAP_GEN(mdev, cap) \
1296 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1297
1298 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1299 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1300
1301 #define MLX5_CAP_ETH(mdev, cap) \
1302 MLX5_GET(per_protocol_networking_offload_caps,\
1303 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1304
1305 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1306 MLX5_GET(per_protocol_networking_offload_caps,\
1307 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1308
1309 #define MLX5_CAP_ROCE(mdev, cap) \
1310 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1311
1312 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1313 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1314
1315 #define MLX5_CAP_ATOMIC(mdev, cap) \
1316 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1317
1318 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1319 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1320
1321 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1322 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1323
1324 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1325 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1326
1327 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1328 MLX5_GET(flow_table_eswitch_cap, \
1329 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1330
1331 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1332 MLX5_GET(flow_table_eswitch_cap, \
1333 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1334
1335 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1336 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1337
1338 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1339 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1340
1341 #define MLX5_CAP_ESW(mdev, cap) \
1342 MLX5_GET(e_switch_cap, \
1343 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1344
1345 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1346 MLX5_GET(e_switch_cap, \
1347 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1348
1349 #define MLX5_CAP_ODP(mdev, cap)\
1350 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1351
1352 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1353 MLX5_GET(vector_calc_cap, \
1354 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1355
1356 enum {
1357 MLX5_CMD_STAT_OK = 0x0,
1358 MLX5_CMD_STAT_INT_ERR = 0x1,
1359 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1360 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1361 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1362 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1363 MLX5_CMD_STAT_RES_BUSY = 0x6,
1364 MLX5_CMD_STAT_LIM_ERR = 0x8,
1365 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1366 MLX5_CMD_STAT_IX_ERR = 0xa,
1367 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1368 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1369 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1370 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1371 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1372 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1373 };
1374
1375 enum {
1376 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1377 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1378 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1379 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1380 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1381 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1382 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1383 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1384 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1385 };
1386
1387 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1388 {
1389 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1390 return 0;
1391 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1392 }
1393
1394 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1395 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1396 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1397 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1398 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1399 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1400
1401 #endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
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