include/linux/mlx5/driver.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DRIVER_H
  34 #define MLX5_DRIVER_H
  35
  36 #include <linux/kernel.h>
  37 #include <linux/completion.h>
  38 #include <linux/pci.h>
  39 #include <linux/spinlock_types.h>
  40 #include <linux/semaphore.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/radix-tree.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/interrupt.h>
  46
  47 #include <linux/mlx5/device.h>
  48 #include <linux/mlx5/doorbell.h>
  49 #include <linux/mlx5/srq.h>
  50
  51 enum {
  52         MLX5_RQ_BITMASK_VSD = 1 << 1,
  53 };
  54
  55 enum {
  56         MLX5_BOARD_ID_LEN = 64,
  57         MLX5_MAX_NAME_LEN = 16,
  58 };
  59
  60 enum {
  61         /* one minute for the sake of bringup. Generally, commands must always
  62          * complete and we may need to increase this timeout value
  63          */
  64         MLX5_CMD_TIMEOUT_MSEC   = 60 * 1000,
  65         MLX5_CMD_WQ_MAX_NAME    = 32,
  66 };
  67
  68 enum {
  69         CMD_OWNER_SW            = 0x0,
  70         CMD_OWNER_HW            = 0x1,
  71         CMD_STATUS_SUCCESS      = 0,
  72 };
  73
  74 enum mlx5_sqp_t {
  75         MLX5_SQP_SMI            = 0,
  76         MLX5_SQP_GSI            = 1,
  77         MLX5_SQP_IEEE_1588      = 2,
  78         MLX5_SQP_SNIFFER        = 3,
  79         MLX5_SQP_SYNC_UMR       = 4,
  80 };
  81
  82 enum {
  83         MLX5_MAX_PORTS  = 2,
  84 };
  85
  86 enum {
  87         MLX5_EQ_VEC_PAGES        = 0,
  88         MLX5_EQ_VEC_CMD          = 1,
  89         MLX5_EQ_VEC_ASYNC        = 2,
  90         MLX5_EQ_VEC_COMP_BASE,
  91 };
  92
  93 enum {
  94         MLX5_MAX_IRQ_NAME       = 32
  95 };
  96
  97 enum {
  98         MLX5_ATOMIC_MODE_IB_COMP        = 1 << 16,
  99         MLX5_ATOMIC_MODE_CX             = 2 << 16,
 100         MLX5_ATOMIC_MODE_8B             = 3 << 16,
 101         MLX5_ATOMIC_MODE_16B            = 4 << 16,
 102         MLX5_ATOMIC_MODE_32B            = 5 << 16,
 103         MLX5_ATOMIC_MODE_64B            = 6 << 16,
 104         MLX5_ATOMIC_MODE_128B           = 7 << 16,
 105         MLX5_ATOMIC_MODE_256B           = 8 << 16,
 106 };
 107
 108 enum {
 109         MLX5_REG_QETCR           = 0x4005,
 110         MLX5_REG_QTCT            = 0x400a,
 111         MLX5_REG_PCAP            = 0x5001,
 112         MLX5_REG_PMTU            = 0x5003,
 113         MLX5_REG_PTYS            = 0x5004,
 114         MLX5_REG_PAOS            = 0x5006,
 115         MLX5_REG_PFCC            = 0x5007,
 116         MLX5_REG_PPCNT           = 0x5008,
 117         MLX5_REG_PMAOS           = 0x5012,
 118         MLX5_REG_PUDE            = 0x5009,
 119         MLX5_REG_PMPE            = 0x5010,
 120         MLX5_REG_PELC            = 0x500e,
 121         MLX5_REG_PVLC            = 0x500f,
 122         MLX5_REG_PCMR            = 0x5041,
 123         MLX5_REG_PMLP            = 0x5002,
 124         MLX5_REG_NODE_DESC       = 0x6001,
 125         MLX5_REG_HOST_ENDIANNESS = 0x7004,
 126         MLX5_REG_MCIA            = 0x9014,
 127         MLX5_REG_MLCR            = 0x902b,
 128 };
 129
 130 enum {
 131         MLX5_ATOMIC_OPS_CMP_SWAP        = 1 << 0,
 132         MLX5_ATOMIC_OPS_FETCH_ADD       = 1 << 1,
 133 };
 134
 135 enum mlx5_page_fault_resume_flags {
 136         MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
 137         MLX5_PAGE_FAULT_RESUME_WRITE     = 1 << 1,
 138         MLX5_PAGE_FAULT_RESUME_RDMA      = 1 << 2,
 139         MLX5_PAGE_FAULT_RESUME_ERROR     = 1 << 7,
 140 };
 141
 142 enum dbg_rsc_type {
 143         MLX5_DBG_RSC_QP,
 144         MLX5_DBG_RSC_EQ,
 145         MLX5_DBG_RSC_CQ,
 146 };
 147
 148 struct mlx5_field_desc {
 149         struct dentry          *dent;
 150         int                     i;
 151 };
 152
 153 struct mlx5_rsc_debug {
 154         struct mlx5_core_dev   *dev;
 155         void                   *object;
 156         enum dbg_rsc_type       type;
 157         struct dentry          *root;
 158         struct mlx5_field_desc  fields[0];
 159 };
 160
 161 enum mlx5_dev_event {
 162         MLX5_DEV_EVENT_SYS_ERROR,
 163         MLX5_DEV_EVENT_PORT_UP,
 164         MLX5_DEV_EVENT_PORT_DOWN,
 165         MLX5_DEV_EVENT_PORT_INITIALIZED,
 166         MLX5_DEV_EVENT_LID_CHANGE,
 167         MLX5_DEV_EVENT_PKEY_CHANGE,
 168         MLX5_DEV_EVENT_GUID_CHANGE,
 169         MLX5_DEV_EVENT_CLIENT_REREG,
 170 };
 171
 172 enum mlx5_port_status {
 173         MLX5_PORT_UP        = 1,
 174         MLX5_PORT_DOWN      = 2,
 175 };
 176
 177 struct mlx5_uuar_info {
 178         struct mlx5_uar        *uars;
 179         int                     num_uars;
 180         int                     num_low_latency_uuars;
 181         unsigned long          *bitmap;
 182         unsigned int           *count;
 183         struct mlx5_bf         *bfs;
 184
 185         /*
 186          * protect uuar allocation data structs
 187          */
 188         struct mutex            lock;
 189         u32                     ver;
 190 };
 191
 192 struct mlx5_bf {
 193         void __iomem           *reg;
 194         void __iomem           *regreg;
 195         int                     buf_size;
 196         struct mlx5_uar        *uar;
 197         unsigned long           offset;
 198         int                     need_lock;
 199         /* protect blue flame buffer selection when needed
 200          */
 201         spinlock_t              lock;
 202
 203         /* serialize 64 bit writes when done as two 32 bit accesses
 204          */
 205         spinlock_t              lock32;
 206         int                     uuarn;
 207 };
 208
 209 struct mlx5_cmd_first {
 210         __be32          data[4];
 211 };
 212
 213 struct mlx5_cmd_msg {
 214         struct list_head                list;
 215         struct cache_ent               *cache;
 216         u32                             len;
 217         struct mlx5_cmd_first           first;
 218         struct mlx5_cmd_mailbox        *next;
 219 };
 220
 221 struct mlx5_cmd_debug {
 222         struct dentry          *dbg_root;
 223         struct dentry          *dbg_in;
 224         struct dentry          *dbg_out;
 225         struct dentry          *dbg_outlen;
 226         struct dentry          *dbg_status;
 227         struct dentry          *dbg_run;
 228         void                   *in_msg;
 229         void                   *out_msg;
 230         u8                      status;
 231         u16                     inlen;
 232         u16                     outlen;
 233 };
 234
 235 struct cache_ent {
 236         /* protect block chain allocations
 237          */
 238         spinlock_t              lock;
 239         struct list_head        head;
 240 };
 241
 242 struct cmd_msg_cache {
 243         struct cache_ent        large;
 244         struct cache_ent        med;
 245
 246 };
 247
 248 struct mlx5_cmd_stats {
 249         u64             sum;
 250         u64             n;
 251         struct dentry  *root;
 252         struct dentry  *avg;
 253         struct dentry  *count;
 254         /* protect command average calculations */
 255         spinlock_t      lock;
 256 };
 257
 258 struct mlx5_cmd {
 259         void           *cmd_alloc_buf;
 260         dma_addr_t      alloc_dma;
 261         int             alloc_size;
 262         void           *cmd_buf;
 263         dma_addr_t      dma;
 264         u16             cmdif_rev;
 265         u8              log_sz;
 266         u8              log_stride;
 267         int             max_reg_cmds;
 268         int             events;
 269         u32 __iomem    *vector;
 270
 271         /* protect command queue allocations
 272          */
 273         spinlock_t      alloc_lock;
 274
 275         /* protect token allocations
 276          */
 277         spinlock_t      token_lock;
 278         u8              token;
 279         unsigned long   bitmask;
 280         char            wq_name[MLX5_CMD_WQ_MAX_NAME];
 281         struct workqueue_struct *wq;
 282         struct semaphore sem;
 283         struct semaphore pages_sem;
 284         int     mode;
 285         struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
 286         struct pci_pool *pool;
 287         struct mlx5_cmd_debug dbg;
 288         struct cmd_msg_cache cache;
 289         int checksum_disabled;
 290         struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
 291 };
 292
 293 struct mlx5_port_caps {
 294         int     gid_table_len;
 295         int     pkey_table_len;
 296         u8      ext_port_cap;
 297 };
 298
 299 struct mlx5_cmd_mailbox {
 300         void           *buf;
 301         dma_addr_t      dma;
 302         struct mlx5_cmd_mailbox *next;
 303 };
 304
 305 struct mlx5_buf_list {
 306         void                   *buf;
 307         dma_addr_t              map;
 308 };
 309
 310 struct mlx5_buf {
 311         struct mlx5_buf_list    direct;
 312         int                     npages;
 313         int                     size;
 314         u8                      page_shift;
 315 };
 316
 317 struct mlx5_eq_tasklet {
 318         struct list_head list;
 319         struct list_head process_list;
 320         struct tasklet_struct task;
 321         /* lock on completion tasklet list */
 322         spinlock_t lock;
 323 };
 324
 325 struct mlx5_eq {
 326         struct mlx5_core_dev   *dev;
 327         __be32 __iomem         *doorbell;
 328         u32                     cons_index;
 329         struct mlx5_buf         buf;
 330         int                     size;
 331         unsigned int            irqn;
 332         u8                      eqn;
 333         int                     nent;
 334         u64                     mask;
 335         struct list_head        list;
 336         int                     index;
 337         struct mlx5_rsc_debug   *dbg;
 338         struct mlx5_eq_tasklet  tasklet_ctx;
 339 };
 340
 341 struct mlx5_core_psv {
 342         u32     psv_idx;
 343         struct psv_layout {
 344                 u32     pd;
 345                 u16     syndrome;
 346                 u16     reserved;
 347                 u16     bg;
 348                 u16     app_tag;
 349                 u32     ref_tag;
 350         } psv;
 351 };
 352
 353 struct mlx5_core_sig_ctx {
 354         struct mlx5_core_psv    psv_memory;
 355         struct mlx5_core_psv    psv_wire;
 356         struct ib_sig_err       err_item;
 357         bool                    sig_status_checked;
 358         bool                    sig_err_exists;
 359         u32                     sigerr_count;
 360 };
 361
 362 struct mlx5_core_mkey {
 363         u64                     iova;
 364         u64                     size;
 365         u32                     key;
 366         u32                     pd;
 367 };
 368
 369 enum mlx5_res_type {
 370         MLX5_RES_QP     = MLX5_EVENT_QUEUE_TYPE_QP,
 371         MLX5_RES_RQ     = MLX5_EVENT_QUEUE_TYPE_RQ,
 372         MLX5_RES_SQ     = MLX5_EVENT_QUEUE_TYPE_SQ,
 373         MLX5_RES_SRQ    = 3,
 374         MLX5_RES_XSRQ   = 4,
 375 };
 376
 377 struct mlx5_core_rsc_common {
 378         enum mlx5_res_type      res;
 379         atomic_t                refcount;
 380         struct completion       free;
 381 };
 382
 383 struct mlx5_core_srq {
 384         struct mlx5_core_rsc_common     common; /* must be first */
 385         u32             srqn;
 386         int             max;
 387         int             max_gs;
 388         int             max_avail_gather;
 389         int             wqe_shift;
 390         void (*event)   (struct mlx5_core_srq *, enum mlx5_event);
 391
 392         atomic_t                refcount;
 393         struct completion       free;
 394 };
 395
 396 struct mlx5_eq_table {
 397         void __iomem           *update_ci;
 398         void __iomem           *update_arm_ci;
 399         struct list_head        comp_eqs_list;
 400         struct mlx5_eq          pages_eq;
 401         struct mlx5_eq          async_eq;
 402         struct mlx5_eq          cmd_eq;
 403         int                     num_comp_vectors;
 404         /* protect EQs list
 405          */
 406         spinlock_t              lock;
 407 };
 408
 409 struct mlx5_uar {
 410         u32                     index;
 411         struct list_head        bf_list;
 412         unsigned                free_bf_bmap;
 413         void __iomem           *bf_map;
 414         void __iomem           *map;
 415 };
 416
 417
 418 struct mlx5_core_health {
 419         struct health_buffer __iomem   *health;
 420         __be32 __iomem                 *health_counter;
 421         struct timer_list               timer;
 422         u32                             prev;
 423         int                             miss_counter;
 424         bool                            sick;
 425         struct workqueue_struct        *wq;
 426         struct work_struct              work;
 427 };
 428
 429 struct mlx5_cq_table {
 430         /* protect radix tree
 431          */
 432         spinlock_t              lock;
 433         struct radix_tree_root  tree;
 434 };
 435
 436 struct mlx5_qp_table {
 437         /* protect radix tree
 438          */
 439         spinlock_t              lock;
 440         struct radix_tree_root  tree;
 441 };
 442
 443 struct mlx5_srq_table {
 444         /* protect radix tree
 445          */
 446         spinlock_t              lock;
 447         struct radix_tree_root  tree;
 448 };
 449
 450 struct mlx5_mkey_table {
 451         /* protect radix tree
 452          */
 453         rwlock_t                lock;
 454         struct radix_tree_root  tree;
 455 };
 456
 457 struct mlx5_vf_context {
 458         int     enabled;
 459 };
 460
 461 struct mlx5_core_sriov {
 462         struct mlx5_vf_context  *vfs_ctx;
 463         int                     num_vfs;
 464         int                     enabled_vfs;
 465 };
 466
 467 struct mlx5_irq_info {
 468         cpumask_var_t mask;
 469         char name[MLX5_MAX_IRQ_NAME];
 470 };
 471
 472 struct mlx5_fc_stats {
 473         struct rb_root counters;
 474         struct list_head addlist;
 475         /* protect addlist add/splice operations */
 476         spinlock_t addlist_lock;
 477
 478         struct workqueue_struct *wq;
 479         struct delayed_work work;
 480         unsigned long next_query;
 481 };
 482
 483 struct mlx5_eswitch;
 484
 485 struct mlx5_rl_entry {
 486         u32                     rate;
 487         u16                     index;
 488         u16                     refcount;
 489 };
 490
 491 struct mlx5_rl_table {
 492         /* protect rate limit table */
 493         struct mutex            rl_lock;
 494         u16                     max_size;
 495         u32                     max_rate;
 496         u32                     min_rate;
 497         struct mlx5_rl_entry   *rl_entry;
 498 };
 499
 500 struct mlx5_priv {
 501         char                    name[MLX5_MAX_NAME_LEN];
 502         struct mlx5_eq_table    eq_table;
 503         struct msix_entry       *msix_arr;
 504         struct mlx5_irq_info    *irq_info;
 505         struct mlx5_uuar_info   uuari;
 506         MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
 507
 508         /* pages stuff */
 509         struct workqueue_struct *pg_wq;
 510         struct rb_root          page_root;
 511         int                     fw_pages;
 512         atomic_t                reg_pages;
 513         struct list_head        free_list;
 514         int                     vfs_pages;
 515
 516         struct mlx5_core_health health;
 517
 518         struct mlx5_srq_table   srq_table;
 519
 520         /* start: qp staff */
 521         struct mlx5_qp_table    qp_table;
 522         struct dentry          *qp_debugfs;
 523         struct dentry          *eq_debugfs;
 524         struct dentry          *cq_debugfs;
 525         struct dentry          *cmdif_debugfs;
 526         /* end: qp staff */
 527
 528         /* start: cq staff */
 529         struct mlx5_cq_table    cq_table;
 530         /* end: cq staff */
 531
 532         /* start: mkey staff */
 533         struct mlx5_mkey_table  mkey_table;
 534         /* end: mkey staff */
 535
 536         /* start: alloc staff */
 537         /* protect buffer alocation according to numa node */
 538         struct mutex            alloc_mutex;
 539         int                     numa_node;
 540
 541         struct mutex            pgdir_mutex;
 542         struct list_head        pgdir_list;
 543         /* end: alloc staff */
 544         struct dentry          *dbg_root;
 545
 546         /* protect mkey key part */
 547         spinlock_t              mkey_lock;
 548         u8                      mkey_key;
 549
 550         struct list_head        dev_list;
 551         struct list_head        ctx_list;
 552         spinlock_t              ctx_lock;
 553
 554         struct mlx5_flow_steering *steering;
 555         struct mlx5_eswitch     *eswitch;
 556         struct mlx5_core_sriov  sriov;
 557         unsigned long           pci_dev_data;
 558         struct mlx5_fc_stats            fc_stats;
 559         struct mlx5_rl_table            rl_table;
 560 };
 561
 562 enum mlx5_device_state {
 563         MLX5_DEVICE_STATE_UP,
 564         MLX5_DEVICE_STATE_INTERNAL_ERROR,
 565 };
 566
 567 enum mlx5_interface_state {
 568         MLX5_INTERFACE_STATE_DOWN = BIT(0),
 569         MLX5_INTERFACE_STATE_UP = BIT(1),
 570         MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
 571 };
 572
 573 enum mlx5_pci_status {
 574         MLX5_PCI_STATUS_DISABLED,
 575         MLX5_PCI_STATUS_ENABLED,
 576 };
 577
 578 struct mlx5_td {
 579         struct list_head tirs_list;
 580         u32              tdn;
 581 };
 582
 583 struct mlx5e_resources {
 584         struct mlx5_uar            cq_uar;
 585         u32                        pdn;
 586         struct mlx5_td             td;
 587         struct mlx5_core_mkey      mkey;
 588 };
 589
 590 struct mlx5_core_dev {
 591         struct pci_dev         *pdev;
 592         /* sync pci state */
 593         struct mutex            pci_status_mutex;
 594         enum mlx5_pci_status    pci_status;
 595         u8                      rev_id;
 596         char                    board_id[MLX5_BOARD_ID_LEN];
 597         struct mlx5_cmd         cmd;
 598         struct mlx5_port_caps   port_caps[MLX5_MAX_PORTS];
 599         u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 600         u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 601         phys_addr_t             iseg_base;
 602         struct mlx5_init_seg __iomem *iseg;
 603         enum mlx5_device_state  state;
 604         /* sync interface state */
 605         struct mutex            intf_state_mutex;
 606         unsigned long           intf_state;
 607         void                    (*event) (struct mlx5_core_dev *dev,
 608                                           enum mlx5_dev_event event,
 609                                           unsigned long param);
 610         struct mlx5_priv        priv;
 611         struct mlx5_profile     *profile;
 612         atomic_t                num_qps;
 613         u32                     issi;
 614         struct mlx5e_resources  mlx5e_res;
 615 #ifdef CONFIG_RFS_ACCEL
 616         struct cpu_rmap         *rmap;
 617 #endif
 618 };
 619
 620 struct mlx5_db {
 621         __be32                  *db;
 622         union {
 623                 struct mlx5_db_pgdir            *pgdir;
 624                 struct mlx5_ib_user_db_page     *user_page;
 625         }                       u;
 626         dma_addr_t              dma;
 627         int                     index;
 628 };
 629
 630 enum {
 631         MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
 632 };
 633
 634 enum {
 635         MLX5_COMP_EQ_SIZE = 1024,
 636 };
 637
 638 enum {
 639         MLX5_PTYS_IB = 1 << 0,
 640         MLX5_PTYS_EN = 1 << 2,
 641 };
 642
 643 struct mlx5_db_pgdir {
 644         struct list_head        list;
 645         DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
 646         __be32                 *db_page;
 647         dma_addr_t              db_dma;
 648 };
 649
 650 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
 651
 652 struct mlx5_cmd_work_ent {
 653         struct mlx5_cmd_msg    *in;
 654         struct mlx5_cmd_msg    *out;
 655         void                   *uout;
 656         int                     uout_size;
 657         mlx5_cmd_cbk_t          callback;
 658         struct delayed_work     cb_timeout_work;
 659         void                   *context;
 660         int                     idx;
 661         struct completion       done;
 662         struct mlx5_cmd        *cmd;
 663         struct work_struct      work;
 664         struct mlx5_cmd_layout *lay;
 665         int                     ret;
 666         int                     page_queue;
 667         u8                      status;
 668         u8                      token;
 669         u64                     ts1;
 670         u64                     ts2;
 671         u16                     op;
 672 };
 673
 674 struct mlx5_pas {
 675         u64     pa;
 676         u8      log_sz;
 677 };
 678
 679 enum port_state_policy {
 680         MLX5_POLICY_DOWN        = 0,
 681         MLX5_POLICY_UP          = 1,
 682         MLX5_POLICY_FOLLOW      = 2,
 683         MLX5_POLICY_INVALID     = 0xffffffff
 684 };
 685
 686 enum phy_port_state {
 687         MLX5_AAA_111
 688 };
 689
 690 struct mlx5_hca_vport_context {
 691         u32                     field_select;
 692         bool                    sm_virt_aware;
 693         bool                    has_smi;
 694         bool                    has_raw;
 695         enum port_state_policy  policy;
 696         enum phy_port_state     phys_state;
 697         enum ib_port_state      vport_state;
 698         u8                      port_physical_state;
 699         u64                     sys_image_guid;
 700         u64                     port_guid;
 701         u64                     node_guid;
 702         u32                     cap_mask1;
 703         u32                     cap_mask1_perm;
 704         u32                     cap_mask2;
 705         u32                     cap_mask2_perm;
 706         u16                     lid;
 707         u8                      init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
 708         u8                      lmc;
 709         u8                      subnet_timeout;
 710         u16                     sm_lid;
 711         u8                      sm_sl;
 712         u16                     qkey_violation_counter;
 713         u16                     pkey_violation_counter;
 714         bool                    grh_required;
 715 };
 716
 717 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
 718 {
 719                 return buf->direct.buf + offset;
 720 }
 721
 722 extern struct workqueue_struct *mlx5_core_wq;
 723
 724 #define STRUCT_FIELD(header, field) \
 725         .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
 726         .struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
 727
 728 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
 729 {
 730         return pci_get_drvdata(pdev);
 731 }
 732
 733 extern struct dentry *mlx5_debugfs_root;
 734
 735 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
 736 {
 737         return ioread32be(&dev->iseg->fw_rev) & 0xffff;
 738 }
 739
 740 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
 741 {
 742         return ioread32be(&dev->iseg->fw_rev) >> 16;
 743 }
 744
 745 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
 746 {
 747         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
 748 }
 749
 750 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
 751 {
 752         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
 753 }
 754
 755 static inline void *mlx5_vzalloc(unsigned long size)
 756 {
 757         void *rtn;
 758
 759         rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
 760         if (!rtn)
 761                 rtn = vzalloc(size);
 762         return rtn;
 763 }
 764
 765 static inline u32 mlx5_base_mkey(const u32 key)
 766 {
 767         return key & 0xffffff00u;
 768 }
 769
 770 int mlx5_cmd_init(struct mlx5_core_dev *dev);
 771 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
 772 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 773 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
 774 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
 775 int mlx5_cmd_status_to_err_v2(void *ptr);
 776 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
 777 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 778                   int out_size);
 779 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
 780                      void *out, int out_size, mlx5_cmd_cbk_t callback,
 781                      void *context);
 782 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
 783 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
 784 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
 785 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
 786 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
 787                        bool map_wc);
 788 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
 789 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
 790 int mlx5_health_init(struct mlx5_core_dev *dev);
 791 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
 792 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
 793 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
 794                         struct mlx5_buf *buf, int node);
 795 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
 796 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
 797 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 798                                                       gfp_t flags, int npages);
 799 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 800                                  struct mlx5_cmd_mailbox *head);
 801 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 802                          struct mlx5_srq_attr *in);
 803 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
 804 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 805                         struct mlx5_srq_attr *out);
 806 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 807                       u16 lwm, int is_srq);
 808 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
 809 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
 810 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
 811                           struct mlx5_core_mkey *mkey,
 812                           struct mlx5_create_mkey_mbox_in *in, int inlen,
 813                           mlx5_cmd_cbk_t callback, void *context,
 814                           struct mlx5_create_mkey_mbox_out *out);
 815 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
 816                            struct mlx5_core_mkey *mkey);
 817 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
 818                          struct mlx5_query_mkey_mbox_out *out, int outlen);
 819 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
 820                              u32 *mkey);
 821 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
 822 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
 823 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
 824                       u16 opmod, u8 port);
 825 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
 826 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
 827 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
 828 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
 829 int mlx5_sriov_init(struct mlx5_core_dev *dev);
 830 int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
 831 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
 832                                  s32 npages);
 833 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
 834 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
 835 void mlx5_register_debugfs(void);
 836 void mlx5_unregister_debugfs(void);
 837 int mlx5_eq_init(struct mlx5_core_dev *dev);
 838 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
 839 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
 840 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
 841 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
 842 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 843 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
 844 #endif
 845 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
 846 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
 847 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
 848 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
 849 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 850                        int nent, u64 mask, const char *name, struct mlx5_uar *uar);
 851 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 852 int mlx5_start_eqs(struct mlx5_core_dev *dev);
 853 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
 854 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
 855                     unsigned int *irqn);
 856 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 857 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 858
 859 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
 860 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
 861 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
 862                          int size_in, void *data_out, int size_out,
 863                          u16 reg_num, int arg, int write);
 864
 865 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 866 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 867 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 868                        struct mlx5_query_eq_mbox_out *out, int outlen);
 869 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
 870 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
 871 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
 872 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
 873 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
 874 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
 875                        int node);
 876 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
 877
 878 const char *mlx5_command_str(int command);
 879 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
 880 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
 881 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
 882                          int npsvs, u32 *sig_index);
 883 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
 884 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
 885 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
 886                         struct mlx5_odp_caps *odp_caps);
 887 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
 888                              u8 port_num, void *out, size_t sz);
 889
 890 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
 891 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
 892 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
 893 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
 894 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
 895
 896 static inline int fw_initializing(struct mlx5_core_dev *dev)
 897 {
 898         return ioread32be(&dev->iseg->initializing) >> 31;
 899 }
 900
 901 static inline u32 mlx5_mkey_to_idx(u32 mkey)
 902 {
 903         return mkey >> 8;
 904 }
 905
 906 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
 907 {
 908         return mkey_idx << 8;
 909 }
 910
 911 static inline u8 mlx5_mkey_variant(u32 mkey)
 912 {
 913         return mkey & 0xff;
 914 }
 915
 916 enum {
 917         MLX5_PROF_MASK_QP_SIZE          = (u64)1 << 0,
 918         MLX5_PROF_MASK_MR_CACHE         = (u64)1 << 1,
 919 };
 920
 921 enum {
 922         MAX_MR_CACHE_ENTRIES    = 16,
 923 };
 924
 925 enum {
 926         MLX5_INTERFACE_PROTOCOL_IB  = 0,
 927         MLX5_INTERFACE_PROTOCOL_ETH = 1,
 928 };
 929
 930 struct mlx5_interface {
 931         void *                  (*add)(struct mlx5_core_dev *dev);
 932         void                    (*remove)(struct mlx5_core_dev *dev, void *context);
 933         void                    (*event)(struct mlx5_core_dev *dev, void *context,
 934                                          enum mlx5_dev_event event, unsigned long param);
 935         void *                  (*get_dev)(void *context);
 936         int                     protocol;
 937         struct list_head        list;
 938 };
 939
 940 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
 941 int mlx5_register_interface(struct mlx5_interface *intf);
 942 void mlx5_unregister_interface(struct mlx5_interface *intf);
 943 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
 944
 945 struct mlx5_profile {
 946         u64     mask;
 947         u8      log_max_qp;
 948         struct {
 949                 int     size;
 950                 int     limit;
 951         } mr_cache[MAX_MR_CACHE_ENTRIES];
 952 };
 953
 954 enum {
 955         MLX5_PCI_DEV_IS_VF              = 1 << 0,
 956 };
 957
 958 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
 959 {
 960         return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
 961 }
 962
 963 static inline int mlx5_get_gid_table_len(u16 param)
 964 {
 965         if (param > 4) {
 966                 pr_warn("gid table length is zero\n");
 967                 return 0;
 968         }
 969
 970         return 8 * (1 << param);
 971 }
 972
 973 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
 974 {
 975         return !!(dev->priv.rl_table.max_size);
 976 }
 977
 978 enum {
 979         MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
 980 };
 981
 982 #endif /* MLX5_DRIVER_H */